Thomas Chou | c960b13 | 2010-04-20 12:49:52 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Altera 10/100/1000 triple speed ethernet mac |
| 3 | * |
| 4 | * Copyright (C) 2008 Altera Corporation. |
| 5 | * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License version 2 as |
| 9 | * published by the Free Software Foundation. |
| 10 | */ |
| 11 | #ifndef _ALTERA_TSE_H_ |
| 12 | #define _ALTERA_TSE_H_ |
| 13 | |
| 14 | #define __packed_1_ __attribute__ ((packed, aligned(1))) |
| 15 | |
Thomas Chou | c960b13 | 2010-04-20 12:49:52 +0800 | [diff] [blame] | 16 | /* SGDMA Stuff */ |
Thomas Chou | c960b13 | 2010-04-20 12:49:52 +0800 | [diff] [blame] | 17 | #define ALT_SGDMA_STATUS_BUSY_MSK (0x00000010) |
| 18 | |
Thomas Chou | c960b13 | 2010-04-20 12:49:52 +0800 | [diff] [blame] | 19 | #define ALT_SGDMA_CONTROL_RUN_MSK (0x00000020) |
| 20 | #define ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK (0x00000040) |
Thomas Chou | c960b13 | 2010-04-20 12:49:52 +0800 | [diff] [blame] | 21 | #define ALT_SGDMA_CONTROL_SOFTWARERESET_MSK (0x00010000) |
Thomas Chou | c960b13 | 2010-04-20 12:49:52 +0800 | [diff] [blame] | 22 | |
Thomas Chou | c960b13 | 2010-04-20 12:49:52 +0800 | [diff] [blame] | 23 | /* |
| 24 | * Descriptor control bit masks & offsets |
| 25 | * |
| 26 | * Note: The control byte physically occupies bits [31:24] in memory. |
| 27 | * The following bit-offsets are expressed relative to the LSB of |
| 28 | * the control register bitfield. |
| 29 | */ |
| 30 | #define ALT_SGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MSK (0x00000001) |
| 31 | #define ALT_SGDMA_DESCRIPTOR_CONTROL_READ_FIXED_ADDRESS_MSK (0x00000002) |
| 32 | #define ALT_SGDMA_DESCRIPTOR_CONTROL_WRITE_FIXED_ADDRESS_MSK (0x00000004) |
Thomas Chou | c960b13 | 2010-04-20 12:49:52 +0800 | [diff] [blame] | 33 | #define ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK (0x00000080) |
| 34 | |
| 35 | /* |
| 36 | * Descriptor status bit masks & offsets |
| 37 | * |
| 38 | * Note: The status byte physically occupies bits [23:16] in memory. |
| 39 | * The following bit-offsets are expressed relative to the LSB of |
| 40 | * the status register bitfield. |
| 41 | */ |
Thomas Chou | c960b13 | 2010-04-20 12:49:52 +0800 | [diff] [blame] | 42 | #define ALT_SGDMA_DESCRIPTOR_STATUS_TERMINATED_BY_EOP_MSK (0x00000080) |
Thomas Chou | c960b13 | 2010-04-20 12:49:52 +0800 | [diff] [blame] | 43 | |
| 44 | /* |
| 45 | * The SGDMA controller buffer descriptor allocates |
| 46 | * 64 bits for each address. To support ANSI C, the |
| 47 | * struct implementing a descriptor places 32-bits |
| 48 | * of padding directly above each address; each pad must |
| 49 | * be cleared when initializing a descriptor. |
| 50 | */ |
| 51 | |
| 52 | /* |
| 53 | * Buffer Descriptor data structure |
| 54 | * |
| 55 | */ |
| 56 | struct alt_sgdma_descriptor { |
Thomas Chou | 96fa1e4 | 2015-10-22 15:29:11 +0800 | [diff] [blame] | 57 | unsigned int source; /* the address of data to be read. */ |
Thomas Chou | c960b13 | 2010-04-20 12:49:52 +0800 | [diff] [blame] | 58 | unsigned int source_pad; |
| 59 | |
Thomas Chou | 96fa1e4 | 2015-10-22 15:29:11 +0800 | [diff] [blame] | 60 | unsigned int destination; /* the address to write data */ |
Thomas Chou | c960b13 | 2010-04-20 12:49:52 +0800 | [diff] [blame] | 61 | unsigned int destination_pad; |
| 62 | |
Thomas Chou | 96fa1e4 | 2015-10-22 15:29:11 +0800 | [diff] [blame] | 63 | unsigned int next; /* the next descriptor in the list. */ |
Thomas Chou | c960b13 | 2010-04-20 12:49:52 +0800 | [diff] [blame] | 64 | unsigned int next_pad; |
| 65 | |
| 66 | unsigned short bytes_to_transfer; /* the number of bytes to transfer */ |
| 67 | unsigned char read_burst; |
| 68 | unsigned char write_burst; |
| 69 | |
| 70 | unsigned short actual_bytes_transferred;/* bytes transferred by DMA */ |
| 71 | unsigned char descriptor_status; |
| 72 | unsigned char descriptor_control; |
| 73 | |
| 74 | } __packed_1_; |
| 75 | |
| 76 | /* SG-DMA Control/Status Slave registers map */ |
| 77 | |
| 78 | struct alt_sgdma_registers { |
| 79 | unsigned int status; |
| 80 | unsigned int status_pad[3]; |
| 81 | unsigned int control; |
| 82 | unsigned int control_pad[3]; |
| 83 | unsigned int next_descriptor_pointer; |
| 84 | unsigned int descriptor_pad[3]; |
| 85 | }; |
| 86 | |
| 87 | /* TSE Stuff */ |
| 88 | #define ALTERA_TSE_CMD_TX_ENA_MSK (0x00000001) |
| 89 | #define ALTERA_TSE_CMD_RX_ENA_MSK (0x00000002) |
Thomas Chou | c960b13 | 2010-04-20 12:49:52 +0800 | [diff] [blame] | 90 | #define ALTERA_TSE_CMD_ETH_SPEED_MSK (0x00000008) |
Thomas Chou | c960b13 | 2010-04-20 12:49:52 +0800 | [diff] [blame] | 91 | #define ALTERA_TSE_CMD_HD_ENA_MSK (0x00000400) |
Thomas Chou | c960b13 | 2010-04-20 12:49:52 +0800 | [diff] [blame] | 92 | #define ALTERA_TSE_CMD_SW_RESET_MSK (0x00002000) |
Thomas Chou | c960b13 | 2010-04-20 12:49:52 +0800 | [diff] [blame] | 93 | #define ALTERA_TSE_CMD_ENA_10_MSK (0x02000000) |
Thomas Chou | c960b13 | 2010-04-20 12:49:52 +0800 | [diff] [blame] | 94 | |
Thomas Chou | 96fa1e4 | 2015-10-22 15:29:11 +0800 | [diff] [blame] | 95 | #define ALT_TSE_SW_RESET_TIMEOUT (3 * CONFIG_SYS_HZ) |
| 96 | #define ALT_TSE_SGDMA_BUSY_TIMEOUT (3 * CONFIG_SYS_HZ) |
Thomas Chou | c960b13 | 2010-04-20 12:49:52 +0800 | [diff] [blame] | 97 | |
| 98 | /* MAC register Space */ |
| 99 | |
| 100 | struct alt_tse_mac { |
| 101 | unsigned int megacore_revision; |
| 102 | unsigned int scratch_pad; |
Thomas Chou | 96fa1e4 | 2015-10-22 15:29:11 +0800 | [diff] [blame] | 103 | unsigned int command_config; |
Thomas Chou | c960b13 | 2010-04-20 12:49:52 +0800 | [diff] [blame] | 104 | unsigned int mac_addr_0; |
| 105 | unsigned int mac_addr_1; |
| 106 | unsigned int max_frame_length; |
| 107 | unsigned int pause_quanta; |
| 108 | unsigned int rx_sel_empty_threshold; |
| 109 | unsigned int rx_sel_full_threshold; |
| 110 | unsigned int tx_sel_empty_threshold; |
| 111 | unsigned int tx_sel_full_threshold; |
| 112 | unsigned int rx_almost_empty_threshold; |
| 113 | unsigned int rx_almost_full_threshold; |
| 114 | unsigned int tx_almost_empty_threshold; |
| 115 | unsigned int tx_almost_full_threshold; |
| 116 | unsigned int mdio_phy0_addr; |
| 117 | unsigned int mdio_phy1_addr; |
| 118 | |
Thomas Chou | fba54a5 | 2015-11-06 09:36:06 +0800 | [diff] [blame^] | 119 | unsigned int reserved1[0x29]; |
Thomas Chou | c960b13 | 2010-04-20 12:49:52 +0800 | [diff] [blame] | 120 | |
| 121 | /*FIFO control register. */ |
Thomas Chou | 96fa1e4 | 2015-10-22 15:29:11 +0800 | [diff] [blame] | 122 | unsigned int tx_cmd_stat; |
| 123 | unsigned int rx_cmd_stat; |
Thomas Chou | c960b13 | 2010-04-20 12:49:52 +0800 | [diff] [blame] | 124 | |
Thomas Chou | fba54a5 | 2015-11-06 09:36:06 +0800 | [diff] [blame^] | 125 | unsigned int reserved2[0x44]; |
Thomas Chou | c960b13 | 2010-04-20 12:49:52 +0800 | [diff] [blame] | 126 | |
| 127 | /*Registers 0 to 31 within PHY device 0/1 */ |
Thomas Chou | 96fa1e4 | 2015-10-22 15:29:11 +0800 | [diff] [blame] | 128 | unsigned int mdio_phy0[0x20]; |
| 129 | unsigned int mdio_phy1[0x20]; |
Thomas Chou | c960b13 | 2010-04-20 12:49:52 +0800 | [diff] [blame] | 130 | |
| 131 | /*4 Supplemental MAC Addresses */ |
| 132 | unsigned int supp_mac_addr_0_0; |
| 133 | unsigned int supp_mac_addr_0_1; |
| 134 | unsigned int supp_mac_addr_1_0; |
| 135 | unsigned int supp_mac_addr_1_1; |
| 136 | unsigned int supp_mac_addr_2_0; |
| 137 | unsigned int supp_mac_addr_2_1; |
| 138 | unsigned int supp_mac_addr_3_0; |
| 139 | unsigned int supp_mac_addr_3_1; |
| 140 | |
Thomas Chou | fba54a5 | 2015-11-06 09:36:06 +0800 | [diff] [blame^] | 141 | unsigned int reserved3[0x38]; |
Thomas Chou | c960b13 | 2010-04-20 12:49:52 +0800 | [diff] [blame] | 142 | }; |
| 143 | |
Thomas Chou | c960b13 | 2010-04-20 12:49:52 +0800 | [diff] [blame] | 144 | struct altera_tse_priv { |
Thomas Chou | 96fa1e4 | 2015-10-22 15:29:11 +0800 | [diff] [blame] | 145 | struct alt_tse_mac *mac_dev; |
| 146 | struct alt_sgdma_registers *sgdma_rx; |
| 147 | struct alt_sgdma_registers *sgdma_tx; |
| 148 | unsigned int rx_fifo_depth; |
| 149 | unsigned int tx_fifo_depth; |
| 150 | struct alt_sgdma_descriptor *rx_desc; |
| 151 | struct alt_sgdma_descriptor *tx_desc; |
| 152 | unsigned char *rx_buf; |
Thomas Chou | c960b13 | 2010-04-20 12:49:52 +0800 | [diff] [blame] | 153 | unsigned int phyaddr; |
Thomas Chou | 96fa1e4 | 2015-10-22 15:29:11 +0800 | [diff] [blame] | 154 | unsigned int interface; |
| 155 | struct phy_device *phydev; |
| 156 | struct mii_dev *bus; |
Thomas Chou | c960b13 | 2010-04-20 12:49:52 +0800 | [diff] [blame] | 157 | }; |
| 158 | |
Thomas Chou | c960b13 | 2010-04-20 12:49:52 +0800 | [diff] [blame] | 159 | #endif /* _ALTERA_TSE_H_ */ |