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Wenyou Yang75238f22015-10-30 09:55:52 +08001/*
2 * Copyright (C) 2015 Atmel Corporation
3 * Wenyou.Yang <wenyou.yang@atmel.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#include <common.h>
9#include <atmel_hlcdc.h>
Wenyou Yang0daa2e12016-10-17 09:55:25 +080010#include <dm.h>
11#include <i2c.h>
Wenyou Yang75238f22015-10-30 09:55:52 +080012#include <lcd.h>
13#include <mmc.h>
14#include <net.h>
15#include <netdev.h>
16#include <spi.h>
17#include <version.h>
18#include <asm/io.h>
19#include <asm/arch/at91_common.h>
Wenyou Yang75238f22015-10-30 09:55:52 +080020#include <asm/arch/atmel_pio4.h>
Wenyou Yang37dadbc2016-02-01 18:18:21 +080021#include <asm/arch/atmel_mpddrc.h>
Wenyou Yang75238f22015-10-30 09:55:52 +080022#include <asm/arch/atmel_usba_udc.h>
23#include <asm/arch/atmel_sdhci.h>
24#include <asm/arch/clk.h>
25#include <asm/arch/gpio.h>
26#include <asm/arch/sama5d2.h>
27
28DECLARE_GLOBAL_DATA_PTR;
29
Wenyou Yang75238f22015-10-30 09:55:52 +080030static void board_usb_hw_init(void)
31{
32 atmel_pio4_set_pio_output(AT91_PIO_PORTB, 10, 1);
33}
34
35#ifdef CONFIG_LCD
36vidinfo_t panel_info = {
37 .vl_col = 480,
38 .vl_row = 272,
39 .vl_clk = 9000000,
40 .vl_bpix = LCD_BPP,
41 .vl_tft = 1,
42 .vl_hsync_len = 41,
43 .vl_left_margin = 2,
44 .vl_right_margin = 2,
45 .vl_vsync_len = 11,
46 .vl_upper_margin = 2,
47 .vl_lower_margin = 2,
48 .mmio = ATMEL_BASE_LCDC,
49};
50
51/* No power up/down pin for the LCD pannel */
52void lcd_enable(void) { /* Empty! */ }
53void lcd_disable(void) { /* Empty! */ }
54
55unsigned int has_lcdc(void)
56{
57 return 1;
58}
59
60static void board_lcd_hw_init(void)
61{
62 atmel_pio4_set_a_periph(AT91_PIO_PORTC, 28, 0); /* LCDPWM */
63 atmel_pio4_set_a_periph(AT91_PIO_PORTC, 29, 0); /* LCDDISP */
64 atmel_pio4_set_a_periph(AT91_PIO_PORTC, 30, 0); /* LCDVSYNC */
65 atmel_pio4_set_a_periph(AT91_PIO_PORTC, 31, 0); /* LCDHSYNC */
66 atmel_pio4_set_a_periph(AT91_PIO_PORTD, 0, 0); /* LCDPCK */
67 atmel_pio4_set_a_periph(AT91_PIO_PORTD, 1, 0); /* LCDDEN */
68
69 /* LCDDAT0 */
70 /* LCDDAT1 */
71 atmel_pio4_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDDAT2 */
72 atmel_pio4_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDDAT3 */
73 atmel_pio4_set_a_periph(AT91_PIO_PORTC, 12, 0); /* LCDDAT4 */
74 atmel_pio4_set_a_periph(AT91_PIO_PORTC, 13, 0); /* LCDDAT5 */
75 atmel_pio4_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDDAT6 */
76 atmel_pio4_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDDAT7 */
77
78 /* LCDDAT8 */
79 /* LCDDAT9 */
80 atmel_pio4_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDDAT10 */
81 atmel_pio4_set_a_periph(AT91_PIO_PORTC, 17, 0); /* LCDDAT11 */
82 atmel_pio4_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDDAT12 */
83 atmel_pio4_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDDAT13 */
84 atmel_pio4_set_a_periph(AT91_PIO_PORTC, 20, 0); /* LCDDAT14 */
85 atmel_pio4_set_a_periph(AT91_PIO_PORTC, 21, 0); /* LCDDAT15 */
86
87 /* LCDD16 */
88 /* LCDD17 */
89 atmel_pio4_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDDAT18 */
90 atmel_pio4_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDDAT19 */
91 atmel_pio4_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDDAT20 */
92 atmel_pio4_set_a_periph(AT91_PIO_PORTC, 25, 0); /* LCDDAT21 */
93 atmel_pio4_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDDAT22 */
94 atmel_pio4_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDDAT23 */
95
96 at91_periph_clk_enable(ATMEL_ID_LCDC);
97}
98
99#ifdef CONFIG_LCD_INFO
100void lcd_show_board_info(void)
101{
102 ulong dram_size;
103 int i;
104 char temp[32];
105
106 lcd_printf("%s\n", U_BOOT_VERSION);
107 lcd_printf("2015 ATMEL Corp\n");
108 lcd_printf("%s CPU at %s MHz\n", get_cpu_name(),
109 strmhz(temp, get_cpu_clk_rate()));
110
111 dram_size = 0;
112 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
113 dram_size += gd->bd->bi_dram[i].size;
114
115 lcd_printf("%ld MB SDRAM\n", dram_size >> 20);
116}
117#endif /* CONFIG_LCD_INFO */
118#endif /* CONFIG_LCD */
119
120static void board_gmac_hw_init(void)
121{
122 atmel_pio4_set_f_periph(AT91_PIO_PORTB, 14, 0); /* GTXCK */
123 atmel_pio4_set_f_periph(AT91_PIO_PORTB, 15, 0); /* GTXEN */
124 atmel_pio4_set_f_periph(AT91_PIO_PORTB, 16, 0); /* GRXDV */
125 atmel_pio4_set_f_periph(AT91_PIO_PORTB, 17, 0); /* GRXER */
126 atmel_pio4_set_f_periph(AT91_PIO_PORTB, 18, 0); /* GRX0 */
127 atmel_pio4_set_f_periph(AT91_PIO_PORTB, 19, 0); /* GRX1 */
128 atmel_pio4_set_f_periph(AT91_PIO_PORTB, 20, 0); /* GTX0 */
129 atmel_pio4_set_f_periph(AT91_PIO_PORTB, 21, 0); /* GTX1 */
130 atmel_pio4_set_f_periph(AT91_PIO_PORTB, 22, 0); /* GMDC */
131 atmel_pio4_set_f_periph(AT91_PIO_PORTB, 23, 0); /* GMDIO */
132
133 at91_periph_clk_enable(ATMEL_ID_GMAC);
134}
135
Wenyou Yang75238f22015-10-30 09:55:52 +0800136static void board_uart1_hw_init(void)
137{
138 atmel_pio4_set_a_periph(AT91_PIO_PORTD, 2, 1); /* URXD1 */
139 atmel_pio4_set_a_periph(AT91_PIO_PORTD, 3, 0); /* UTXD1 */
140
141 at91_periph_clk_enable(ATMEL_ID_UART1);
142}
143
144int board_early_init_f(void)
145{
Wenyou Yang75238f22015-10-30 09:55:52 +0800146 board_uart1_hw_init();
147
148 return 0;
149}
150
151int board_init(void)
152{
153 /* address of boot parameters */
154 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
155
Wenyou Yang75238f22015-10-30 09:55:52 +0800156#ifdef CONFIG_MACB
157 board_gmac_hw_init();
158#endif
159#ifdef CONFIG_LCD
160 board_lcd_hw_init();
161#endif
162#ifdef CONFIG_CMD_USB
163 board_usb_hw_init();
164#endif
165#ifdef CONFIG_USB_GADGET_ATMEL_USBA
166 at91_udp_hw_init();
167#endif
168
169 return 0;
170}
171
172int dram_init(void)
173{
174 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
175 CONFIG_SYS_SDRAM_SIZE);
176 return 0;
177}
178
179int board_eth_init(bd_t *bis)
180{
181 int rc = 0;
182
183#ifdef CONFIG_MACB
184 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC, 0x00);
185#endif
186
187#ifdef CONFIG_USB_GADGET_ATMEL_USBA
188 usba_udc_probe(&pdata);
189#ifdef CONFIG_USB_ETH_RNDIS
190 usb_eth_initialize(bis);
191#endif
192#endif
193
194 return rc;
195}
Wenyou Yang37dadbc2016-02-01 18:18:21 +0800196
Wenyou Yang0daa2e12016-10-17 09:55:25 +0800197#ifdef CONFIG_CMD_I2C
198static int set_ethaddr_from_eeprom(void)
199{
200 const int ETH_ADDR_LEN = 6;
201 unsigned char ethaddr[ETH_ADDR_LEN];
202 const char *ETHADDR_NAME = "ethaddr";
203 struct udevice *bus, *dev;
204
205 if (getenv(ETHADDR_NAME))
206 return 0;
207
208 if (uclass_get_device_by_seq(UCLASS_I2C, 1, &bus)) {
209 printf("Cannot find I2C bus 1\n");
210 return -1;
211 }
212
213 if (dm_i2c_probe(bus, AT24MAC_ADDR, 0, &dev)) {
214 printf("Failed to probe I2C chip\n");
215 return -1;
216 }
217
218 if (dm_i2c_read(dev, AT24MAC_REG, ethaddr, ETH_ADDR_LEN)) {
219 printf("Failed to read ethernet address from EEPROM\n");
220 return -1;
221 }
222
223 if (!is_valid_ethaddr(ethaddr)) {
224 printf("The ethernet address read from EEPROM is not valid!\n");
225 return -1;
226 }
227
228 return eth_setenv_enetaddr(ETHADDR_NAME, ethaddr);
229}
230#else
231static int set_ethaddr_from_eeprom(void)
232{
233 return 0;
234}
235#endif
236
237#ifdef CONFIG_MISC_INIT_R
238int misc_init_r(void)
239{
240 set_ethaddr_from_eeprom();
241
242 return 0;
243}
244#endif
245
Wenyou Yang37dadbc2016-02-01 18:18:21 +0800246/* SPL */
247#ifdef CONFIG_SPL_BUILD
248void spl_board_init(void)
249{
Wenyou Yang37dadbc2016-02-01 18:18:21 +0800250}
251
252static void ddrc_conf(struct atmel_mpddrc_config *ddrc)
253{
254 ddrc->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR3_SDRAM);
255
256 ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
257 ATMEL_MPDDRC_CR_NR_ROW_14 |
258 ATMEL_MPDDRC_CR_CAS_DDR_CAS5 |
259 ATMEL_MPDDRC_CR_DIC_DS |
260 ATMEL_MPDDRC_CR_DIS_DLL |
261 ATMEL_MPDDRC_CR_NB_8BANKS |
262 ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
263 ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
264
265 ddrc->rtr = 0x511;
266
267 ddrc->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
268 3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
269 4 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
270 9 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
271 3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
272 4 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
273 4 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
274 4 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
275
276 ddrc->tpr1 = (27 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET |
277 29 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
278 0 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
279 3 << ATMEL_MPDDRC_TPR1_TXP_OFFSET);
280
281 ddrc->tpr2 = (0 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET |
282 0 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
283 0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
284 4 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
285 7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET);
286}
287
288void mem_init(void)
289{
290 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
291 struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
292 struct atmel_mpddrc_config ddrc_config;
293 u32 reg;
294
295 ddrc_conf(&ddrc_config);
296
297 at91_periph_clk_enable(ATMEL_ID_MPDDRC);
298 writel(AT91_PMC_DDR, &pmc->scer);
299
300 reg = readl(&mpddrc->io_calibr);
301 reg &= ~ATMEL_MPDDRC_IO_CALIBR_RDIV;
302 reg |= ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55;
303 reg &= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO;
304 reg |= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(100);
305 writel(reg, &mpddrc->io_calibr);
306
307 writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_TWO_CYCLE,
308 &mpddrc->rd_data_path);
309
310 ddr3_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddrc_config);
311
312 writel(0x3, &mpddrc->cal_mr4);
313 writel(64, &mpddrc->tim_cal);
314}
315
316void at91_pmc_init(void)
317{
318 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
319 u32 tmp;
320
321 tmp = AT91_PMC_PLLAR_29 |
322 AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
323 AT91_PMC_PLLXR_MUL(82) |
324 AT91_PMC_PLLXR_DIV(1);
325 at91_plla_init(tmp);
326
327 writel(0x0 << 8, &pmc->pllicpr);
328
329 tmp = AT91_PMC_MCKR_H32MXDIV |
330 AT91_PMC_MCKR_PLLADIV_2 |
331 AT91_PMC_MCKR_MDIV_3 |
332 AT91_PMC_MCKR_CSS_PLLA;
333 at91_mck_init(tmp);
334}
335#endif