| Gregory CLEMENT | 6787c1e | 2018-12-14 16:16:49 +0100 | [diff] [blame] | 1 | // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| 2 | /* |
| 3 | * Copyright (c) 2018 Microsemi Corporation |
| 4 | */ |
| 5 | |
| 6 | / { |
| 7 | #address-cells = <1>; |
| 8 | #size-cells = <1>; |
| 9 | compatible = "mscc,ocelot"; |
| 10 | |
| 11 | cpus { |
| 12 | #address-cells = <1>; |
| 13 | #size-cells = <0>; |
| 14 | |
| 15 | cpu@0 { |
| 16 | compatible = "mips,mips24KEc"; |
| 17 | device_type = "cpu"; |
| 18 | clocks = <&cpu_clk>; |
| 19 | reg = <0>; |
| 20 | }; |
| 21 | }; |
| 22 | |
| 23 | aliases { |
| 24 | serial0 = &uart0; |
| 25 | }; |
| 26 | |
| 27 | cpuintc: interrupt-controller@0 { |
| 28 | #address-cells = <0>; |
| 29 | #interrupt-cells = <1>; |
| 30 | interrupt-controller; |
| 31 | compatible = "mti,cpu-interrupt-controller"; |
| 32 | }; |
| 33 | |
| 34 | cpu_clk: cpu-clock { |
| 35 | compatible = "fixed-clock"; |
| 36 | #clock-cells = <0>; |
| 37 | clock-frequency = <500000000>; |
| 38 | }; |
| 39 | |
| 40 | ahb_clk: ahb-clk { |
| 41 | compatible = "fixed-clock"; |
| 42 | #clock-cells = <0>; |
| 43 | clock-frequency = <250000000>; |
| 44 | }; |
| 45 | |
| 46 | ahb { |
| 47 | compatible = "simple-bus"; |
| 48 | #address-cells = <1>; |
| 49 | #size-cells = <1>; |
| 50 | ranges = <0 0x70000000 0x2000000>; |
| 51 | |
| 52 | interrupt-parent = <&intc>; |
| 53 | |
| 54 | cpu_ctrl: syscon@0 { |
| 55 | compatible = "mscc,ocelot-cpu-syscon", "syscon"; |
| 56 | reg = <0x0 0x2c>; |
| 57 | }; |
| 58 | |
| 59 | intc: interrupt-controller@70 { |
| 60 | compatible = "mscc,ocelot-icpu-intr"; |
| 61 | reg = <0x70 0x70>; |
| 62 | #interrupt-cells = <1>; |
| 63 | interrupt-controller; |
| 64 | interrupt-parent = <&cpuintc>; |
| 65 | interrupts = <2>; |
| 66 | }; |
| 67 | |
| 68 | uart0: serial@100000 { |
| 69 | pinctrl-0 = <&uart_pins>; |
| 70 | pinctrl-names = "default"; |
| 71 | compatible = "ns16550a"; |
| 72 | reg = <0x100000 0x20>; |
| 73 | interrupts = <6>; |
| 74 | clocks = <&ahb_clk>; |
| 75 | reg-io-width = <4>; |
| 76 | reg-shift = <2>; |
| 77 | |
| 78 | status = "disabled"; |
| 79 | }; |
| 80 | |
| 81 | uart2: serial@100800 { |
| 82 | pinctrl-0 = <&uart2_pins>; |
| 83 | pinctrl-names = "default"; |
| 84 | compatible = "ns16550a"; |
| 85 | reg = <0x100800 0x20>; |
| 86 | interrupts = <7>; |
| 87 | clocks = <&ahb_clk>; |
| 88 | reg-io-width = <4>; |
| 89 | reg-shift = <2>; |
| 90 | |
| 91 | status = "disabled"; |
| 92 | }; |
| 93 | |
| 94 | spi0: spi-master@101000 { |
| 95 | #address-cells = <1>; |
| 96 | #size-cells = <0>; |
| 97 | compatible = "snps,dw-apb-ssi"; |
| 98 | reg = <0x101000 0x40>; |
| 99 | num-chipselect = <4>; |
| 100 | bus-num = <0>; |
| 101 | reg-io-width = <4>; |
| 102 | reg-shift = <2>; |
| 103 | spi-max-frequency = <18000000>; /* input clock */ |
| 104 | clocks = <&ahb_clk>; |
| 105 | |
| 106 | status = "disabled"; |
| 107 | }; |
| 108 | |
| 109 | reset@1070008 { |
| 110 | compatible = "mscc,ocelot-chip-reset"; |
| 111 | reg = <0x1070008 0x4>; |
| 112 | }; |
| 113 | |
| 114 | gpio: pinctrl@1070034 { |
| 115 | compatible = "mscc,ocelot-pinctrl"; |
| 116 | reg = <0x1070034 0x68>; |
| 117 | gpio-controller; |
| 118 | #gpio-cells = <2>; |
| 119 | gpio-ranges = <&gpio 0 0 22>; |
| 120 | |
| 121 | uart_pins: uart-pins { |
| 122 | pins = "GPIO_6", "GPIO_7"; |
| 123 | function = "uart"; |
| 124 | }; |
| 125 | |
| 126 | uart2_pins: uart2-pins { |
| 127 | pins = "GPIO_12", "GPIO_13"; |
| 128 | function = "uart2"; |
| 129 | }; |
| 130 | |
| 131 | spi_cs1_pin: spi-cs1-pin { |
| 132 | pins = "GPIO_8"; |
| 133 | function = "si"; |
| 134 | }; |
| 135 | |
| 136 | spi_cs2_pin: spi-cs2-pin { |
| 137 | pins = "GPIO_9"; |
| 138 | function = "si"; |
| 139 | }; |
| 140 | |
| 141 | spi_cs3_pin: spi-cs3-pin { |
| 142 | pins = "GPIO_16"; |
| 143 | function = "si"; |
| 144 | }; |
| 145 | |
| 146 | spi_cs4_pin: spi-cs4-pin { |
| 147 | pins = "GPIO_17"; |
| 148 | function = "si"; |
| 149 | }; |
| 150 | }; |
| 151 | }; |
| 152 | }; |