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wdenk9e3f8cd2002-09-15 14:08:13 +00001/*
wdenk414eec32005-04-02 22:37:54 +00002 * (C) Copyright 2001-2005
wdenk9e3f8cd2002-09-15 14:08:13 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31#include <mpc8xx_irq.h>
32
33/*
34 * High Level Configuration Options
35 * (easy to change)
36 */
37#define CONFIG_MPC860 1
38#define CONFIG_MPC860T 1
39#define CONFIG_ICU862 1
40#define CONFIG_MPC862 1
41
Wolfgang Denk2ae18242010-10-06 09:05:45 +020042#define CONFIG_SYS_TEXT_BASE 0x40F00000
43
wdenk9e3f8cd2002-09-15 14:08:13 +000044#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
45#undef CONFIG_8xx_CONS_SMC2
46#undef CONFIG_8xx_CONS_NONE
47#define CONFIG_BAUDRATE 9600
48#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
49
50#ifdef CONFIG_100MHz
51#define MPC8XX_FACT 24 /* Multiply by 24 */
52#define MPC8XX_XIN 4165000 /* 4.165 MHz in */
53#define CONFIG_8xx_GCLK_FREQ (MPC8XX_FACT * MPC8XX_XIN)
54 /* define if cant' use get_gclk_freq */
55#else
56#if 1 /* for 50MHz version of processor */
57#define MPC8XX_FACT 12 /* Multiply by 12 */
58#define MPC8XX_XIN 4000000 /* 4 MHz in */
59#define CONFIG_8xx_GCLK_FREQ 48000000 /* define if cant use get_gclk_freq */
60#else /* for 80MHz version of processor */
61#define MPC8XX_FACT 20 /* Multiply by 20 */
62#define MPC8XX_XIN 4000000 /* 4 MHz in */
63#define CONFIG_8xx_GCLK_FREQ 80000000 /* define if cant use get_gclk_freq */
64#endif
65#endif
66
wdenk9e3f8cd2002-09-15 14:08:13 +000067#if 0
68#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
69#else
70#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
71#endif
72
Wolfgang Denk32bf3d12008-03-03 12:16:44 +010073#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
wdenk9e3f8cd2002-09-15 14:08:13 +000074
75#undef CONFIG_BOOTARGS
76#define CONFIG_BOOTCOMMAND \
Wolfgang Denk53677ef2008-05-20 16:00:29 +020077 "bootp;" \
78 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
79 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
wdenk9e3f8cd2002-09-15 14:08:13 +000080 "bootm"
81
82#undef CONFIG_WATCHDOG /* watchdog disabled */
83
84#define CONFIG_STATUS_LED 1 /* Status LED enabled */
85
Jon Loeliger7be044e2007-07-09 21:24:19 -050086/*
87 * BOOTP options
88 */
89#define CONFIG_BOOTP_SUBNETMASK
90#define CONFIG_BOOTP_GATEWAY
91#define CONFIG_BOOTP_HOSTNAME
92#define CONFIG_BOOTP_BOOTPATH
93#define CONFIG_BOOTP_BOOTFILESIZE
94
wdenk9e3f8cd2002-09-15 14:08:13 +000095
96#undef CONFIG_SCC1_ENET /* disable SCC1 ethernet */
97#define CONFIG_FEC_ENET 1 /* use FEC ethernet */
Marian Balakowicz63ff0042005-10-28 22:30:33 +020098#define CONFIG_MII 1
wdenk9e3f8cd2002-09-15 14:08:13 +000099#if 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200100#define CONFIG_SYS_DISCOVER_PHY 1
wdenk9e3f8cd2002-09-15 14:08:13 +0000101#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200102#undef CONFIG_SYS_DISCOVER_PHY
wdenk9e3f8cd2002-09-15 14:08:13 +0000103#endif
104
105#define CONFIG_MAC_PARTITION
106#define CONFIG_DOS_PARTITION
107
108/* enable I2C and select the hardware/software driver */
109#undef CONFIG_HARD_I2C /* I2C with hardware support */
110#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111# define CONFIG_SYS_I2C_SPEED 50000
112# define CONFIG_SYS_I2C_SLAVE 0xFE
113# define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
114# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
wdenk9e3f8cd2002-09-15 14:08:13 +0000115/*
116 * Software (bit-bang) I2C driver configuration
117 */
118#define PB_SCL 0x00000020 /* PB 26 */
119#define PB_SDA 0x00000010 /* PB 27 */
120
121#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
122#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
123#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
124#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
125#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
126 else immr->im_cpm.cp_pbdat &= ~PB_SDA
127#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
128 else immr->im_cpm.cp_pbdat &= ~PB_SCL
129#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
130
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131#define CONFIG_SYS_EEPROM_X40430 /* Use a Xicor X40430 EEPROM */
132#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 16 bytes page write mode */
wdenk9e3f8cd2002-09-15 14:08:13 +0000133
134#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
135
wdenk9e3f8cd2002-09-15 14:08:13 +0000136
Jon Loeliger348f2582007-07-08 13:46:18 -0500137/*
138 * Command line configuration.
139 */
140#include <config_cmd_default.h>
141
142#define CONFIG_CMD_ASKENV
143#define CONFIG_CMD_DATE
144#define CONFIG_CMD_DHCP
145#define CONFIG_CMD_EEPROM
146#define CONFIG_CMD_I2C
147#define CONFIG_CMD_IDE
148#define CONFIG_CMD_NFS
149#define CONFIG_CMD_SNTP
150
wdenk9e3f8cd2002-09-15 14:08:13 +0000151
152/*
153 * Miscellaneous configurable options
154 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200155#define CONFIG_SYS_LONGHELP /* undef to save memory */
156#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger348f2582007-07-08 13:46:18 -0500157#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200158#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk9e3f8cd2002-09-15 14:08:13 +0000159#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200160#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk9e3f8cd2002-09-15 14:08:13 +0000161#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
163#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
164#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk9e3f8cd2002-09-15 14:08:13 +0000165
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */
167#define CONFIG_SYS_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */
wdenk9e3f8cd2002-09-15 14:08:13 +0000168
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169#define CONFIG_SYS_LOAD_ADDR 0x00100000
wdenk9e3f8cd2002-09-15 14:08:13 +0000170
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200171#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenk9e3f8cd2002-09-15 14:08:13 +0000172
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenk9e3f8cd2002-09-15 14:08:13 +0000174
175/*
176 * Low Level Configuration Settings
177 * (address mappings, register initial values, etc.)
178 * You should know what you are doing if you make changes here.
179 */
180/*-----------------------------------------------------------------------
181 * Internal Memory Mapped Register
182 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183#define CONFIG_SYS_IMMR 0xF0000000
184#define CONFIG_SYS_IMMR_SIZE ((uint)(64 * 1024))
wdenk9e3f8cd2002-09-15 14:08:13 +0000185
186/*-----------------------------------------------------------------------
187 * Definitions for initial stack pointer and data area (in DPRAM)
188 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200189#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200190#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200191#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200192#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200193#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk9e3f8cd2002-09-15 14:08:13 +0000194
195/*-----------------------------------------------------------------------
196 * Start addresses for the final memory configuration
197 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200198 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenk9e3f8cd2002-09-15 14:08:13 +0000199 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200200#define CONFIG_SYS_SDRAM_BASE 0x00000000
201#define CONFIG_SYS_FLASH_BASE 0x40000000
202#define CONFIG_SYS_FLASH_SIZE ((uint)(16 * 1024 * 1024)) /* max 16Mbyte */
wdenk9e3f8cd2002-09-15 14:08:13 +0000203
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200204#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
wdenk9e3f8cd2002-09-15 14:08:13 +0000205
206#if 0
207#if defined(DEBUG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200208#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
wdenk9e3f8cd2002-09-15 14:08:13 +0000209#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
wdenk9e3f8cd2002-09-15 14:08:13 +0000211#endif
212#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
wdenk9e3f8cd2002-09-15 14:08:13 +0000214#endif
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200215#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */
wdenk9e3f8cd2002-09-15 14:08:13 +0000217
218/*
219 * For booting Linux, the board info and command line data
220 * have to be in the first 8 MB of memory, since this is
221 * the maximum mapped by the Linux kernel during initialization.
222 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk9e3f8cd2002-09-15 14:08:13 +0000224/*-----------------------------------------------------------------------
225 * FLASH organization
226 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200227#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
228#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
wdenk9e3f8cd2002-09-15 14:08:13 +0000229
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200230#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
231#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenk9e3f8cd2002-09-15 14:08:13 +0000232
233
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200234#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200235#define CONFIG_ENV_OFFSET 0x00F40000
wdenk9e3f8cd2002-09-15 14:08:13 +0000236
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200237#define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment sector */
238#define CONFIG_ENV_SIZE 0x4000 /* Used Size of Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200239#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
wdenk9e3f8cd2002-09-15 14:08:13 +0000240
241/*-----------------------------------------------------------------------
242 * Cache Configuration
243 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200244#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger348f2582007-07-08 13:46:18 -0500245#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
wdenk9e3f8cd2002-09-15 14:08:13 +0000247#endif
248
249/*-----------------------------------------------------------------------
250 * SYPCR - System Protection Control 11-9
251 * SYPCR can only be written once after reset!
252 *-----------------------------------------------------------------------
253 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
254 */
255#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200256#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenk9e3f8cd2002-09-15 14:08:13 +0000257 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
258#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200259#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
wdenk9e3f8cd2002-09-15 14:08:13 +0000260#endif
261
262/*-----------------------------------------------------------------------
263 * SIUMCR - SIU Module Configuration 11-6
264 *-----------------------------------------------------------------------
265 * PCMCIA config., multi-function pin tri-state
266 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200267#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenk9e3f8cd2002-09-15 14:08:13 +0000268
269/*-----------------------------------------------------------------------
270 * TBSCR - Time Base Status and Control 11-26
271 *-----------------------------------------------------------------------
272 * Clear Reference Interrupt Status, Timebase freezing enabled
273 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200274#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
wdenk9e3f8cd2002-09-15 14:08:13 +0000275
276/*-----------------------------------------------------------------------
277 * PISCR - Periodic Interrupt Status and Control 11-31
278 *-----------------------------------------------------------------------
279 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
280 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200281#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
wdenk9e3f8cd2002-09-15 14:08:13 +0000282
283/*-----------------------------------------------------------------------
284 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
285 *-----------------------------------------------------------------------
286 * set the PLL, the low-power modes and the reset control (15-29)
287 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200288#define CONFIG_SYS_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \
wdenk9e3f8cd2002-09-15 14:08:13 +0000289 PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
290
291/*-----------------------------------------------------------------------
292 * SCCR - System Clock and reset Control Register 15-27
293 *-----------------------------------------------------------------------
294 * Set clock output, timebase and RTC source and divider,
295 * power management and some other internal clocks
296 */
297#ifdef CONFIG_100MHz /* for 100 MHz, external bus is half CPU clock */
298#define SCCR_MASK 0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200299#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_COM00 | SCCR_DFSYNC00 | \
wdenk9e3f8cd2002-09-15 14:08:13 +0000300 SCCR_DFBRG00 | SCCR_DFNL000 | SCCR_DFNH000 | \
301 SCCR_DFLCD000 |SCCR_DFALCD00 | SCCR_EBDF01)
302#else /* up to 50 MHz we use a 1:1 clock */
303#define SCCR_MASK SCCR_EBDF11
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200304#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_COM00 | SCCR_DFSYNC00 | \
wdenk9e3f8cd2002-09-15 14:08:13 +0000305 SCCR_DFBRG00 | SCCR_DFNL000 | SCCR_DFNH000 | \
306 SCCR_DFLCD000 |SCCR_DFALCD00 )
307#endif /* CONFIG_100MHz */
308
309/*-----------------------------------------------------------------------
310 * RCCR - RISC Controller Configuration Register 19-4
311 *-----------------------------------------------------------------------
312 */
313/* +0x09C4 => DRQP = 10 (IDMA requests have lowest priority) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200314#define CONFIG_SYS_RCCR 0x0020
wdenk9e3f8cd2002-09-15 14:08:13 +0000315
316/*-----------------------------------------------------------------------
317 * PCMCIA stuff
318 *-----------------------------------------------------------------------
319 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200320#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
321#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
322#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
323#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
324#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
325#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
326#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
327#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
wdenk9e3f8cd2002-09-15 14:08:13 +0000328
329/*-----------------------------------------------------------------------
330 * PCMCIA Power Switch
331 *
332 * The ICU862 uses a TPS2205 PC-Card Power-Interface Switch to
333 * control the voltages on the PCMCIA slot which is connected to Port B
334 *-----------------------------------------------------------------------
335 */
336 /* Output pins */
337#define TPS2205_VCC5 0x00008000 /* PB.16: 5V Voltage Control */
338#define TPS2205_VCC3 0x00004000 /* PB.17: 3V Voltage Control */
339#define TPS2205_VPP_PGM 0x00002000 /* PB.18: PGM Voltage Control */
340#define TPS2205_VPP_VCC 0x00001000 /* PB.19: VPP Voltage Control */
341#define TPS2205_SHDN 0x00000200 /* PB.22: Shutdown */
342#define TPS2205_OUTPUTS ( TPS2205_VCC5 | TPS2205_VCC3 | \
343 TPS2205_VPP_PGM | TPS2205_VPP_VCC | \
344 TPS2205_SHDN)
345
346 /* Input pins */
347#define TPS2205_OC 0x00000100 /* PB.23: Over-Current */
348#define TPS2205_INPUTS ( TPS2205_OC )
349
350/*-----------------------------------------------------------------------
351 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
352 *-----------------------------------------------------------------------
353 */
354
355#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
356
357#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
358#undef CONFIG_IDE_LED /* LED for ide not supported */
359#undef CONFIG_IDE_RESET /* reset for ide not supported */
360
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200361#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
362#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
wdenk9e3f8cd2002-09-15 14:08:13 +0000363
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200364#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
wdenk9e3f8cd2002-09-15 14:08:13 +0000365
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200366#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
wdenk9e3f8cd2002-09-15 14:08:13 +0000367
368/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200369#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenk9e3f8cd2002-09-15 14:08:13 +0000370
371/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200372#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenk9e3f8cd2002-09-15 14:08:13 +0000373
374/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200375#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
wdenk9e3f8cd2002-09-15 14:08:13 +0000376
377
378 /*-----------------------------------------------------------------------
379 *
380 *-----------------------------------------------------------------------
381 *
382 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200383#define CONFIG_SYS_DER 0
wdenk9e3f8cd2002-09-15 14:08:13 +0000384
385/* Because of the way the 860 starts up and assigns CS0 the
386* entire address space, we have to set the memory controller
387* differently. Normally, you write the option register
388* first, and then enable the chip select by writing the
389* base register. For CS0, you must write the base register
390* first, followed by the option register.
391*/
392
393/*
394 * Init Memory Controller:
395 *
396 * BR0 and OR0 (FLASH)
397 */
398
399#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
400#define FLASH_BASE1_PRELIM 0x0 /* FLASH bank #1 */
401
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200402#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
403#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
wdenk9e3f8cd2002-09-15 14:08:13 +0000404
405/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200406#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
wdenk9e3f8cd2002-09-15 14:08:13 +0000407
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200408#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
wdenk9e3f8cd2002-09-15 14:08:13 +0000409
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200410#define CONFIG_SYS_OR0_PRELIM 0xFF000954 /* Real values for the board */
411#define CONFIG_SYS_BR0_PRELIM 0x40000001 /* Real values for the board */
wdenk9e3f8cd2002-09-15 14:08:13 +0000412
413/*
414 * BR1 and OR1 (SDRAM)
415 */
416#define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank */
417#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
418
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200419#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000800 /* BIH is not set */
wdenk9e3f8cd2002-09-15 14:08:13 +0000420
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200421#define CONFIG_SYS_OR1_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM)
422#define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V)
wdenk9e3f8cd2002-09-15 14:08:13 +0000423
424/*
425 * Memory Periodic Timer Prescaler
426 */
427
428/* periodic timer for refresh */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200429#define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */
wdenk9e3f8cd2002-09-15 14:08:13 +0000430
431/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200432#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
433#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
wdenk9e3f8cd2002-09-15 14:08:13 +0000434
435/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200436#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
437#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
wdenk9e3f8cd2002-09-15 14:08:13 +0000438
439/*
440 * MAMR settings for SDRAM
441 */
442
443/* 8 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200444#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenk9e3f8cd2002-09-15 14:08:13 +0000445 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
446 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
447/* 9 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200448#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenk9e3f8cd2002-09-15 14:08:13 +0000449 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
450 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
451
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200452#define CONFIG_SYS_MAMR 0x13a01114
wdenk9e3f8cd2002-09-15 14:08:13 +0000453
454#ifdef CONFIG_MPC860T
455
456/* Interrupt level assignments.
457*/
458#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */
459
460#endif /* CONFIG_MPC860T */
461
462
463#endif /* __CONFIG_H */