| Simon Glass | 2f3f477 | 2016-03-11 22:07:18 -0700 | [diff] [blame] | 1 | # |
| 2 | # Copyright (C) 2016 Google Inc. |
| 3 | # |
| 4 | # SPDX-License-Identifier: GPL-2.0 |
| 5 | |
| 6 | config INTEL_BROADWELL |
| 7 | bool |
| 8 | select CACHE_MRC_BIN |
| Bin Meng | 5d89b37 | 2017-07-30 06:23:13 -0700 | [diff] [blame] | 9 | select ARCH_EARLY_INIT_R |
| Bin Meng | 1e452b4 | 2017-07-30 06:23:10 -0700 | [diff] [blame] | 10 | imply HAVE_INTEL_ME |
| Bin Meng | 67f99f9 | 2017-07-30 06:23:14 -0700 | [diff] [blame] | 11 | imply ENABLE_MRC_CACHE |
| Bin Meng | 1b15ef9 | 2017-07-30 06:23:19 -0700 | [diff] [blame] | 12 | imply ENV_IS_IN_SPI_FLASH |
| 13 | imply ICH_SPI |
| 14 | imply INTEL_BROADWELL_GPIO |
| 15 | imply SCSI |
| 16 | imply SPI_FLASH |
| Bin Meng | b9342b2 | 2017-07-30 06:23:27 -0700 | [diff] [blame] | 17 | imply USB |
| 18 | imply USB_EHCI_HCD |
| Bin Meng | 1b15ef9 | 2017-07-30 06:23:19 -0700 | [diff] [blame] | 19 | imply VIDEO_BROADWELL_IGD |
| Simon Glass | 2f3f477 | 2016-03-11 22:07:18 -0700 | [diff] [blame] | 20 | |
| 21 | if INTEL_BROADWELL |
| 22 | |
| 23 | config DCACHE_RAM_BASE |
| 24 | default 0xff7c0000 |
| 25 | |
| 26 | config DCACHE_RAM_SIZE |
| 27 | default 0x40000 |
| 28 | |
| 29 | config DCACHE_RAM_MRC_VAR_SIZE |
| 30 | default 0x30000 |
| 31 | |
| 32 | config CPU_SPECIFIC_OPTIONS |
| 33 | def_bool y |
| 34 | select SMM_TSEG |
| 35 | select X86_RAMTEST |
| 36 | |
| 37 | config SMM_TSEG_SIZE |
| 38 | hex |
| 39 | default 0x800000 |
| 40 | |
| 41 | endif |