wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 1 | /* |
Stefan Roese | dbbd125 | 2007-10-05 17:10:59 +0200 | [diff] [blame] | 2 | * (C) Copyright 2000-2007 |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 21 | * MA 02111-1307 USA |
| 22 | */ |
| 23 | |
| 24 | #include <common.h> |
| 25 | #include <watchdog.h> |
Stefan Roese | b36df56 | 2010-09-09 19:18:00 +0200 | [diff] [blame] | 26 | #include <asm/ppc4xx-emac.h> |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 27 | #include <asm/processor.h> |
Stefan Roese | 0988776 | 2010-09-16 14:30:37 +0200 | [diff] [blame] | 28 | #include <asm/ppc4xx-gpio.h> |
Stefan Roese | b36df56 | 2010-09-09 19:18:00 +0200 | [diff] [blame] | 29 | #include <asm/ppc4xx.h> |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 30 | |
Wolfgang Denk | d87080b | 2006-03-31 18:32:53 +0200 | [diff] [blame] | 31 | #if defined(CONFIG_405GP) || defined(CONFIG_405EP) |
| 32 | DECLARE_GLOBAL_DATA_PTR; |
| 33 | #endif |
| 34 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 35 | #ifndef CONFIG_SYS_PLL_RECONFIG |
| 36 | #define CONFIG_SYS_PLL_RECONFIG 0 |
Mike Nuss | f66e2c8 | 2008-02-20 11:54:20 -0500 | [diff] [blame] | 37 | #endif |
| 38 | |
Stefan Roese | fe7cca7 | 2010-05-19 11:13:24 +0200 | [diff] [blame] | 39 | #if defined(CONFIG_440EPX) || \ |
| 40 | defined(CONFIG_460EX) || defined(CONFIG_460GT) |
| 41 | static void reset_with_rli(void) |
| 42 | { |
| 43 | u32 reg; |
| 44 | |
| 45 | /* |
| 46 | * Set reload inhibit so configuration will persist across |
| 47 | * processor resets |
| 48 | */ |
| 49 | mfcpr(CPR0_ICFG, reg); |
| 50 | reg |= CPR0_ICFG_RLI_MASK; |
| 51 | mtcpr(CPR0_ICFG, reg); |
| 52 | |
| 53 | /* Reset processor if configuration changed */ |
| 54 | __asm__ __volatile__ ("sync; isync"); |
| 55 | mtspr(SPRN_DBCR0, 0x20000000); |
| 56 | } |
| 57 | #endif |
| 58 | |
Mike Nuss | f66e2c8 | 2008-02-20 11:54:20 -0500 | [diff] [blame] | 59 | void reconfigure_pll(u32 new_cpu_freq) |
| 60 | { |
| 61 | #if defined(CONFIG_440EPX) |
| 62 | int reset_needed = 0; |
| 63 | u32 reg, temp; |
| 64 | u32 prbdv0, target_prbdv0, /* CLK_PRIMBD */ |
| 65 | fwdva, target_fwdva, fwdvb, target_fwdvb, /* CLK_PLLD */ |
| 66 | fbdv, target_fbdv, lfbdv, target_lfbdv, |
| 67 | perdv0, target_perdv0, /* CLK_PERD */ |
| 68 | spcid0, target_spcid0; /* CLK_SPCID */ |
| 69 | |
| 70 | /* Reconfigure clocks if necessary. |
| 71 | * See PPC440EPx User's Manual, sections 8.2 and 14 */ |
| 72 | if (new_cpu_freq == 667) { |
| 73 | target_prbdv0 = 2; |
| 74 | target_fwdva = 2; |
| 75 | target_fwdvb = 4; |
| 76 | target_fbdv = 20; |
| 77 | target_lfbdv = 1; |
| 78 | target_perdv0 = 4; |
| 79 | target_spcid0 = 4; |
| 80 | |
Niklaus Giger | ddc922f | 2009-10-04 20:04:20 +0200 | [diff] [blame] | 81 | mfcpr(CPR0_PRIMBD0, reg); |
Mike Nuss | f66e2c8 | 2008-02-20 11:54:20 -0500 | [diff] [blame] | 82 | temp = (reg & PRBDV_MASK) >> 24; |
| 83 | prbdv0 = temp ? temp : 8; |
| 84 | if (prbdv0 != target_prbdv0) { |
| 85 | reg &= ~PRBDV_MASK; |
| 86 | reg |= ((target_prbdv0 == 8 ? 0 : target_prbdv0) << 24); |
Niklaus Giger | ddc922f | 2009-10-04 20:04:20 +0200 | [diff] [blame] | 87 | mtcpr(CPR0_PRIMBD0, reg); |
Mike Nuss | f66e2c8 | 2008-02-20 11:54:20 -0500 | [diff] [blame] | 88 | reset_needed = 1; |
| 89 | } |
| 90 | |
Stefan Roese | d1c3b27 | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 91 | mfcpr(CPR0_PLLD, reg); |
Mike Nuss | f66e2c8 | 2008-02-20 11:54:20 -0500 | [diff] [blame] | 92 | |
| 93 | temp = (reg & PLLD_FWDVA_MASK) >> 16; |
| 94 | fwdva = temp ? temp : 16; |
| 95 | |
| 96 | temp = (reg & PLLD_FWDVB_MASK) >> 8; |
| 97 | fwdvb = temp ? temp : 8; |
| 98 | |
| 99 | temp = (reg & PLLD_FBDV_MASK) >> 24; |
| 100 | fbdv = temp ? temp : 32; |
| 101 | |
| 102 | temp = (reg & PLLD_LFBDV_MASK); |
| 103 | lfbdv = temp ? temp : 64; |
| 104 | |
| 105 | if (fwdva != target_fwdva || fbdv != target_fbdv || lfbdv != target_lfbdv) { |
| 106 | reg &= ~(PLLD_FWDVA_MASK | PLLD_FWDVB_MASK | |
| 107 | PLLD_FBDV_MASK | PLLD_LFBDV_MASK); |
| 108 | reg |= ((target_fwdva == 16 ? 0 : target_fwdva) << 16) | |
| 109 | ((target_fwdvb == 8 ? 0 : target_fwdvb) << 8) | |
| 110 | ((target_fbdv == 32 ? 0 : target_fbdv) << 24) | |
| 111 | (target_lfbdv == 64 ? 0 : target_lfbdv); |
Stefan Roese | d1c3b27 | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 112 | mtcpr(CPR0_PLLD, reg); |
Mike Nuss | f66e2c8 | 2008-02-20 11:54:20 -0500 | [diff] [blame] | 113 | reset_needed = 1; |
| 114 | } |
| 115 | |
Stefan Roese | d1c3b27 | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 116 | mfcpr(CPR0_PERD, reg); |
Mike Nuss | f66e2c8 | 2008-02-20 11:54:20 -0500 | [diff] [blame] | 117 | perdv0 = (reg & CPR0_PERD_PERDV0_MASK) >> 24; |
| 118 | if (perdv0 != target_perdv0) { |
| 119 | reg &= ~CPR0_PERD_PERDV0_MASK; |
| 120 | reg |= (target_perdv0 << 24); |
Stefan Roese | d1c3b27 | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 121 | mtcpr(CPR0_PERD, reg); |
Mike Nuss | f66e2c8 | 2008-02-20 11:54:20 -0500 | [diff] [blame] | 122 | reset_needed = 1; |
| 123 | } |
| 124 | |
Stefan Roese | d1c3b27 | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 125 | mfcpr(CPR0_SPCID, reg); |
Mike Nuss | f66e2c8 | 2008-02-20 11:54:20 -0500 | [diff] [blame] | 126 | temp = (reg & CPR0_SPCID_SPCIDV0_MASK) >> 24; |
| 127 | spcid0 = temp ? temp : 4; |
| 128 | if (spcid0 != target_spcid0) { |
| 129 | reg &= ~CPR0_SPCID_SPCIDV0_MASK; |
| 130 | reg |= ((target_spcid0 == 4 ? 0 : target_spcid0) << 24); |
Stefan Roese | d1c3b27 | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 131 | mtcpr(CPR0_SPCID, reg); |
Mike Nuss | f66e2c8 | 2008-02-20 11:54:20 -0500 | [diff] [blame] | 132 | reset_needed = 1; |
| 133 | } |
Rupjyoti Sarmah | c550afa | 2010-03-24 16:52:02 +0530 | [diff] [blame] | 134 | } |
Mike Nuss | f66e2c8 | 2008-02-20 11:54:20 -0500 | [diff] [blame] | 135 | |
Rupjyoti Sarmah | c550afa | 2010-03-24 16:52:02 +0530 | [diff] [blame] | 136 | /* Get current value of FWDVA.*/ |
| 137 | mfcpr(CPR0_PLLD, reg); |
| 138 | temp = (reg & PLLD_FWDVA_MASK) >> 16; |
| 139 | |
| 140 | /* |
| 141 | * Check to see if FWDVA has been set to value of 1. if it has we must |
| 142 | * modify it. |
| 143 | */ |
| 144 | if (temp == 1) { |
Rupjyoti Sarmah | c550afa | 2010-03-24 16:52:02 +0530 | [diff] [blame] | 145 | /* |
| 146 | * Load register that contains current boot strapping option. |
| 147 | */ |
| 148 | mfcpr(CPR0_ICFG, reg); |
Stefan Roese | c1ab75c | 2010-08-26 17:14:51 +0200 | [diff] [blame] | 149 | /* |
| 150 | * Strapping option bits (ICS) are already in correct position, |
| 151 | * only masking needed. |
| 152 | */ |
| 153 | reg &= CPR0_ICFG_ICS_MASK; |
Rupjyoti Sarmah | c550afa | 2010-03-24 16:52:02 +0530 | [diff] [blame] | 154 | |
| 155 | if ((reg == BOOT_STRAP_OPTION_A) || (reg == BOOT_STRAP_OPTION_B) || |
| 156 | (reg == BOOT_STRAP_OPTION_D) || (reg == BOOT_STRAP_OPTION_E)) { |
Stefan Roese | c1ab75c | 2010-08-26 17:14:51 +0200 | [diff] [blame] | 157 | mfcpr(CPR0_PLLD, reg); |
| 158 | |
| 159 | /* Get current value of fbdv. */ |
| 160 | temp = (reg & PLLD_FBDV_MASK) >> 24; |
| 161 | fbdv = temp ? temp : 32; |
| 162 | |
| 163 | /* Get current value of lfbdv. */ |
| 164 | temp = (reg & PLLD_LFBDV_MASK); |
| 165 | lfbdv = temp ? temp : 64; |
| 166 | |
Rupjyoti Sarmah | c550afa | 2010-03-24 16:52:02 +0530 | [diff] [blame] | 167 | /* |
| 168 | * Get current value of FWDVA. Assign current FWDVA to |
| 169 | * new FWDVB. |
| 170 | */ |
| 171 | mfcpr(CPR0_PLLD, reg); |
| 172 | target_fwdvb = (reg & PLLD_FWDVA_MASK) >> 16; |
| 173 | fwdvb = target_fwdvb ? target_fwdvb : 8; |
Stefan Roese | c1ab75c | 2010-08-26 17:14:51 +0200 | [diff] [blame] | 174 | |
Rupjyoti Sarmah | c550afa | 2010-03-24 16:52:02 +0530 | [diff] [blame] | 175 | /* |
| 176 | * Get current value of FWDVB. Assign current FWDVB to |
| 177 | * new FWDVA. |
| 178 | */ |
| 179 | target_fwdva = (reg & PLLD_FWDVB_MASK) >> 8; |
| 180 | fwdva = target_fwdva ? target_fwdva : 16; |
Stefan Roese | c1ab75c | 2010-08-26 17:14:51 +0200 | [diff] [blame] | 181 | |
Rupjyoti Sarmah | c550afa | 2010-03-24 16:52:02 +0530 | [diff] [blame] | 182 | /* |
| 183 | * Update CPR0_PLLD with switched FWDVA and FWDVB. |
| 184 | */ |
| 185 | reg &= ~(PLLD_FWDVA_MASK | PLLD_FWDVB_MASK | |
| 186 | PLLD_FBDV_MASK | PLLD_LFBDV_MASK); |
| 187 | reg |= ((fwdva == 16 ? 0 : fwdva) << 16) | |
| 188 | ((fwdvb == 8 ? 0 : fwdvb) << 8) | |
| 189 | ((fbdv == 32 ? 0 : fbdv) << 24) | |
| 190 | (lfbdv == 64 ? 0 : lfbdv); |
| 191 | mtcpr(CPR0_PLLD, reg); |
Stefan Roese | c1ab75c | 2010-08-26 17:14:51 +0200 | [diff] [blame] | 192 | |
Rupjyoti Sarmah | c550afa | 2010-03-24 16:52:02 +0530 | [diff] [blame] | 193 | /* Acknowledge that a reset is required. */ |
| 194 | reset_needed = 1; |
| 195 | } |
| 196 | } |
| 197 | |
Stefan Roese | fe7cca7 | 2010-05-19 11:13:24 +0200 | [diff] [blame] | 198 | /* Now reset the CPU if needed */ |
| 199 | if (reset_needed) |
| 200 | reset_with_rli(); |
| 201 | #endif |
Mike Nuss | f66e2c8 | 2008-02-20 11:54:20 -0500 | [diff] [blame] | 202 | |
Stefan Roese | fe7cca7 | 2010-05-19 11:13:24 +0200 | [diff] [blame] | 203 | #if defined(CONFIG_460EX) || defined(CONFIG_460GT) |
| 204 | u32 reg; |
| 205 | |
| 206 | /* |
| 207 | * See "9.2.1.1 Booting with Option E" in the 460EX/GT |
| 208 | * users manual |
| 209 | */ |
| 210 | mfcpr(CPR0_PLLC, reg); |
| 211 | if ((reg & (CPR0_PLLC_RST | CPR0_PLLC_ENG)) == CPR0_PLLC_RST) { |
| 212 | /* |
| 213 | * Set engage bit |
| 214 | */ |
| 215 | reg = (reg & ~CPR0_PLLC_RST) | CPR0_PLLC_ENG; |
| 216 | mtcpr(CPR0_PLLC, reg); |
| 217 | |
| 218 | /* Now reset the CPU */ |
| 219 | reset_with_rli(); |
Mike Nuss | f66e2c8 | 2008-02-20 11:54:20 -0500 | [diff] [blame] | 220 | } |
| 221 | #endif |
| 222 | } |
| 223 | |
Steven A. Falco | 644362c | 2011-05-05 10:08:35 -0400 | [diff] [blame] | 224 | #ifdef CONFIG_SYS_4xx_CHIP_21_ERRATA |
| 225 | void |
| 226 | chip_21_errata(void) |
| 227 | { |
| 228 | /* |
| 229 | * See rev 1.09 of the 405EX/405EXr errata. CHIP_21 says that |
| 230 | * sometimes reading the PVR and/or SDR0_ECID results in incorrect |
| 231 | * values. Since the rev-D chip uses the SDR0_ECID bits to control |
| 232 | * internal features, that means the second PCIe or ethernet of an EX |
| 233 | * variant could fail to work. Also, security features of both EX and |
| 234 | * EXr might be incorrectly disabled. |
| 235 | * |
| 236 | * The suggested workaround is as follows (covering rev-C and rev-D): |
| 237 | * |
| 238 | * 1.Read the PVR and SDR0_ECID3. |
| 239 | * |
| 240 | * 2.If the PVR matches an expected Revision C PVR value AND if |
| 241 | * SDR0_ECID3[12:15] is different from PVR[28:31], then processor is |
| 242 | * Revision C: continue executing the initialization code (no reset |
| 243 | * required). else go to step 3. |
| 244 | * |
| 245 | * 3.If the PVR matches an expected Revision D PVR value AND if |
| 246 | * SDR0_ECID3[10:11] matches its expected value, then continue |
| 247 | * executing initialization code, no reset required. else write |
| 248 | * DBCR0[RST] = 0b11 to generate a SysReset. |
| 249 | */ |
| 250 | |
| 251 | u32 pvr; |
| 252 | u32 pvr_28_31; |
| 253 | u32 ecid3; |
| 254 | u32 ecid3_10_11; |
| 255 | u32 ecid3_12_15; |
| 256 | |
| 257 | /* Step 1: */ |
| 258 | pvr = get_pvr(); |
| 259 | mfsdr(SDR0_ECID3, ecid3); |
| 260 | |
| 261 | /* Step 2: */ |
| 262 | pvr_28_31 = pvr & 0xf; |
| 263 | ecid3_10_11 = (ecid3 >> 20) & 0x3; |
| 264 | ecid3_12_15 = (ecid3 >> 16) & 0xf; |
| 265 | if ((pvr == CONFIG_405EX_CHIP21_PVR_REV_C) && |
| 266 | (pvr_28_31 != ecid3_12_15)) { |
| 267 | /* No reset required. */ |
| 268 | return; |
| 269 | } |
| 270 | |
| 271 | /* Step 3: */ |
| 272 | if ((pvr == CONFIG_405EX_CHIP21_PVR_REV_D) && |
| 273 | (ecid3_10_11 == CONFIG_405EX_CHIP21_ECID3_REV_D)) { |
| 274 | /* No reset required. */ |
| 275 | return; |
| 276 | } |
| 277 | |
| 278 | /* Reset required. */ |
| 279 | __asm__ __volatile__ ("sync; isync"); |
| 280 | mtspr(SPRN_DBCR0, 0x30000000); |
| 281 | } |
| 282 | #endif |
| 283 | |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 284 | /* |
| 285 | * Breath some life into the CPU... |
| 286 | * |
Mike Nuss | f66e2c8 | 2008-02-20 11:54:20 -0500 | [diff] [blame] | 287 | * Reconfigure PLL if necessary, |
| 288 | * set up the memory map, |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 289 | * initialize a bunch of registers |
| 290 | */ |
| 291 | void |
| 292 | cpu_init_f (void) |
| 293 | { |
Stefan Roese | f556483 | 2008-08-21 11:05:03 +0200 | [diff] [blame] | 294 | #if defined(CONFIG_WATCHDOG) || defined(CONFIG_440GX) || defined(CONFIG_460EX) |
Stefan Roese | 745d8a0 | 2008-06-28 14:56:17 +0200 | [diff] [blame] | 295 | u32 val; |
Wolfgang Denk | f11033e | 2007-01-15 13:41:04 +0100 | [diff] [blame] | 296 | #endif |
Stefan Roese | 5de8514 | 2008-06-26 17:36:39 +0200 | [diff] [blame] | 297 | |
Steven A. Falco | 644362c | 2011-05-05 10:08:35 -0400 | [diff] [blame] | 298 | #ifdef CONFIG_SYS_4xx_CHIP_21_ERRATA |
| 299 | chip_21_errata(); |
| 300 | #endif |
| 301 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 302 | reconfigure_pll(CONFIG_SYS_PLL_RECONFIG); |
Wolfgang Denk | f11033e | 2007-01-15 13:41:04 +0100 | [diff] [blame] | 303 | |
Tirumala Marri | 1b8fec1 | 2010-09-28 14:15:14 -0700 | [diff] [blame] | 304 | #if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && \ |
| 305 | !defined(CONFIG_APM821XX) &&!defined(CONFIG_SYS_4xx_GPIO_TABLE) |
stroese | b867d70 | 2003-05-23 11:18:02 +0000 | [diff] [blame] | 306 | /* |
| 307 | * GPIO0 setup (select GPIO or alternate function) |
| 308 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 309 | #if defined(CONFIG_SYS_GPIO0_OR) |
| 310 | out32(GPIO0_OR, CONFIG_SYS_GPIO0_OR); /* set initial state of output pins */ |
Stefan Roese | e0a4655 | 2006-10-12 19:43:29 +0200 | [diff] [blame] | 311 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 312 | #if defined(CONFIG_SYS_GPIO0_ODR) |
| 313 | out32(GPIO0_ODR, CONFIG_SYS_GPIO0_ODR); /* open-drain select */ |
Stefan Roese | e0a4655 | 2006-10-12 19:43:29 +0200 | [diff] [blame] | 314 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 315 | out32(GPIO0_OSRH, CONFIG_SYS_GPIO0_OSRH); /* output select */ |
| 316 | out32(GPIO0_OSRL, CONFIG_SYS_GPIO0_OSRL); |
| 317 | out32(GPIO0_ISR1H, CONFIG_SYS_GPIO0_ISR1H); /* input select */ |
| 318 | out32(GPIO0_ISR1L, CONFIG_SYS_GPIO0_ISR1L); |
| 319 | out32(GPIO0_TSRH, CONFIG_SYS_GPIO0_TSRH); /* three-state select */ |
| 320 | out32(GPIO0_TSRL, CONFIG_SYS_GPIO0_TSRL); |
| 321 | #if defined(CONFIG_SYS_GPIO0_ISR2H) |
| 322 | out32(GPIO0_ISR2H, CONFIG_SYS_GPIO0_ISR2H); |
| 323 | out32(GPIO0_ISR2L, CONFIG_SYS_GPIO0_ISR2L); |
Stefan Roese | dbbd125 | 2007-10-05 17:10:59 +0200 | [diff] [blame] | 324 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 325 | #if defined (CONFIG_SYS_GPIO0_TCR) |
| 326 | out32(GPIO0_TCR, CONFIG_SYS_GPIO0_TCR); /* enable output driver for outputs */ |
Stefan Roese | dbbd125 | 2007-10-05 17:10:59 +0200 | [diff] [blame] | 327 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 328 | #endif /* CONFIG_405EP ... && !CONFIG_SYS_4xx_GPIO_TABLE */ |
stroese | b867d70 | 2003-05-23 11:18:02 +0000 | [diff] [blame] | 329 | |
Stefan Roese | bec9264 | 2007-12-28 15:53:46 +0100 | [diff] [blame] | 330 | #if defined (CONFIG_405EP) |
stroese | b867d70 | 2003-05-23 11:18:02 +0000 | [diff] [blame] | 331 | /* |
| 332 | * Set EMAC noise filter bits |
| 333 | */ |
Stefan Roese | afabb49 | 2010-09-12 06:21:37 +0200 | [diff] [blame] | 334 | mtdcr(CPC0_EPCTL, CPC0_EPCTL_E0NFE | CPC0_EPCTL_E1NFE); |
stroese | b867d70 | 2003-05-23 11:18:02 +0000 | [diff] [blame] | 335 | #endif /* CONFIG_405EP */ |
| 336 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 337 | #if defined(CONFIG_SYS_4xx_GPIO_TABLE) |
Stefan Roese | 0d974d5 | 2007-03-24 15:57:09 +0100 | [diff] [blame] | 338 | gpio_set_chip_configuration(); |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 339 | #endif /* CONFIG_SYS_4xx_GPIO_TABLE */ |
Stefan Roese | a4c8d13 | 2006-06-02 16:18:04 +0200 | [diff] [blame] | 340 | |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 341 | /* |
| 342 | * External Bus Controller (EBC) Setup |
| 343 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 344 | #if (defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR)) |
Stefan Roese | a4c8d13 | 2006-06-02 16:18:04 +0200 | [diff] [blame] | 345 | #if (defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ |
Stefan Roese | e01bd21 | 2007-03-21 13:38:59 +0100 | [diff] [blame] | 346 | defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \ |
Stefan Roese | dbbd125 | 2007-10-05 17:10:59 +0200 | [diff] [blame] | 347 | defined(CONFIG_405EX) || defined(CONFIG_405)) |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 348 | /* |
| 349 | * Move the next instructions into icache, since these modify the flash |
| 350 | * we are running from! |
| 351 | */ |
| 352 | asm volatile(" bl 0f" ::: "lr"); |
| 353 | asm volatile("0: mflr 3" ::: "r3"); |
Wolfgang Denk | 1636d1c | 2007-06-22 23:59:00 +0200 | [diff] [blame] | 354 | asm volatile(" addi 4, 0, 14" ::: "r4"); |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 355 | asm volatile(" mtctr 4" ::: "ctr"); |
| 356 | asm volatile("1: icbt 0, 3"); |
| 357 | asm volatile(" addi 3, 3, 32" ::: "r3"); |
| 358 | asm volatile(" bdnz 1b" ::: "ctr", "cr0"); |
| 359 | asm volatile(" addis 3, 0, 0x0" ::: "r3"); |
| 360 | asm volatile(" ori 3, 3, 0xA000" ::: "r3"); |
| 361 | asm volatile(" mtctr 3" ::: "ctr"); |
| 362 | asm volatile("2: bdnz 2b" ::: "ctr", "cr0"); |
Stefan Roese | a4c8d13 | 2006-06-02 16:18:04 +0200 | [diff] [blame] | 363 | #endif |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 364 | |
Stefan Roese | d1c3b27 | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 365 | mtebc(PB0AP, CONFIG_SYS_EBC_PB0AP); |
| 366 | mtebc(PB0CR, CONFIG_SYS_EBC_PB0CR); |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 367 | #endif |
| 368 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 369 | #if (defined(CONFIG_SYS_EBC_PB1AP) && defined(CONFIG_SYS_EBC_PB1CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 1)) |
Stefan Roese | d1c3b27 | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 370 | mtebc(PB1AP, CONFIG_SYS_EBC_PB1AP); |
| 371 | mtebc(PB1CR, CONFIG_SYS_EBC_PB1CR); |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 372 | #endif |
| 373 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 374 | #if (defined(CONFIG_SYS_EBC_PB2AP) && defined(CONFIG_SYS_EBC_PB2CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 2)) |
Stefan Roese | d1c3b27 | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 375 | mtebc(PB2AP, CONFIG_SYS_EBC_PB2AP); |
| 376 | mtebc(PB2CR, CONFIG_SYS_EBC_PB2CR); |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 377 | #endif |
| 378 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 379 | #if (defined(CONFIG_SYS_EBC_PB3AP) && defined(CONFIG_SYS_EBC_PB3CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 3)) |
Stefan Roese | d1c3b27 | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 380 | mtebc(PB3AP, CONFIG_SYS_EBC_PB3AP); |
| 381 | mtebc(PB3CR, CONFIG_SYS_EBC_PB3CR); |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 382 | #endif |
| 383 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 384 | #if (defined(CONFIG_SYS_EBC_PB4AP) && defined(CONFIG_SYS_EBC_PB4CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 4)) |
Stefan Roese | d1c3b27 | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 385 | mtebc(PB4AP, CONFIG_SYS_EBC_PB4AP); |
| 386 | mtebc(PB4CR, CONFIG_SYS_EBC_PB4CR); |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 387 | #endif |
| 388 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 389 | #if (defined(CONFIG_SYS_EBC_PB5AP) && defined(CONFIG_SYS_EBC_PB5CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 5)) |
Stefan Roese | d1c3b27 | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 390 | mtebc(PB5AP, CONFIG_SYS_EBC_PB5AP); |
| 391 | mtebc(PB5CR, CONFIG_SYS_EBC_PB5CR); |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 392 | #endif |
| 393 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 394 | #if (defined(CONFIG_SYS_EBC_PB6AP) && defined(CONFIG_SYS_EBC_PB6CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 6)) |
Stefan Roese | d1c3b27 | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 395 | mtebc(PB6AP, CONFIG_SYS_EBC_PB6AP); |
| 396 | mtebc(PB6CR, CONFIG_SYS_EBC_PB6CR); |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 397 | #endif |
| 398 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 399 | #if (defined(CONFIG_SYS_EBC_PB7AP) && defined(CONFIG_SYS_EBC_PB7CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 7)) |
Stefan Roese | d1c3b27 | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 400 | mtebc(PB7AP, CONFIG_SYS_EBC_PB7AP); |
| 401 | mtebc(PB7CR, CONFIG_SYS_EBC_PB7CR); |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 402 | #endif |
| 403 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 404 | #if defined (CONFIG_SYS_EBC_CFG) |
| 405 | mtebc(EBC0_CFG, CONFIG_SYS_EBC_CFG); |
Heiko Schocher | ca43ba1 | 2007-01-11 15:44:44 +0100 | [diff] [blame] | 406 | #endif |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 407 | |
Wolfgang Denk | f11033e | 2007-01-15 13:41:04 +0100 | [diff] [blame] | 408 | #if defined(CONFIG_WATCHDOG) |
Stefan Roese | f472069 | 2010-10-04 11:09:40 +0200 | [diff] [blame] | 409 | val = mfspr(SPRN_TCR); |
Stefan Roese | 846b0dd | 2005-08-08 12:42:22 +0200 | [diff] [blame] | 410 | #if defined(CONFIG_440EP) || defined(CONFIG_440GR) |
Stefan Roese | c157d8e | 2005-08-01 16:41:48 +0200 | [diff] [blame] | 411 | val |= 0xb8000000; /* generate system reset after 1.34 seconds */ |
Igor Lisitsin | a11e069 | 2007-03-28 19:06:19 +0400 | [diff] [blame] | 412 | #elif defined(CONFIG_440EPX) |
| 413 | val |= 0xb0000000; /* generate system reset after 1.34 seconds */ |
Stefan Roese | c157d8e | 2005-08-01 16:41:48 +0200 | [diff] [blame] | 414 | #else |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 415 | val |= 0xf0000000; /* generate system reset after 2.684 seconds */ |
Stefan Roese | c157d8e | 2005-08-01 16:41:48 +0200 | [diff] [blame] | 416 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 417 | #if defined(CONFIG_SYS_4xx_RESET_TYPE) |
Stefan Roese | 1c2ce22 | 2006-11-27 14:12:17 +0100 | [diff] [blame] | 418 | val &= ~0x30000000; /* clear WRC bits */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 419 | val |= CONFIG_SYS_4xx_RESET_TYPE << 28; /* set board specific WRC type */ |
Stefan Roese | 1c2ce22 | 2006-11-27 14:12:17 +0100 | [diff] [blame] | 420 | #endif |
Stefan Roese | f472069 | 2010-10-04 11:09:40 +0200 | [diff] [blame] | 421 | mtspr(SPRN_TCR, val); |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 422 | |
Stefan Roese | f472069 | 2010-10-04 11:09:40 +0200 | [diff] [blame] | 423 | val = mfspr(SPRN_TSR); |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 424 | val |= 0x80000000; /* enable watchdog timer */ |
Stefan Roese | f472069 | 2010-10-04 11:09:40 +0200 | [diff] [blame] | 425 | mtspr(SPRN_TSR, val); |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 426 | |
| 427 | reset_4xx_watchdog(); |
| 428 | #endif /* CONFIG_WATCHDOG */ |
Stefan Roese | 745d8a0 | 2008-06-28 14:56:17 +0200 | [diff] [blame] | 429 | |
Stefan Roese | 5de8514 | 2008-06-26 17:36:39 +0200 | [diff] [blame] | 430 | #if defined(CONFIG_440GX) |
| 431 | /* Take the GX out of compatibility mode |
| 432 | * Travis Sawyer, 9 Mar 2004 |
| 433 | * NOTE: 440gx user manual inconsistency here |
| 434 | * Compatibility mode and Ethernet Clock select are not |
| 435 | * correct in the manual |
| 436 | */ |
Stefan Roese | d1c3b27 | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 437 | mfsdr(SDR0_MFR, val); |
Stefan Roese | 5de8514 | 2008-06-26 17:36:39 +0200 | [diff] [blame] | 438 | val &= ~0x10000000; |
Stefan Roese | d1c3b27 | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 439 | mtsdr(SDR0_MFR,val); |
Stefan Roese | 5de8514 | 2008-06-26 17:36:39 +0200 | [diff] [blame] | 440 | #endif /* CONFIG_440GX */ |
| 441 | |
Stefan Roese | 745d8a0 | 2008-06-28 14:56:17 +0200 | [diff] [blame] | 442 | #if defined(CONFIG_460EX) |
| 443 | /* |
| 444 | * Set SDR0_AHB_CFG[A2P_INCR4] (bit 24) and |
| 445 | * clear SDR0_AHB_CFG[A2P_PROT2] (bit 25) for a new 460EX errata |
| 446 | * regarding concurrent use of AHB USB OTG, USB 2.0 host and SATA |
| 447 | */ |
| 448 | mfsdr(SDR0_AHB_CFG, val); |
| 449 | val |= 0x80; |
| 450 | val &= ~0x40; |
| 451 | mtsdr(SDR0_AHB_CFG, val); |
| 452 | mfsdr(SDR0_USB2HOST_CFG, val); |
| 453 | val &= ~0xf00; |
| 454 | val |= 0x400; |
| 455 | mtsdr(SDR0_USB2HOST_CFG, val); |
| 456 | #endif /* CONFIG_460EX */ |
Prodyut Hazarika | 079589b | 2008-08-20 09:38:51 -0700 | [diff] [blame] | 457 | |
Stefan Roese | f556483 | 2008-08-21 11:05:03 +0200 | [diff] [blame] | 458 | #if defined(CONFIG_405EX) || \ |
| 459 | defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ |
Prodyut Hazarika | 079589b | 2008-08-20 09:38:51 -0700 | [diff] [blame] | 460 | defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ |
Tirumala Marri | 1b8fec1 | 2010-09-28 14:15:14 -0700 | [diff] [blame] | 461 | defined(CONFIG_460SX) || defined(CONFIG_APM821XX) |
Prodyut Hazarika | 079589b | 2008-08-20 09:38:51 -0700 | [diff] [blame] | 462 | /* |
| 463 | * Set PLB4 arbiter (Segment 0 and 1) to 4 deep pipeline read |
| 464 | */ |
Stefan Roese | 5e7abce | 2010-09-11 09:31:43 +0200 | [diff] [blame] | 465 | mtdcr(PLB4A0_ACR, (mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_RDP_MASK) | |
| 466 | PLB4Ax_ACR_RDP_4DEEP); |
| 467 | mtdcr(PLB4A1_ACR, (mfdcr(PLB4A1_ACR) & ~PLB4Ax_ACR_RDP_MASK) | |
| 468 | PLB4Ax_ACR_RDP_4DEEP); |
Prodyut Hazarika | 079589b | 2008-08-20 09:38:51 -0700 | [diff] [blame] | 469 | #endif /* CONFIG_440SP/SPE || CONFIG_460EX/GT || CONFIG_405EX */ |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 470 | } |
| 471 | |
| 472 | /* |
| 473 | * initialize higher level parts of CPU like time base and timers |
| 474 | */ |
| 475 | int cpu_init_r (void) |
| 476 | { |
stroese | b867d70 | 2003-05-23 11:18:02 +0000 | [diff] [blame] | 477 | #if defined(CONFIG_405GP) |
stroese | 38daa27 | 2003-03-20 15:21:50 +0000 | [diff] [blame] | 478 | uint pvr = get_pvr(); |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 479 | |
| 480 | /* |
stroese | 38daa27 | 2003-03-20 15:21:50 +0000 | [diff] [blame] | 481 | * Set edge conditioning circuitry on PPC405GPr |
| 482 | * for compatibility to existing PPC405GP designs. |
| 483 | */ |
stroese | baa3d52 | 2003-04-04 16:00:33 +0000 | [diff] [blame] | 484 | if ((pvr & 0xfffffff0) == (PVR_405GPR_RB & 0xfffffff0)) { |
Stefan Roese | d1c3b27 | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 485 | mtdcr(CPC0_ECR, 0x60606000); |
stroese | 38daa27 | 2003-03-20 15:21:50 +0000 | [diff] [blame] | 486 | } |
stroese | b867d70 | 2003-05-23 11:18:02 +0000 | [diff] [blame] | 487 | #endif /* defined(CONFIG_405GP) */ |
Stefan Roese | 2801b2d | 2008-03-11 15:05:50 +0100 | [diff] [blame] | 488 | |
Stefan Roese | 9cd6901 | 2009-02-23 16:42:51 +0100 | [diff] [blame] | 489 | return 0; |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 490 | } |
Stefan Roese | 5e47f95 | 2009-10-19 14:06:23 +0200 | [diff] [blame] | 491 | |
| 492 | #if defined(CONFIG_PCI) && \ |
| 493 | (defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \ |
| 494 | defined(CONFIG_440GR) || defined(CONFIG_440GRX)) |
| 495 | /* |
| 496 | * 440EP(x)/GR(x) PCI async/sync clocking restriction: |
| 497 | * |
| 498 | * In asynchronous PCI mode, the synchronous PCI clock must meet |
| 499 | * certain requirements. The following equation describes the |
| 500 | * relationship that must be maintained between the asynchronous PCI |
| 501 | * clock and synchronous PCI clock. Select an appropriate PCI:PLB |
| 502 | * ratio to maintain the relationship: |
| 503 | * |
| 504 | * AsyncPCIClk - 1MHz <= SyncPCIclock <= (2 * AsyncPCIClk) - 1MHz |
| 505 | */ |
| 506 | static int ppc4xx_pci_sync_clock_ok(u32 sync, u32 async) |
| 507 | { |
| 508 | if (((async - 1000000) > sync) || (sync > ((2 * async) - 1000000))) |
| 509 | return 0; |
| 510 | else |
| 511 | return 1; |
| 512 | } |
| 513 | |
| 514 | int ppc4xx_pci_sync_clock_config(u32 async) |
| 515 | { |
| 516 | sys_info_t sys_info; |
| 517 | u32 sync; |
| 518 | int div; |
| 519 | u32 reg; |
| 520 | u32 spcid_val[] = { |
| 521 | CPR0_SPCID_SPCIDV0_DIV1, CPR0_SPCID_SPCIDV0_DIV2, |
| 522 | CPR0_SPCID_SPCIDV0_DIV3, CPR0_SPCID_SPCIDV0_DIV4 }; |
| 523 | |
| 524 | get_sys_info(&sys_info); |
| 525 | sync = sys_info.freqPCI; |
| 526 | |
| 527 | /* |
| 528 | * First check if the equation above is met |
| 529 | */ |
| 530 | if (!ppc4xx_pci_sync_clock_ok(sync, async)) { |
| 531 | /* |
| 532 | * Reconfigure PCI sync clock to meet the equation. |
| 533 | * Start with highest possible PCI sync frequency |
| 534 | * (divider 1). |
| 535 | */ |
| 536 | for (div = 1; div <= 4; div++) { |
| 537 | sync = sys_info.freqPLB / div; |
| 538 | if (ppc4xx_pci_sync_clock_ok(sync, async)) |
| 539 | break; |
| 540 | } |
| 541 | |
| 542 | if (div <= 4) { |
| 543 | mtcpr(CPR0_SPCID, spcid_val[div]); |
| 544 | |
| 545 | mfcpr(CPR0_ICFG, reg); |
| 546 | reg |= CPR0_ICFG_RLI_MASK; |
| 547 | mtcpr(CPR0_ICFG, reg); |
| 548 | |
| 549 | /* do chip reset */ |
| 550 | mtspr(SPRN_DBCR0, 0x20000000); |
| 551 | } else { |
| 552 | /* Impossible to configure the PCI sync clock */ |
| 553 | return -1; |
| 554 | } |
| 555 | } |
| 556 | |
| 557 | return 0; |
| 558 | } |
| 559 | #endif |