| John Rigby | be72e0c | 2011-04-19 10:42:40 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) ST-Ericsson SA 2009 |
| 3 | * |
| 4 | * See file CREDITS for list of people who contributed to this |
| 5 | * project. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; either version 2 of |
| 10 | * the License, or (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 20 | * MA 02111-1307 USA |
| 21 | */ |
| 22 | |
| 23 | #ifndef __U8500_H |
| 24 | #define __U8500_H |
| 25 | |
| 26 | /* |
| 27 | * base register values for U8500 |
| 28 | */ |
| 29 | #define CFG_PRCMU_BASE 0x80157000 /* Power, reset and clock |
| 30 | Management Unit */ |
| 31 | #define CFG_SDRAMC_BASE 0x903CF000 /* SDRAMC cnf registers */ |
| 32 | #define CFG_FSMC_BASE 0x80000000 /* FSMC Controller */ |
| 33 | |
| 34 | /* |
| 35 | * U8500 GPIO register base for 9 banks |
| 36 | */ |
| 37 | #define U8500_GPIO_0_BASE 0x8012E000 |
| 38 | #define U8500_GPIO_1_BASE 0x8012E080 |
| 39 | #define U8500_GPIO_2_BASE 0x8000E000 |
| 40 | #define U8500_GPIO_3_BASE 0x8000E080 |
| 41 | #define U8500_GPIO_4_BASE 0x8000E100 |
| 42 | #define U8500_GPIO_5_BASE 0x8000E180 |
| 43 | #define U8500_GPIO_6_BASE 0x8011E000 |
| 44 | #define U8500_GPIO_7_BASE 0x8011E080 |
| 45 | #define U8500_GPIO_8_BASE 0xA03FE000 |
| 46 | |
| 47 | #endif /* __U8500_H */ |