blob: 1ce2358afd2717706e87729231c7292cc82888c2 [file] [log] [blame]
Vladimir Zapolskiy52f69f82012-04-19 04:33:08 +00001/*
2 * Copyright (C) 2011 Vladimir Zapolskiy <vz@mleia.com>
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19
20#include <common.h>
21#include <asm/arch/cpu.h>
22#include <asm/arch/clk.h>
23#include <asm/arch/timer.h>
24#include <asm/io.h>
25
26static struct timer_regs *timer0 = (struct timer_regs *)TIMER0_BASE;
27static struct timer_regs *timer1 = (struct timer_regs *)TIMER1_BASE;
28static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
29
30static void lpc32xx_timer_clock(u32 bit, int enable)
31{
32 if (enable)
33 setbits_le32(&clk->timclk_ctrl1, bit);
34 else
35 clrbits_le32(&clk->timclk_ctrl1, bit);
36}
37
38static void lpc32xx_timer_reset(struct timer_regs *timer, u32 freq)
39{
40 writel(TIMER_TCR_COUNTER_RESET, &timer->tcr);
41 writel(TIMER_TCR_COUNTER_DISABLE, &timer->tcr);
42 writel(0, &timer->tc);
43 writel(0, &timer->pr);
44
45 /* Count mode is every rising PCLK edge */
46 writel(TIMER_CTCR_MODE_TIMER, &timer->ctcr);
47
48 /* Set prescale counter value */
49 writel((get_periph_clk_rate() / freq) - 1, &timer->pr);
50}
51
52static void lpc32xx_timer_count(struct timer_regs *timer, int enable)
53{
54 if (enable)
55 writel(TIMER_TCR_COUNTER_ENABLE, &timer->tcr);
56 else
57 writel(TIMER_TCR_COUNTER_DISABLE, &timer->tcr);
58}
59
60int timer_init(void)
61{
62 lpc32xx_timer_clock(CLK_TIMCLK_TIMER0, 1);
63 lpc32xx_timer_reset(timer0, CONFIG_SYS_HZ);
64 lpc32xx_timer_count(timer0, 1);
65
66 return 0;
67}
68
69ulong get_timer(ulong base)
70{
71 return readl(&timer0->tc) - base;
72}
73
74void __udelay(unsigned long usec)
75{
76 lpc32xx_timer_clock(CLK_TIMCLK_TIMER1, 1);
77 lpc32xx_timer_reset(timer1, CONFIG_SYS_HZ * 1000);
78 lpc32xx_timer_count(timer1, 1);
79
80 while (readl(&timer1->tc) < usec)
81 /* NOP */;
82
83 lpc32xx_timer_count(timer1, 0);
84 lpc32xx_timer_clock(CLK_TIMCLK_TIMER1, 0);
85}
86
87unsigned long long get_ticks(void)
88{
89 return get_timer(0);
90}
91
92ulong get_tbclk(void)
93{
94 return CONFIG_SYS_HZ;
95}