blob: 578325cd05ebf3a31e28893bf66a03d932aefdd1 [file] [log] [blame]
Ilya Yanok5fb17032010-07-07 20:16:13 +04001/*
2 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
3 * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
4 *
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Ilya Yanok5fb17032010-07-07 20:16:13 +04007 */
8
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
Kim Phillipsfdfaa292015-03-17 12:00:45 -050012#define CONFIG_DISPLAY_BOARDINFO
13
Ilya Yanok5fb17032010-07-07 20:16:13 +040014/*
15 * High Level Configuration Options
16 */
17#define CONFIG_E300 1 /* E300 family */
Gerlando Falauto8afad912012-10-10 22:13:07 +000018#define CONFIG_MPC830x 1 /* MPC830x family */
Ilya Yanok5fb17032010-07-07 20:16:13 +040019#define CONFIG_MPC8308 1 /* MPC8308 CPU specific */
20#define CONFIG_MPC8308RDB 1 /* MPC8308RDB board specific */
21
Wolfgang Denk2ae18242010-10-06 09:05:45 +020022#define CONFIG_SYS_TEXT_BASE 0xFE000000
23
Ilya Yanok5fb17032010-07-07 20:16:13 +040024#define CONFIG_MISC_INIT_R
25
Ira W. Snyderdb1fc7d2012-09-12 14:17:35 -070026#define CONFIG_MMC 1
27
28#ifdef CONFIG_MMC
29#define CONFIG_FSL_ESDHC
30#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
31#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
32#define CONFIG_SYS_FSL_ESDHC_USE_PIO
33
Ira W. Snyderdb1fc7d2012-09-12 14:17:35 -070034#define CONFIG_GENERIC_MMC
Ira W. Snyderdb1fc7d2012-09-12 14:17:35 -070035#define CONFIG_DOS_PARTITION
36#endif
37
Ilya Yanok5fb17032010-07-07 20:16:13 +040038/*
39 * On-board devices
40 *
41 * TSEC1 is SoC TSEC
42 * TSEC2 is VSC switch
43 */
44#define CONFIG_TSEC1
45#define CONFIG_VSC7385_ENET
46
47/*
48 * System Clock Setup
49 */
50#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
51#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
52
53/*
54 * Hardware Reset Configuration Word
55 * if CLKIN is 66.66MHz, then
56 * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
57 * We choose the A type silicon as default, so the core is 400Mhz.
58 */
59#define CONFIG_SYS_HRCW_LOW (\
60 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
61 HRCWL_DDR_TO_SCB_CLK_2X1 |\
62 HRCWL_SVCOD_DIV_2 |\
63 HRCWL_CSB_TO_CLKIN_4X1 |\
64 HRCWL_CORE_TO_CSB_3X1)
65/*
66 * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
67 * in 8308's HRCWH according to the manual, but original Freescale's
68 * code has them and I've expirienced some problems using the board
69 * with BDI3000 attached when I've tried to set these bits to zero
70 * (UART doesn't work after the 'reset run' command).
71 */
72#define CONFIG_SYS_HRCW_HIGH (\
73 HRCWH_PCI_HOST |\
74 HRCWH_PCI1_ARBITER_ENABLE |\
75 HRCWH_CORE_ENABLE |\
76 HRCWH_FROM_0X00000100 |\
77 HRCWH_BOOTSEQ_DISABLE |\
78 HRCWH_SW_WATCHDOG_DISABLE |\
79 HRCWH_ROM_LOC_LOCAL_16BIT |\
80 HRCWH_RL_EXT_LEGACY |\
81 HRCWH_TSEC1M_IN_RGMII |\
82 HRCWH_TSEC2M_IN_RGMII |\
83 HRCWH_BIG_ENDIAN)
84
85/*
86 * System IO Config
87 */
Ilya Yanok65ea7582010-09-17 23:41:49 +020088#define CONFIG_SYS_SICRH (\
89 SICRH_ESDHC_A_SD |\
90 SICRH_ESDHC_B_SD |\
91 SICRH_ESDHC_C_SD |\
92 SICRH_GPIO_A_TSEC2 |\
93 SICRH_GPIO_B_TSEC2_GTX_CLK125 |\
94 SICRH_IEEE1588_A_GPIO |\
95 SICRH_USB |\
96 SICRH_GTM_GPIO |\
97 SICRH_IEEE1588_B_GPIO |\
98 SICRH_ETSEC2_CRS |\
99 SICRH_GPIOSEL_1 |\
100 SICRH_TMROBI_V3P3 |\
101 SICRH_TSOBI1_V2P5 |\
102 SICRH_TSOBI2_V2P5) /* 0x01b7d103 */
103#define CONFIG_SYS_SICRL (\
104 SICRL_SPI_PF0 |\
105 SICRL_UART_PF0 |\
106 SICRL_IRQ_PF0 |\
107 SICRL_I2C2_PF0 |\
108 SICRL_ETSEC1_GTX_CLK125) /* 0x00000040 */
Ilya Yanok5fb17032010-07-07 20:16:13 +0400109
110/*
111 * IMMR new address
112 */
113#define CONFIG_SYS_IMMR 0xE0000000
114
115/*
116 * SERDES
117 */
118#define CONFIG_FSL_SERDES
119#define CONFIG_FSL_SERDES1 0xe3000
120
121/*
122 * Arbiter Setup
123 */
124#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
125#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
126#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
127
128/*
129 * DDR Setup
130 */
131#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
132#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
133#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
134#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
135#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
136 | DDRCDR_PZ_LOZ \
137 | DDRCDR_NZ_LOZ \
138 | DDRCDR_ODT \
139 | DDRCDR_Q_DRN)
140 /* 0x7b880001 */
141/*
142 * Manually set up DDR parameters
143 * consist of two chips HY5PS12621BFP-C4 from HYNIX
144 */
145
146#define CONFIG_SYS_DDR_SIZE 128 /* MB */
147
148#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
149#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
Joe Hershberger2fef4022011-10-11 23:57:29 -0500150 | CSCONFIG_ODT_RD_NEVER \
151 | CSCONFIG_ODT_WR_ONLY_CURRENT \
Ilya Yanok5fb17032010-07-07 20:16:13 +0400152 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
153 /* 0x80010102 */
154#define CONFIG_SYS_DDR_TIMING_3 0x00000000
155#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
156 | (0 << TIMING_CFG0_WRT_SHIFT) \
157 | (0 << TIMING_CFG0_RRT_SHIFT) \
158 | (0 << TIMING_CFG0_WWT_SHIFT) \
159 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
160 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
161 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
162 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
163 /* 0x00220802 */
164#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
165 | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
166 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
167 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
168 | (6 << TIMING_CFG1_REFREC_SHIFT) \
169 | (2 << TIMING_CFG1_WRREC_SHIFT) \
170 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
171 | (2 << TIMING_CFG1_WRTORD_SHIFT))
172 /* 0x27256222 */
173#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
174 | (4 << TIMING_CFG2_CPO_SHIFT) \
175 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
176 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
177 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
178 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
179 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
180 /* 0x121048c5 */
181#define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
182 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
183 /* 0x03600100 */
184#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
185 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
Joe Hershberger2fef4022011-10-11 23:57:29 -0500186 | SDRAM_CFG_DBW_32)
Ilya Yanok5fb17032010-07-07 20:16:13 +0400187 /* 0x43080000 */
188
189#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
190#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
191 | (0x0232 << SDRAM_MODE_SD_SHIFT))
192 /* ODT 150ohm CL=3, AL=1 on SDRAM */
193#define CONFIG_SYS_DDR_MODE2 0x00000000
194
195/*
196 * Memory test
197 */
198#define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */
199#define CONFIG_SYS_MEMTEST_END 0x07f00000
200
201/*
202 * The reserved memory
203 */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200204#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Ilya Yanok5fb17032010-07-07 20:16:13 +0400205
206#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
207#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
208
209/*
210 * Initial RAM Base Address Setup
211 */
212#define CONFIG_SYS_INIT_RAM_LOCK 1
213#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
Joe Hershberger34f81962011-10-11 23:57:09 -0500214#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
Ilya Yanok5fb17032010-07-07 20:16:13 +0400215#define CONFIG_SYS_GBL_DATA_OFFSET \
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200216 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Ilya Yanok5fb17032010-07-07 20:16:13 +0400217
218/*
219 * Local Bus Configuration & Clock Setup
220 */
221#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
222#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
223#define CONFIG_SYS_LBC_LBCR 0x00040000
224
225/*
226 * FLASH on the Local Bus
227 */
228#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
229#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
230#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
231
232#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
233#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */
234#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
235
236/* Window base at flash base */
237#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
Ilya Yanok65ea7582010-09-17 23:41:49 +0200238#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB)
Ilya Yanok5fb17032010-07-07 20:16:13 +0400239
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500240#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
241 | BR_PS_16 /* 16 bit port */ \
242 | BR_MS_GPCM /* MSEL = GPCM */ \
243 | BR_V) /* valid */
244#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
Ilya Yanok5fb17032010-07-07 20:16:13 +0400245 | OR_UPM_XAM \
246 | OR_GPCM_CSNT \
247 | OR_GPCM_ACS_DIV2 \
248 | OR_GPCM_XACS \
249 | OR_GPCM_SCY_15 \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500250 | OR_GPCM_TRLX_SET \
251 | OR_GPCM_EHTR_SET)
Ilya Yanok5fb17032010-07-07 20:16:13 +0400252
253#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
254/* 127 64KB sectors and 8 8KB top sectors per device */
255#define CONFIG_SYS_MAX_FLASH_SECT 135
256
257#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
258#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
259
260/*
261 * NAND Flash on the Local Bus
262 */
Joe Hershberger34f81962011-10-11 23:57:09 -0500263#define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500264#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) /* 0x00008000 */
Joe Hershberger34f81962011-10-11 23:57:09 -0500265#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500266 | BR_DECC_CHK_GEN /* Use HW ECC */ \
267 | BR_PS_8 /* 8 bit Port */ \
Ilya Yanok5fb17032010-07-07 20:16:13 +0400268 | BR_MS_FCM /* MSEL = FCM */ \
Joe Hershberger34f81962011-10-11 23:57:09 -0500269 | BR_V) /* valid */
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500270#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
Ilya Yanok5fb17032010-07-07 20:16:13 +0400271 | OR_FCM_CSCT \
272 | OR_FCM_CST \
273 | OR_FCM_CHT \
274 | OR_FCM_SCY_1 \
275 | OR_FCM_TRLX \
Joe Hershberger34f81962011-10-11 23:57:09 -0500276 | OR_FCM_EHTR)
Ilya Yanok5fb17032010-07-07 20:16:13 +0400277 /* 0xFFFF8396 */
278
279#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
Ilya Yanok65ea7582010-09-17 23:41:49 +0200280#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
Ilya Yanok5fb17032010-07-07 20:16:13 +0400281
282#ifdef CONFIG_VSC7385_ENET
283#define CONFIG_TSEC2
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500284 /* VSC7385 Base address on CS2 */
Ilya Yanok5fb17032010-07-07 20:16:13 +0400285#define CONFIG_SYS_VSC7385_BASE 0xF0000000
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500286#define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */
287#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \
288 | BR_PS_8 /* 8-bit port */ \
289 | BR_MS_GPCM /* MSEL = GPCM */ \
290 | BR_V) /* valid */
291 /* 0xF0000801 */
292#define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \
293 | OR_GPCM_CSNT \
294 | OR_GPCM_XACS \
295 | OR_GPCM_SCY_15 \
296 | OR_GPCM_SETA \
297 | OR_GPCM_TRLX_SET \
298 | OR_GPCM_EHTR_SET)
299 /* 0xFFFE09FF */
Ilya Yanok5fb17032010-07-07 20:16:13 +0400300/* Access window base at VSC7385 base */
301#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE
302/* Access window size 128K */
Ilya Yanok65ea7582010-09-17 23:41:49 +0200303#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB)
Ilya Yanok5fb17032010-07-07 20:16:13 +0400304/* The flash address and size of the VSC7385 firmware image */
305#define CONFIG_VSC7385_IMAGE 0xFE7FE000
306#define CONFIG_VSC7385_IMAGE_SIZE 8192
307#endif
308/*
309 * Serial Port
310 */
311#define CONFIG_CONS_INDEX 1
Ilya Yanok5fb17032010-07-07 20:16:13 +0400312#define CONFIG_SYS_NS16550_SERIAL
313#define CONFIG_SYS_NS16550_REG_SIZE 1
314#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
315
316#define CONFIG_SYS_BAUDRATE_TABLE \
317 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
318
319#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
320#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
321
Ilya Yanok5fb17032010-07-07 20:16:13 +0400322/* I2C */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200323#define CONFIG_SYS_I2C
324#define CONFIG_SYS_I2C_FSL
325#define CONFIG_SYS_FSL_I2C_SPEED 400000
326#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
327#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
328#define CONFIG_SYS_FSL_I2C2_SPEED 400000
329#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
330#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
331#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
Ilya Yanok5fb17032010-07-07 20:16:13 +0400332
Ira W. Snyderea1ea542012-09-12 14:17:32 -0700333/*
334 * SPI on header J8
335 *
336 * WARNING: enabling this will break TSEC2 (connected to the Vitesse switch)
337 * due to a pinmux conflict between GPIO9 (SPI chip select )and the TSEC2 pins.
338 */
339#ifdef CONFIG_MPC8XXX_SPI
Ira W. Snyderea1ea542012-09-12 14:17:32 -0700340#define CONFIG_USE_SPIFLASH
Ira W. Snyderea1ea542012-09-12 14:17:32 -0700341#endif
Ilya Yanok5fb17032010-07-07 20:16:13 +0400342
343/*
344 * Board info - revision and where boot from
345 */
346#define CONFIG_SYS_I2C_PCF8574A_ADDR 0x39
347
348/*
349 * Config on-board RTC
350 */
351#define CONFIG_RTC_DS1337 /* ds1339 on board, use ds1337 rtc via i2c */
352#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
353
354/*
355 * General PCI
356 * Addresses are mapped 1-1.
357 */
358#define CONFIG_SYS_PCIE1_BASE 0xA0000000
359#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
360#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
361#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
362#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
363#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
364#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
365#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
366#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
367
Ilya Yanok65ea7582010-09-17 23:41:49 +0200368/* enable PCIE clock */
369#define CONFIG_SYS_SCCR_PCIEXP1CM 1
Ilya Yanok5fb17032010-07-07 20:16:13 +0400370
371#define CONFIG_PCI
Gabor Juhos842033e2013-05-30 07:06:12 +0000372#define CONFIG_PCI_INDIRECT_BRIDGE
Ilya Yanok5fb17032010-07-07 20:16:13 +0400373#define CONFIG_PCIE
374
375#define CONFIG_PCI_PNP /* do pci plug-and-play */
376
377#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
378#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
379
380/*
381 * TSEC
382 */
Ilya Yanok5fb17032010-07-07 20:16:13 +0400383#define CONFIG_TSEC_ENET /* TSEC ethernet support */
384#define CONFIG_SYS_TSEC1_OFFSET 0x24000
385#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
386#define CONFIG_SYS_TSEC2_OFFSET 0x25000
387#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
388
389/*
390 * TSEC ethernet configuration
391 */
392#define CONFIG_MII 1 /* MII PHY management */
393#define CONFIG_TSEC1_NAME "eTSEC0"
394#define CONFIG_TSEC2_NAME "eTSEC1"
395#define TSEC1_PHY_ADDR 2
396#define TSEC2_PHY_ADDR 1
397#define TSEC1_PHYIDX 0
398#define TSEC2_PHYIDX 0
399#define TSEC1_FLAGS TSEC_GIGABIT
400#define TSEC2_FLAGS TSEC_GIGABIT
401
402/* Options are: eTSEC[0-1] */
403#define CONFIG_ETHPRIME "eTSEC0"
404
405/*
406 * Environment
407 */
408#define CONFIG_ENV_IS_IN_FLASH 1
409#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
410 CONFIG_SYS_MONITOR_LEN)
411#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
412#define CONFIG_ENV_SIZE 0x2000
413#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
414#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
415
416#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
417#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
418
419/*
420 * BOOTP options
421 */
422#define CONFIG_BOOTP_BOOTFILESIZE
423#define CONFIG_BOOTP_BOOTPATH
424#define CONFIG_BOOTP_GATEWAY
425#define CONFIG_BOOTP_HOSTNAME
426
427/*
428 * Command line configuration.
429 */
Ilya Yanok5fb17032010-07-07 20:16:13 +0400430#define CONFIG_CMD_DATE
Ilya Yanok5fb17032010-07-07 20:16:13 +0400431#define CONFIG_CMD_PCI
Ilya Yanok5fb17032010-07-07 20:16:13 +0400432
433#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
434
435/*
436 * Miscellaneous configurable options
437 */
438#define CONFIG_SYS_LONGHELP /* undef to save memory */
439#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Ilya Yanok5fb17032010-07-07 20:16:13 +0400440
441#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
442
443/* Print Buffer Size */
444#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
445#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
446/* Boot Argument Buffer Size */
447#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
Ilya Yanok5fb17032010-07-07 20:16:13 +0400448
449/*
450 * For booting Linux, the board info and command line data
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700451 * have to be in the first 256 MB of memory, since this is
Ilya Yanok5fb17032010-07-07 20:16:13 +0400452 * the maximum mapped by the Linux kernel during initialization.
453 */
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700454#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
Ilya Yanok5fb17032010-07-07 20:16:13 +0400455
456/*
457 * Core HID Setup
458 */
459#define CONFIG_SYS_HID0_INIT 0x000000000
460#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
461 HID0_ENABLE_INSTRUCTION_CACHE | \
462 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
463#define CONFIG_SYS_HID2 HID2_HBE
464
465/*
466 * MMU Setup
467 */
468
469/* DDR: cache cacheable */
Joe Hershberger72cd4082011-10-11 23:57:28 -0500470#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
Ilya Yanok5fb17032010-07-07 20:16:13 +0400471 BATL_MEMCOHERENCE)
472#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
473 BATU_VS | BATU_VP)
474#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
475#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
476
477/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
Joe Hershberger72cd4082011-10-11 23:57:28 -0500478#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \
Ilya Yanok5fb17032010-07-07 20:16:13 +0400479 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
480#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
481 BATU_VP)
482#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
483#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
484
485/* FLASH: icache cacheable, but dcache-inhibit and guarded */
Joe Hershberger72cd4082011-10-11 23:57:28 -0500486#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
Ilya Yanok5fb17032010-07-07 20:16:13 +0400487 BATL_MEMCOHERENCE)
488#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
489 BATU_VS | BATU_VP)
Joe Hershberger72cd4082011-10-11 23:57:28 -0500490#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
Ilya Yanok5fb17032010-07-07 20:16:13 +0400491 BATL_CACHEINHIBIT | \
492 BATL_GUARDEDSTORAGE)
493#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
494
495/* Stack in dcache: cacheable, no memory coherence */
Joe Hershberger72cd4082011-10-11 23:57:28 -0500496#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
Ilya Yanok5fb17032010-07-07 20:16:13 +0400497#define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
498 BATU_VS | BATU_VP)
499#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
500#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
501
502/*
Ilya Yanok5fb17032010-07-07 20:16:13 +0400503 * Environment Configuration
504 */
505
506#define CONFIG_ENV_OVERWRITE
507
508#if defined(CONFIG_TSEC_ENET)
509#define CONFIG_HAS_ETH0
510#define CONFIG_HAS_ETH1
511#endif
512
513#define CONFIG_BAUDRATE 115200
514
515#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
516
Ilya Yanok5fb17032010-07-07 20:16:13 +0400517
Ilya Yanok5fb17032010-07-07 20:16:13 +0400518#define CONFIG_EXTRA_ENV_SETTINGS \
519 "netdev=eth0\0" \
520 "consoledev=ttyS0\0" \
521 "nfsargs=setenv bootargs root=/dev/nfs rw " \
522 "nfsroot=${serverip}:${rootpath}\0" \
523 "ramargs=setenv bootargs root=/dev/ram rw\0" \
524 "addip=setenv bootargs ${bootargs} " \
525 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
526 ":${hostname}:${netdev}:off panic=1\0" \
527 "addtty=setenv bootargs ${bootargs}" \
528 " console=${consoledev},${baudrate}\0" \
529 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
530 "addmisc=setenv bootargs ${bootargs}\0" \
531 "kernel_addr=FE080000\0" \
532 "fdt_addr=FE280000\0" \
533 "ramdisk_addr=FE290000\0" \
534 "u-boot=mpc8308rdb/u-boot.bin\0" \
535 "kernel_addr_r=1000000\0" \
536 "fdt_addr_r=C00000\0" \
537 "hostname=mpc8308rdb\0" \
538 "bootfile=mpc8308rdb/uImage\0" \
539 "fdtfile=mpc8308rdb/mpc8308rdb.dtb\0" \
540 "rootpath=/opt/eldk-4.2/ppc_6xx\0" \
541 "flash_self=run ramargs addip addtty addmtd addmisc;" \
542 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
543 "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
544 "bootm ${kernel_addr} - ${fdt_addr}\0" \
545 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
546 "tftp ${fdt_addr_r} ${fdtfile};" \
547 "run nfsargs addip addtty addmtd addmisc;" \
548 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
549 "bootcmd=run flash_self\0" \
550 "load=tftp ${loadaddr} ${u-boot}\0" \
Marek Vasut93ea89f2012-09-23 17:41:23 +0200551 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
552 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
Ilya Yanok5fb17032010-07-07 20:16:13 +0400553 " +${filesize};cp.b ${fileaddr} " \
Marek Vasut93ea89f2012-09-23 17:41:23 +0200554 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
Ilya Yanok5fb17032010-07-07 20:16:13 +0400555 "upd=run load update\0" \
556
557#endif /* __CONFIG_H */