arch/arm/dts/sama7g5.dtsi

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * sama7g5.dtsi - Device Tree Include file for SAMA7G5 SoC.
 *
 * Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries
 *
 * Author: Eugen Hristev <eugen.hristev@microchip.com>
 * Author: Claudiu Beznea <claudiu.beznea@microchip.com>
 *
 */

#include "skeleton.dtsi"
#include <dt-bindings/clk/at91.h>

/ {
	model = "Microchip SAMA7G5 family SoC";
	compatible = "microchip,sama7g5";

	clocks {
		slow_rc_osc: slow_rc_osc {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <32000>;
		};

		main_rc: main_rc {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <12000000>;
		};

		slow_xtal: slow_xtal {
			compatible = "fixed-clock";
			#clock-cells = <0>;
		};

		main_xtal: main_xtal {
			compatible = "fixed-clock";
			#clock-cells = <0>;
		};
	};

	ahb {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;

		apb {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;

			pmc: pmc@e0018000 {
				compatible = "microchip,sama7g5-pmc";
				reg = <0xe0018000 0x200>;
				#clock-cells = <2>;
				clocks = <&clk32 1>, <&clk32 0>, <&main_xtal>, <&main_rc>;
				clock-names = "td_slck", "md_slck", "main_xtal", "main_rc";
				status = "okay";
			};

			clk32: sckc@e001d050 {
				compatible = "microchip,sam9x60-sckc";
				reg = <0xe001d050 0x4>;
				clocks = <&slow_rc_osc>, <&slow_xtal>;
				#clock-cells = <1>;
			};

			sdmmc1: sdio-host@e1208000 {
				compatible = "microchip,sama7g5-sdhci";
				reg = <0xe1208000 0x300>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 81>, <&pmc PMC_TYPE_GCK 81>;
				clock-names = "hclock", "multclk";
				status = "disabled";
			};

			uart0: serial@e1824200 {
				compatible = "atmel,at91sam9260-usart";
				reg = <0xe1824200 0x200>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
				clock-names = "usart";
				status = "disabled";
			};
		};
	};
};