Bin Meng | 9c7dea6 | 2015-05-25 22:35:04 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> |
| 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0+ |
| 5 | */ |
| 6 | |
| 7 | #include <common.h> |
Simon Glass | e76187a | 2016-01-19 21:32:25 -0700 | [diff] [blame] | 8 | #include <dm.h> |
Bin Meng | 9c7dea6 | 2015-05-25 22:35:04 +0800 | [diff] [blame] | 9 | #include <errno.h> |
| 10 | #include <fdtdec.h> |
| 11 | #include <malloc.h> |
| 12 | #include <asm/io.h> |
| 13 | #include <asm/irq.h> |
| 14 | #include <asm/pci.h> |
| 15 | #include <asm/pirq_routing.h> |
| 16 | |
| 17 | DECLARE_GLOBAL_DATA_PTR; |
| 18 | |
Bin Meng | 9c7dea6 | 2015-05-25 22:35:04 +0800 | [diff] [blame] | 19 | static struct irq_routing_table *pirq_routing_table; |
| 20 | |
Bin Meng | b46c208 | 2016-02-01 01:40:51 -0800 | [diff] [blame] | 21 | bool pirq_check_irq_routed(struct udevice *dev, int link, u8 irq) |
Bin Meng | 9c7dea6 | 2015-05-25 22:35:04 +0800 | [diff] [blame] | 22 | { |
Bin Meng | b46c208 | 2016-02-01 01:40:51 -0800 | [diff] [blame] | 23 | struct irq_router *priv = dev_get_priv(dev); |
Bin Meng | 9c7dea6 | 2015-05-25 22:35:04 +0800 | [diff] [blame] | 24 | u8 pirq; |
Bin Meng | b46c208 | 2016-02-01 01:40:51 -0800 | [diff] [blame] | 25 | int base = priv->link_base; |
Bin Meng | 9c7dea6 | 2015-05-25 22:35:04 +0800 | [diff] [blame] | 26 | |
Bin Meng | b46c208 | 2016-02-01 01:40:51 -0800 | [diff] [blame] | 27 | if (priv->config == PIRQ_VIA_PCI) |
Bin Meng | 248c4fa | 2016-02-01 01:40:52 -0800 | [diff] [blame] | 28 | dm_pci_read_config8(dev->parent, LINK_N2V(link, base), &pirq); |
Bin Meng | 9c7dea6 | 2015-05-25 22:35:04 +0800 | [diff] [blame] | 29 | else |
Bin Meng | b46c208 | 2016-02-01 01:40:51 -0800 | [diff] [blame] | 30 | pirq = readb(priv->ibase + LINK_N2V(link, base)); |
Bin Meng | 9c7dea6 | 2015-05-25 22:35:04 +0800 | [diff] [blame] | 31 | |
| 32 | pirq &= 0xf; |
| 33 | |
| 34 | /* IRQ# 0/1/2/8/13 are reserved */ |
| 35 | if (pirq < 3 || pirq == 8 || pirq == 13) |
| 36 | return false; |
| 37 | |
| 38 | return pirq == irq ? true : false; |
| 39 | } |
| 40 | |
Bin Meng | b46c208 | 2016-02-01 01:40:51 -0800 | [diff] [blame] | 41 | int pirq_translate_link(struct udevice *dev, int link) |
Bin Meng | 9c7dea6 | 2015-05-25 22:35:04 +0800 | [diff] [blame] | 42 | { |
Bin Meng | b46c208 | 2016-02-01 01:40:51 -0800 | [diff] [blame] | 43 | struct irq_router *priv = dev_get_priv(dev); |
| 44 | |
| 45 | return LINK_V2N(link, priv->link_base); |
Bin Meng | 9c7dea6 | 2015-05-25 22:35:04 +0800 | [diff] [blame] | 46 | } |
| 47 | |
Bin Meng | b46c208 | 2016-02-01 01:40:51 -0800 | [diff] [blame] | 48 | void pirq_assign_irq(struct udevice *dev, int link, u8 irq) |
Bin Meng | 9c7dea6 | 2015-05-25 22:35:04 +0800 | [diff] [blame] | 49 | { |
Bin Meng | b46c208 | 2016-02-01 01:40:51 -0800 | [diff] [blame] | 50 | struct irq_router *priv = dev_get_priv(dev); |
| 51 | int base = priv->link_base; |
Bin Meng | 9c7dea6 | 2015-05-25 22:35:04 +0800 | [diff] [blame] | 52 | |
| 53 | /* IRQ# 0/1/2/8/13 are reserved */ |
| 54 | if (irq < 3 || irq == 8 || irq == 13) |
| 55 | return; |
| 56 | |
Bin Meng | b46c208 | 2016-02-01 01:40:51 -0800 | [diff] [blame] | 57 | if (priv->config == PIRQ_VIA_PCI) |
Bin Meng | 248c4fa | 2016-02-01 01:40:52 -0800 | [diff] [blame] | 58 | dm_pci_write_config8(dev->parent, LINK_N2V(link, base), irq); |
Bin Meng | 9c7dea6 | 2015-05-25 22:35:04 +0800 | [diff] [blame] | 59 | else |
Bin Meng | b46c208 | 2016-02-01 01:40:51 -0800 | [diff] [blame] | 60 | writeb(irq, priv->ibase + LINK_N2V(link, base)); |
Bin Meng | 9c7dea6 | 2015-05-25 22:35:04 +0800 | [diff] [blame] | 61 | } |
| 62 | |
Bin Meng | df81749 | 2015-06-23 12:18:47 +0800 | [diff] [blame] | 63 | static struct irq_info *check_dup_entry(struct irq_info *slot_base, |
| 64 | int entry_num, int bus, int device) |
Bin Meng | 9c7dea6 | 2015-05-25 22:35:04 +0800 | [diff] [blame] | 65 | { |
Bin Meng | df81749 | 2015-06-23 12:18:47 +0800 | [diff] [blame] | 66 | struct irq_info *slot = slot_base; |
| 67 | int i; |
Bin Meng | 9c7dea6 | 2015-05-25 22:35:04 +0800 | [diff] [blame] | 68 | |
Bin Meng | df81749 | 2015-06-23 12:18:47 +0800 | [diff] [blame] | 69 | for (i = 0; i < entry_num; i++) { |
| 70 | if (slot->bus == bus && slot->devfn == (device << 3)) |
| 71 | break; |
| 72 | slot++; |
| 73 | } |
| 74 | |
| 75 | return (i == entry_num) ? NULL : slot; |
| 76 | } |
| 77 | |
Bin Meng | b46c208 | 2016-02-01 01:40:51 -0800 | [diff] [blame] | 78 | static inline void fill_irq_info(struct irq_router *priv, struct irq_info *slot, |
| 79 | int bus, int device, int pin, int pirq) |
Bin Meng | df81749 | 2015-06-23 12:18:47 +0800 | [diff] [blame] | 80 | { |
Bin Meng | 9c7dea6 | 2015-05-25 22:35:04 +0800 | [diff] [blame] | 81 | slot->bus = bus; |
Bin Meng | 8c38e4d | 2015-06-23 12:18:46 +0800 | [diff] [blame] | 82 | slot->devfn = (device << 3) | 0; |
Bin Meng | b46c208 | 2016-02-01 01:40:51 -0800 | [diff] [blame] | 83 | slot->irq[pin - 1].link = LINK_N2V(pirq, priv->link_base); |
| 84 | slot->irq[pin - 1].bitmap = priv->irq_mask; |
Bin Meng | 9c7dea6 | 2015-05-25 22:35:04 +0800 | [diff] [blame] | 85 | } |
| 86 | |
Simon Glass | b565d66 | 2016-01-19 21:32:28 -0700 | [diff] [blame] | 87 | static int create_pirq_routing_table(struct udevice *dev) |
Bin Meng | 9c7dea6 | 2015-05-25 22:35:04 +0800 | [diff] [blame] | 88 | { |
Bin Meng | b46c208 | 2016-02-01 01:40:51 -0800 | [diff] [blame] | 89 | struct irq_router *priv = dev_get_priv(dev); |
Bin Meng | 9c7dea6 | 2015-05-25 22:35:04 +0800 | [diff] [blame] | 90 | const void *blob = gd->fdt_blob; |
Bin Meng | 9c7dea6 | 2015-05-25 22:35:04 +0800 | [diff] [blame] | 91 | int node; |
| 92 | int len, count; |
| 93 | const u32 *cell; |
| 94 | struct irq_routing_table *rt; |
Bin Meng | df81749 | 2015-06-23 12:18:47 +0800 | [diff] [blame] | 95 | struct irq_info *slot, *slot_base; |
Bin Meng | 9c7dea6 | 2015-05-25 22:35:04 +0800 | [diff] [blame] | 96 | int irq_entries = 0; |
| 97 | int i; |
| 98 | int ret; |
| 99 | |
Simon Glass | b565d66 | 2016-01-19 21:32:28 -0700 | [diff] [blame] | 100 | node = dev->of_offset; |
Bin Meng | 9c7dea6 | 2015-05-25 22:35:04 +0800 | [diff] [blame] | 101 | |
| 102 | /* extract the bdf from fdt_pci_addr */ |
Bin Meng | b46c208 | 2016-02-01 01:40:51 -0800 | [diff] [blame] | 103 | priv->bdf = dm_pci_get_bdf(dev->parent); |
Bin Meng | 9c7dea6 | 2015-05-25 22:35:04 +0800 | [diff] [blame] | 104 | |
| 105 | ret = fdt_find_string(blob, node, "intel,pirq-config", "pci"); |
| 106 | if (!ret) { |
Bin Meng | b46c208 | 2016-02-01 01:40:51 -0800 | [diff] [blame] | 107 | priv->config = PIRQ_VIA_PCI; |
Bin Meng | 9c7dea6 | 2015-05-25 22:35:04 +0800 | [diff] [blame] | 108 | } else { |
| 109 | ret = fdt_find_string(blob, node, "intel,pirq-config", "ibase"); |
| 110 | if (!ret) |
Bin Meng | b46c208 | 2016-02-01 01:40:51 -0800 | [diff] [blame] | 111 | priv->config = PIRQ_VIA_IBASE; |
Bin Meng | 9c7dea6 | 2015-05-25 22:35:04 +0800 | [diff] [blame] | 112 | else |
| 113 | return -EINVAL; |
| 114 | } |
| 115 | |
Simon Glass | 9e3ff9c | 2015-08-10 07:05:06 -0600 | [diff] [blame] | 116 | ret = fdtdec_get_int(blob, node, "intel,pirq-link", -1); |
| 117 | if (ret == -1) |
Bin Meng | 9c7dea6 | 2015-05-25 22:35:04 +0800 | [diff] [blame] | 118 | return ret; |
Bin Meng | b46c208 | 2016-02-01 01:40:51 -0800 | [diff] [blame] | 119 | priv->link_base = ret; |
Bin Meng | 9c7dea6 | 2015-05-25 22:35:04 +0800 | [diff] [blame] | 120 | |
Bin Meng | b46c208 | 2016-02-01 01:40:51 -0800 | [diff] [blame] | 121 | priv->irq_mask = fdtdec_get_int(blob, node, |
| 122 | "intel,pirq-mask", PIRQ_BITMAP); |
Bin Meng | 9c7dea6 | 2015-05-25 22:35:04 +0800 | [diff] [blame] | 123 | |
Bin Meng | 07ac84e | 2016-05-07 07:46:13 -0700 | [diff] [blame] | 124 | if (IS_ENABLED(CONFIG_GENERATE_ACPI_TABLE)) { |
| 125 | /* Reserve IRQ9 for SCI */ |
| 126 | priv->irq_mask &= ~(1 << 9); |
| 127 | } |
| 128 | |
Bin Meng | b46c208 | 2016-02-01 01:40:51 -0800 | [diff] [blame] | 129 | if (priv->config == PIRQ_VIA_IBASE) { |
Bin Meng | 9c7dea6 | 2015-05-25 22:35:04 +0800 | [diff] [blame] | 130 | int ibase_off; |
| 131 | |
| 132 | ibase_off = fdtdec_get_int(blob, node, "intel,ibase-offset", 0); |
| 133 | if (!ibase_off) |
| 134 | return -EINVAL; |
| 135 | |
| 136 | /* |
| 137 | * Here we assume that the IBASE register has already been |
| 138 | * properly configured by U-Boot before. |
| 139 | * |
| 140 | * By 'valid' we mean: |
| 141 | * 1) a valid memory space carved within system memory space |
| 142 | * assigned to IBASE register block. |
| 143 | * 2) memory range decoding is enabled. |
| 144 | * Hence we don't do any santify test here. |
| 145 | */ |
Bin Meng | 248c4fa | 2016-02-01 01:40:52 -0800 | [diff] [blame] | 146 | dm_pci_read_config32(dev->parent, ibase_off, &priv->ibase); |
Bin Meng | b46c208 | 2016-02-01 01:40:51 -0800 | [diff] [blame] | 147 | priv->ibase &= ~0xf; |
Bin Meng | 9c7dea6 | 2015-05-25 22:35:04 +0800 | [diff] [blame] | 148 | } |
| 149 | |
Bin Meng | d4e61f5 | 2016-05-07 07:46:14 -0700 | [diff] [blame] | 150 | priv->actl_8bit = fdtdec_get_bool(blob, node, "intel,actl-8bit"); |
| 151 | priv->actl_addr = fdtdec_get_int(blob, node, "intel,actl-addr", 0); |
| 152 | |
Bin Meng | 9c7dea6 | 2015-05-25 22:35:04 +0800 | [diff] [blame] | 153 | cell = fdt_getprop(blob, node, "intel,pirq-routing", &len); |
Simon Glass | 9e3ff9c | 2015-08-10 07:05:06 -0600 | [diff] [blame] | 154 | if (!cell || len % sizeof(struct pirq_routing)) |
Bin Meng | 9c7dea6 | 2015-05-25 22:35:04 +0800 | [diff] [blame] | 155 | return -EINVAL; |
Simon Glass | 9e3ff9c | 2015-08-10 07:05:06 -0600 | [diff] [blame] | 156 | count = len / sizeof(struct pirq_routing); |
Bin Meng | 9c7dea6 | 2015-05-25 22:35:04 +0800 | [diff] [blame] | 157 | |
Simon Glass | 9e3ff9c | 2015-08-10 07:05:06 -0600 | [diff] [blame] | 158 | rt = calloc(1, sizeof(struct irq_routing_table)); |
Bin Meng | 9c7dea6 | 2015-05-25 22:35:04 +0800 | [diff] [blame] | 159 | if (!rt) |
| 160 | return -ENOMEM; |
Bin Meng | 9c7dea6 | 2015-05-25 22:35:04 +0800 | [diff] [blame] | 161 | |
| 162 | /* Populate the PIRQ table fields */ |
| 163 | rt->signature = PIRQ_SIGNATURE; |
| 164 | rt->version = PIRQ_VERSION; |
Bin Meng | b46c208 | 2016-02-01 01:40:51 -0800 | [diff] [blame] | 165 | rt->rtr_bus = PCI_BUS(priv->bdf); |
| 166 | rt->rtr_devfn = (PCI_DEV(priv->bdf) << 3) | PCI_FUNC(priv->bdf); |
Bin Meng | 9c7dea6 | 2015-05-25 22:35:04 +0800 | [diff] [blame] | 167 | rt->rtr_vendor = PCI_VENDOR_ID_INTEL; |
| 168 | rt->rtr_device = PCI_DEVICE_ID_INTEL_ICH7_31; |
| 169 | |
Bin Meng | df81749 | 2015-06-23 12:18:47 +0800 | [diff] [blame] | 170 | slot_base = rt->slots; |
Bin Meng | 9c7dea6 | 2015-05-25 22:35:04 +0800 | [diff] [blame] | 171 | |
| 172 | /* Now fill in the irq_info entries in the PIRQ table */ |
Simon Glass | 9e3ff9c | 2015-08-10 07:05:06 -0600 | [diff] [blame] | 173 | for (i = 0; i < count; |
| 174 | i++, cell += sizeof(struct pirq_routing) / sizeof(u32)) { |
Bin Meng | 9c7dea6 | 2015-05-25 22:35:04 +0800 | [diff] [blame] | 175 | struct pirq_routing pr; |
| 176 | |
| 177 | pr.bdf = fdt_addr_to_cpu(cell[0]); |
| 178 | pr.pin = fdt_addr_to_cpu(cell[1]); |
| 179 | pr.pirq = fdt_addr_to_cpu(cell[2]); |
| 180 | |
| 181 | debug("irq_info %d: b.d.f %x.%x.%x INT%c PIRQ%c\n", |
| 182 | i, PCI_BUS(pr.bdf), PCI_DEV(pr.bdf), |
| 183 | PCI_FUNC(pr.bdf), 'A' + pr.pin - 1, |
| 184 | 'A' + pr.pirq); |
Bin Meng | df81749 | 2015-06-23 12:18:47 +0800 | [diff] [blame] | 185 | |
| 186 | slot = check_dup_entry(slot_base, irq_entries, |
| 187 | PCI_BUS(pr.bdf), PCI_DEV(pr.bdf)); |
| 188 | if (slot) { |
| 189 | debug("found entry for bus %d device %d, ", |
| 190 | PCI_BUS(pr.bdf), PCI_DEV(pr.bdf)); |
| 191 | |
| 192 | if (slot->irq[pr.pin - 1].link) { |
| 193 | debug("skipping\n"); |
| 194 | |
| 195 | /* |
| 196 | * Sanity test on the routed PIRQ pin |
| 197 | * |
| 198 | * If they don't match, show a warning to tell |
| 199 | * there might be something wrong with the PIRQ |
| 200 | * routing information in the device tree. |
| 201 | */ |
| 202 | if (slot->irq[pr.pin - 1].link != |
Bin Meng | b46c208 | 2016-02-01 01:40:51 -0800 | [diff] [blame] | 203 | LINK_N2V(pr.pirq, priv->link_base)) |
Bin Meng | df81749 | 2015-06-23 12:18:47 +0800 | [diff] [blame] | 204 | debug("WARNING: Inconsistent PIRQ routing information\n"); |
Bin Meng | df81749 | 2015-06-23 12:18:47 +0800 | [diff] [blame] | 205 | continue; |
| 206 | } |
Simon Glass | 9e3ff9c | 2015-08-10 07:05:06 -0600 | [diff] [blame] | 207 | } else { |
| 208 | slot = slot_base + irq_entries++; |
Bin Meng | df81749 | 2015-06-23 12:18:47 +0800 | [diff] [blame] | 209 | } |
Simon Glass | 9e3ff9c | 2015-08-10 07:05:06 -0600 | [diff] [blame] | 210 | debug("writing INT%c\n", 'A' + pr.pin - 1); |
Bin Meng | b46c208 | 2016-02-01 01:40:51 -0800 | [diff] [blame] | 211 | fill_irq_info(priv, slot, PCI_BUS(pr.bdf), PCI_DEV(pr.bdf), |
| 212 | pr.pin, pr.pirq); |
Bin Meng | 9c7dea6 | 2015-05-25 22:35:04 +0800 | [diff] [blame] | 213 | } |
| 214 | |
| 215 | rt->size = irq_entries * sizeof(struct irq_info) + 32; |
| 216 | |
| 217 | pirq_routing_table = rt; |
| 218 | |
| 219 | return 0; |
| 220 | } |
| 221 | |
Bin Meng | d4e61f5 | 2016-05-07 07:46:14 -0700 | [diff] [blame] | 222 | static void irq_enable_sci(struct udevice *dev) |
| 223 | { |
| 224 | struct irq_router *priv = dev_get_priv(dev); |
| 225 | |
| 226 | if (priv->actl_8bit) { |
| 227 | /* Bit7 must be turned on to enable ACPI */ |
| 228 | dm_pci_write_config8(dev->parent, priv->actl_addr, 0x80); |
| 229 | } else { |
| 230 | /* Write 0 to enable SCI on IRQ9 */ |
| 231 | if (priv->config == PIRQ_VIA_PCI) |
| 232 | dm_pci_write_config32(dev->parent, priv->actl_addr, 0); |
| 233 | else |
| 234 | writel(0, priv->ibase + priv->actl_addr); |
| 235 | } |
| 236 | } |
| 237 | |
Simon Glass | d3b884b | 2016-01-19 21:32:27 -0700 | [diff] [blame] | 238 | int irq_router_common_init(struct udevice *dev) |
Simon Glass | e76187a | 2016-01-19 21:32:25 -0700 | [diff] [blame] | 239 | { |
Simon Glass | 7e4be12 | 2015-08-10 07:05:08 -0600 | [diff] [blame] | 240 | int ret; |
| 241 | |
Simon Glass | b565d66 | 2016-01-19 21:32:28 -0700 | [diff] [blame] | 242 | ret = create_pirq_routing_table(dev); |
Simon Glass | 7e4be12 | 2015-08-10 07:05:08 -0600 | [diff] [blame] | 243 | if (ret) { |
Bin Meng | 9c7dea6 | 2015-05-25 22:35:04 +0800 | [diff] [blame] | 244 | debug("Failed to create pirq routing table\n"); |
Simon Glass | 7e4be12 | 2015-08-10 07:05:08 -0600 | [diff] [blame] | 245 | return ret; |
Bin Meng | 9c7dea6 | 2015-05-25 22:35:04 +0800 | [diff] [blame] | 246 | } |
Simon Glass | 7e4be12 | 2015-08-10 07:05:08 -0600 | [diff] [blame] | 247 | /* Route PIRQ */ |
Bin Meng | b46c208 | 2016-02-01 01:40:51 -0800 | [diff] [blame] | 248 | pirq_route_irqs(dev, pirq_routing_table->slots, |
Simon Glass | 7e4be12 | 2015-08-10 07:05:08 -0600 | [diff] [blame] | 249 | get_irq_slot_count(pirq_routing_table)); |
| 250 | |
Bin Meng | d4e61f5 | 2016-05-07 07:46:14 -0700 | [diff] [blame] | 251 | if (IS_ENABLED(CONFIG_GENERATE_ACPI_TABLE)) |
| 252 | irq_enable_sci(dev); |
| 253 | |
Simon Glass | 7e4be12 | 2015-08-10 07:05:08 -0600 | [diff] [blame] | 254 | return 0; |
Bin Meng | 9c7dea6 | 2015-05-25 22:35:04 +0800 | [diff] [blame] | 255 | } |
| 256 | |
Simon Glass | d3b884b | 2016-01-19 21:32:27 -0700 | [diff] [blame] | 257 | int irq_router_probe(struct udevice *dev) |
| 258 | { |
| 259 | return irq_router_common_init(dev); |
| 260 | } |
| 261 | |
Bin Meng | 9c7dea6 | 2015-05-25 22:35:04 +0800 | [diff] [blame] | 262 | u32 write_pirq_routing_table(u32 addr) |
| 263 | { |
Bin Meng | 67b2497 | 2015-05-25 22:35:07 +0800 | [diff] [blame] | 264 | if (!pirq_routing_table) |
| 265 | return addr; |
| 266 | |
Bin Meng | 9c7dea6 | 2015-05-25 22:35:04 +0800 | [diff] [blame] | 267 | return copy_pirq_routing_table(addr, pirq_routing_table); |
| 268 | } |
Simon Glass | e76187a | 2016-01-19 21:32:25 -0700 | [diff] [blame] | 269 | |
| 270 | static const struct udevice_id irq_router_ids[] = { |
| 271 | { .compatible = "intel,irq-router" }, |
| 272 | { } |
| 273 | }; |
| 274 | |
| 275 | U_BOOT_DRIVER(irq_router_drv) = { |
| 276 | .name = "intel_irq", |
| 277 | .id = UCLASS_IRQ, |
| 278 | .of_match = irq_router_ids, |
| 279 | .probe = irq_router_probe, |
Bin Meng | b46c208 | 2016-02-01 01:40:51 -0800 | [diff] [blame] | 280 | .priv_auto_alloc_size = sizeof(struct irq_router), |
Simon Glass | e76187a | 2016-01-19 21:32:25 -0700 | [diff] [blame] | 281 | }; |
| 282 | |
| 283 | UCLASS_DRIVER(irq) = { |
| 284 | .id = UCLASS_IRQ, |
| 285 | .name = "irq", |
| 286 | }; |