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wdenk2262cfe2002-11-18 00:14:45 +00001/*
Graeme Russdbf71152011-04-13 19:43:26 +10002 * (C) Copyright 2008-2011
3 * Graeme Russ, <graeme.russ@gmail.com>
4 *
wdenk2262cfe2002-11-18 00:14:45 +00005 * (C) Copyright 2002
Albert ARIBAUDfa82f872011-08-04 18:45:45 +02006 * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
wdenk8bde7f72003-06-27 21:31:46 +00007 *
wdenk2262cfe2002-11-18 00:14:45 +00008 * (C) Copyright 2002
9 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
10 * Marius Groeger <mgroeger@sysgo.de>
11 *
12 * (C) Copyright 2002
13 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
14 * Alex Zuepke <azu@sysgo.de>
15 *
Bin Meng52f952b2014-11-09 22:18:56 +080016 * Part of this file is adapted from coreboot
17 * src/arch/x86/lib/cpu.c
18 *
Wolfgang Denk1a459662013-07-08 09:37:19 +020019 * SPDX-License-Identifier: GPL-2.0+
wdenk2262cfe2002-11-18 00:14:45 +000020 */
21
wdenk2262cfe2002-11-18 00:14:45 +000022#include <common.h>
23#include <command.h>
Bin Meng6e6f4ce2015-06-17 11:15:36 +080024#include <dm.h>
Simon Glass200182a2014-10-10 08:21:55 -060025#include <errno.h>
26#include <malloc.h>
Bin Mengd8906c12016-06-08 05:07:38 -070027#include <syscon.h>
Bin Mengb7279612017-04-21 07:24:32 -070028#include <asm/acpi_s3.h>
Bin Meng3a34cae2017-04-21 07:24:37 -070029#include <asm/acpi_table.h>
Stefan Reinauer095593c2012-12-02 04:49:50 +000030#include <asm/control_regs.h>
Bin Mengd19c9072016-05-11 07:45:01 -070031#include <asm/coreboot_tables.h>
Simon Glass200182a2014-10-10 08:21:55 -060032#include <asm/cpu.h>
Bin Meng6e6f4ce2015-06-17 11:15:36 +080033#include <asm/lapic.h>
Simon Glasse77b62e2016-03-11 22:07:11 -070034#include <asm/microcode.h>
Bin Meng6e6f4ce2015-06-17 11:15:36 +080035#include <asm/mp.h>
Bin Meng0c2b7ee2016-05-11 07:45:00 -070036#include <asm/mrccache.h>
Bin Meng43dd22f2015-07-06 16:31:30 +080037#include <asm/msr.h>
38#include <asm/mtrr.h>
Simon Glassa49e3c72014-11-12 22:42:26 -070039#include <asm/post.h>
Graeme Russc53fd2b2011-02-12 15:11:30 +110040#include <asm/processor.h>
Graeme Russ0c24c9c2011-02-12 15:11:32 +110041#include <asm/processor-flags.h>
Graeme Russ3f5f18d2008-12-07 10:29:02 +110042#include <asm/interrupt.h>
Bin Meng5e2400e2015-04-24 18:10:04 +080043#include <asm/tables.h>
Gabe Black60a9b6b2011-11-16 23:32:50 +000044#include <linux/compiler.h>
wdenk2262cfe2002-11-18 00:14:45 +000045
Bin Meng52f952b2014-11-09 22:18:56 +080046DECLARE_GLOBAL_DATA_PTR;
47
Bin Meng52f952b2014-11-09 22:18:56 +080048static const char *const x86_vendor_name[] = {
49 [X86_VENDOR_INTEL] = "Intel",
50 [X86_VENDOR_CYRIX] = "Cyrix",
51 [X86_VENDOR_AMD] = "AMD",
52 [X86_VENDOR_UMC] = "UMC",
53 [X86_VENDOR_NEXGEN] = "NexGen",
54 [X86_VENDOR_CENTAUR] = "Centaur",
55 [X86_VENDOR_RISE] = "Rise",
56 [X86_VENDOR_TRANSMETA] = "Transmeta",
57 [X86_VENDOR_NSC] = "NSC",
58 [X86_VENDOR_SIS] = "SiS",
59};
60
Gabe Blackf30fc4d2012-10-20 12:33:10 +000061int __weak x86_cleanup_before_linux(void)
62{
Simon Glass79497032013-04-17 16:13:35 +000063#ifdef CONFIG_BOOTSTAGE_STASH
Simon Glassee2b2432015-03-02 17:04:37 -070064 bootstage_stash((void *)CONFIG_BOOTSTAGE_STASH_ADDR,
Simon Glass79497032013-04-17 16:13:35 +000065 CONFIG_BOOTSTAGE_STASH_SIZE);
66#endif
67
Gabe Blackf30fc4d2012-10-20 12:33:10 +000068 return 0;
69}
70
Graeme Russd6532442011-12-27 22:46:43 +110071int x86_init_cache(void)
72{
73 enable_caches();
74
wdenk2262cfe2002-11-18 00:14:45 +000075 return 0;
76}
Graeme Russd6532442011-12-27 22:46:43 +110077int init_cache(void) __attribute__((weak, alias("x86_init_cache")));
wdenk2262cfe2002-11-18 00:14:45 +000078
Wolfgang Denk54841ab2010-06-28 22:00:46 +020079int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
wdenk2262cfe2002-11-18 00:14:45 +000080{
Graeme Russ717979f2011-11-08 02:33:13 +000081 printf("resetting ...\n");
Graeme Russdbf71152011-04-13 19:43:26 +100082
83 /* wait 50 ms */
84 udelay(50000);
wdenk2262cfe2002-11-18 00:14:45 +000085 disable_interrupts();
86 reset_cpu(0);
87
88 /*NOTREACHED*/
89 return 0;
90}
91
Graeme Russ717979f2011-11-08 02:33:13 +000092void flush_cache(unsigned long dummy1, unsigned long dummy2)
wdenk2262cfe2002-11-18 00:14:45 +000093{
94 asm("wbinvd\n");
wdenk2262cfe2002-11-18 00:14:45 +000095}
Graeme Russ3f5f18d2008-12-07 10:29:02 +110096
Simon Glasse1ffd812014-11-06 13:20:08 -070097__weak void reset_cpu(ulong addr)
Graeme Russ3f5f18d2008-12-07 10:29:02 +110098{
Simon Glassff6a8f32015-04-28 20:11:29 -060099 /* Do a hard reset through the chipset's reset control register */
Simon Glass2a605d42016-03-11 22:06:59 -0700100 outb(SYS_RST | RST_CPU, IO_PORT_RESET);
Simon Glassff6a8f32015-04-28 20:11:29 -0600101 for (;;)
102 cpu_hlt();
103}
104
105void x86_full_reset(void)
106{
Simon Glass2a605d42016-03-11 22:06:59 -0700107 outb(FULL_RST | SYS_RST | RST_CPU, IO_PORT_RESET);
Graeme Russ3f5f18d2008-12-07 10:29:02 +1100108}
Stefan Reinauer095593c2012-12-02 04:49:50 +0000109
Stefan Reinauer095593c2012-12-02 04:49:50 +0000110/* Define these functions to allow ehch-hcd to function */
111void flush_dcache_range(unsigned long start, unsigned long stop)
112{
113}
114
115void invalidate_dcache_range(unsigned long start, unsigned long stop)
116{
117}
Simon Glass89371402013-02-28 19:26:11 +0000118
119void dcache_enable(void)
120{
121 enable_caches();
122}
123
124void dcache_disable(void)
125{
126 disable_caches();
127}
128
129void icache_enable(void)
130{
131}
132
133void icache_disable(void)
134{
135}
136
137int icache_status(void)
138{
139 return 1;
140}
Simon Glass7bddac92014-10-10 08:21:52 -0600141
Bin Meng52f952b2014-11-09 22:18:56 +0800142const char *cpu_vendor_name(int vendor)
143{
144 const char *name;
145 name = "<invalid cpu vendor>";
146 if ((vendor < (ARRAY_SIZE(x86_vendor_name))) &&
147 (x86_vendor_name[vendor] != 0))
148 name = x86_vendor_name[vendor];
149
150 return name;
151}
152
Simon Glass727c1a92014-11-10 18:00:26 -0700153char *cpu_get_name(char *name)
Bin Meng52f952b2014-11-09 22:18:56 +0800154{
Simon Glass727c1a92014-11-10 18:00:26 -0700155 unsigned int *name_as_ints = (unsigned int *)name;
Bin Meng52f952b2014-11-09 22:18:56 +0800156 struct cpuid_result regs;
Simon Glass727c1a92014-11-10 18:00:26 -0700157 char *ptr;
Bin Meng52f952b2014-11-09 22:18:56 +0800158 int i;
159
Simon Glass727c1a92014-11-10 18:00:26 -0700160 /* This bit adds up to 48 bytes */
Bin Meng52f952b2014-11-09 22:18:56 +0800161 for (i = 0; i < 3; i++) {
162 regs = cpuid(0x80000002 + i);
163 name_as_ints[i * 4 + 0] = regs.eax;
164 name_as_ints[i * 4 + 1] = regs.ebx;
165 name_as_ints[i * 4 + 2] = regs.ecx;
166 name_as_ints[i * 4 + 3] = regs.edx;
167 }
Simon Glass727c1a92014-11-10 18:00:26 -0700168 name[CPU_MAX_NAME_LEN - 1] = '\0';
Bin Meng52f952b2014-11-09 22:18:56 +0800169
170 /* Skip leading spaces. */
Simon Glass727c1a92014-11-10 18:00:26 -0700171 ptr = name;
172 while (*ptr == ' ')
173 ptr++;
Bin Meng52f952b2014-11-09 22:18:56 +0800174
Simon Glass727c1a92014-11-10 18:00:26 -0700175 return ptr;
Bin Meng52f952b2014-11-09 22:18:56 +0800176}
177
Simon Glass727c1a92014-11-10 18:00:26 -0700178int default_print_cpuinfo(void)
Simon Glass92cc94a2014-10-10 08:21:54 -0600179{
Bin Meng52f952b2014-11-09 22:18:56 +0800180 printf("CPU: %s, vendor %s, device %xh\n",
181 cpu_has_64bit() ? "x86_64" : "x86",
182 cpu_vendor_name(gd->arch.x86_vendor), gd->arch.x86_device);
Simon Glass92cc94a2014-10-10 08:21:54 -0600183
Bin Mengb7279612017-04-21 07:24:32 -0700184#ifdef CONFIG_HAVE_ACPI_RESUME
185 debug("ACPI previous sleep state: %s\n",
186 acpi_ss_string(gd->arch.prev_sleep_state));
187#endif
188
Simon Glass92cc94a2014-10-10 08:21:54 -0600189 return 0;
190}
Simon Glass200182a2014-10-10 08:21:55 -0600191
Simon Glassa49e3c72014-11-12 22:42:26 -0700192void show_boot_progress(int val)
193{
Simon Glassa49e3c72014-11-12 22:42:26 -0700194 outb(val, POST_PORT);
195}
Bin Meng5e2400e2015-04-24 18:10:04 +0800196
197#ifndef CONFIG_SYS_COREBOOT
Bin Meng1e2f7b92016-05-11 07:44:56 -0700198/*
199 * Implement a weak default function for boards that optionally
200 * need to clean up the system before jumping to the kernel.
201 */
202__weak void board_final_cleanup(void)
203{
204}
205
Bin Meng5e2400e2015-04-24 18:10:04 +0800206int last_stage_init(void)
207{
Bin Mengbffd7982017-04-21 07:24:41 -0700208 board_final_cleanup();
209
Bin Meng3a34cae2017-04-21 07:24:37 -0700210#if CONFIG_HAVE_ACPI_RESUME
211 void *wake_vector = acpi_find_wakeup_vector();
212
213 if (wake_vector != NULL && gd->arch.prev_sleep_state == ACPI_S3)
214 acpi_resume(wake_vector);
215#endif
216
Bin Meng5e2400e2015-04-24 18:10:04 +0800217 write_tables();
218
219 return 0;
220}
221#endif
Simon Glassbcb0c612015-04-29 22:26:01 -0600222
Simon Glassafd5d502016-01-17 16:11:28 -0700223static int x86_init_cpus(void)
Simon Glassbcb0c612015-04-29 22:26:01 -0600224{
Bin Meng6e6f4ce2015-06-17 11:15:36 +0800225#ifdef CONFIG_SMP
226 debug("Init additional CPUs\n");
227 x86_mp_init();
Bin Mengc77b8912015-07-22 01:21:12 -0700228#else
229 struct udevice *dev;
230
231 /*
232 * This causes the cpu-x86 driver to be probed.
233 * We don't check return value here as we want to allow boards
234 * which have not been converted to use cpu uclass driver to boot.
235 */
236 uclass_first_device(UCLASS_CPU, &dev);
Bin Meng6e6f4ce2015-06-17 11:15:36 +0800237#endif
238
Simon Glassbcb0c612015-04-29 22:26:01 -0600239 return 0;
240}
241
242int cpu_init_r(void)
243{
Simon Glassac643e02016-01-17 16:11:30 -0700244 struct udevice *dev;
245 int ret;
246
247 if (!ll_boot_init())
248 return 0;
249
250 ret = x86_init_cpus();
251 if (ret)
252 return ret;
253
254 /*
255 * Set up the northbridge, PCH and LPC if available. Note that these
256 * may have had some limited pre-relocation init if they were probed
257 * before relocation, but this is post relocation.
258 */
259 uclass_first_device(UCLASS_NORTHBRIDGE, &dev);
260 uclass_first_device(UCLASS_PCH, &dev);
261 uclass_first_device(UCLASS_LPC, &dev);
Simon Glasse49ccea2015-08-04 12:34:00 -0600262
Bin Mengd8906c12016-06-08 05:07:38 -0700263 /* Set up pin control if available */
264 ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, &dev);
265 debug("%s, pinctrl=%p, ret=%d\n", __func__, dev, ret);
266
Simon Glasse49ccea2015-08-04 12:34:00 -0600267 return 0;
Simon Glassbcb0c612015-04-29 22:26:01 -0600268}
Bin Meng0c2b7ee2016-05-11 07:45:00 -0700269
270#ifndef CONFIG_EFI_STUB
271int reserve_arch(void)
272{
273#ifdef CONFIG_ENABLE_MRC_CACHE
Bin Mengd19c9072016-05-11 07:45:01 -0700274 mrccache_reserve();
Bin Meng0c2b7ee2016-05-11 07:45:00 -0700275#endif
Bin Mengd19c9072016-05-11 07:45:01 -0700276
277#ifdef CONFIG_SEABIOS
278 high_table_reserve();
279#endif
280
Bin Mengba658082017-04-21 07:24:39 -0700281#if defined(CONFIG_HAVE_ACPI_RESUME) && defined(CONFIG_HAVE_FSP)
282 /*
283 * Save stack address to CMOS so that at next S3 boot,
284 * we can use it as the stack address for fsp_contiue()
285 */
286 fsp_save_s3_stack();
287#endif
288
Bin Mengd19c9072016-05-11 07:45:01 -0700289 return 0;
Bin Meng0c2b7ee2016-05-11 07:45:00 -0700290}
291#endif