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gerrit.cesnet.cz / github / trini / u-boot / e7670f6c1e52ae6d2a43ff75a8bcfa7a5c86e47b / . / onenand_ipl / board / apollon / low_levelinit.S
blob: 417a5a7e0da9de29cef0ba3ab44331648a6958bf [file] [log] [blame]
Kyungmin Park751b9b52008-01-17 16:43:25 +0900[diff] [blame]1/*
2 * Board specific setup info
3 *
4 * (C) Copyright 2005-2008 Samsung Electronics
5 * Kyungmin Park <kyungmin.park@samsung.com>
6 *
7 * Derived from board/omap2420h4/platform.S
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#include <config.h>
29#include <asm/arch/omap2420.h>
30#include <asm/arch/mem.h>
31#include <asm/arch/clocks.h>
32
33#define APOLLON_CS0_BASE 0x00000000
34
35#ifdef PRCM_CONFIG_I
36#define SDRC_ACTIM_CTRLA_0_VAL 0x7BA35907
37#define SDRC_ACTIM_CTRLB_0_VAL 0x00000013
38#define SDRC_RFR_CTRL_0_VAL 0x00044C01
39
40/* GPMC */
41#define APOLLON_GPMC_CONFIG1_0 0xe30d1201
42#define APOLLON_GPMC_CONFIG2_0 0x000c1000
43#define APOLLON_GPMC_CONFIG3_0 0x00030400
44#define APOLLON_GPMC_CONFIG4_0 0x0B841006
45#define APOLLON_GPMC_CONFIG5_0 0x020F0C11
46#define APOLLON_GPMC_CONFIG6_0 0x00000000
47#define APOLLON_GPMC_CONFIG7_0 (0x00000e40 | (APOLLON_CS0_BASE >> 24))
48
49#elif defined(PRCM_CONFIG_II)
50#define SDRC_ACTIM_CTRLA_0_VAL 0x4A59B485
51#define SDRC_ACTIM_CTRLB_0_VAL 0x0000000C
52#define SDRC_RFR_CTRL_0_VAL 0x00030001
53
54/* GPMC */
55#define APOLLON_GPMC_CONFIG1_0 0xe30d1201
56#define APOLLON_GPMC_CONFIG2_0 0x00080E81
57#define APOLLON_GPMC_CONFIG3_0 0x00030400
58#define APOLLON_GPMC_CONFIG4_0 0x08041586
59#define APOLLON_GPMC_CONFIG5_0 0x020C090E
60#define APOLLON_GPMC_CONFIG6_0 0x00000000
61#define APOLLON_GPMC_CONFIG7_0 (0x00000e40 | (APOLLON_CS0_BASE >> 24))
62
63#else
64#error "Please configure PRCM schecm"
65#endif
66
67_TEXT_BASE:
68 .word TEXT_BASE /* sdram load addr from config.mk */
69
70.globl lowlevel_init
71lowlevel_init:
72 mov r3, r0 /* save skip information */
73
74 /* Disable watchdog */
75 ldr r0, =WD2_BASE
76 ldr r1, =WD_UNLOCK1
77 str r1, [r0, #WSPR]
78
79 ldr r1, =WD_UNLOCK2
80 str r1, [r0, #WSPR]
81
82#ifdef DEBUG_LED
83 /* LED0 OFF */
84 ldr r0, =0x480000E5 /* ball AA10, mode 3 */
85 mov r1, #0x0b
86 strb r1, [r0]
87#endif
88
89 /* Pin muxing for SDRC */
90 mov r1, #0x00
91 ldr r0, =0x480000A1 /* ball C12, mode 0 */
92 strb r1, [r0]
93
94 ldr r0, =0x48000032 /* ball D11, mode 0 */
95 strb r1, [r0]
96
97 ldr r0, =0x480000A3 /* ball B13, mode 0 */
98 strb r1, [r0]
99
100 /* SDRC setting */
101 ldr r0, =OMAP2420_SDRC_BASE
102 ldr r1, =0x00000010
103 str r1, [r0, #0x10]
104
105 ldr r1, =0x00000100
106 str r1, [r0, #0x44]
107
108 /* SDRC CS0 configuration */
109#ifdef CONFIG_APOLLON_PLUS
110 ldr r1, =0x01702011
111#else
112 ldr r1, =0x00d04011
113#endif
114 str r1, [r0, #0x80]
115
116 ldr r1, =SDRC_ACTIM_CTRLA_0_VAL
117 str r1, [r0, #0x9C]
118
119 ldr r1, =SDRC_ACTIM_CTRLB_0_VAL
120 str r1, [r0, #0xA0]
121
122 ldr r1, =SDRC_RFR_CTRL_0_VAL
123 str r1, [r0, #0xA4]
124
125 ldr r1, =0x00000041
126 str r1, [r0, #0x70]
127
128 /* Manual command sequence */
129 ldr r1, =0x00000007
130 str r1, [r0, #0xA8]
131
132 ldr r1, =0x00000000
133 str r1, [r0, #0xA8]
134
135 ldr r1, =0x00000001
136 str r1, [r0, #0xA8]
137
138 ldr r1, =0x00000002
139 str r1, [r0, #0xA8]
140 str r1, [r0, #0xA8]
141
142 /*
143 * CS0 SDRC Mode register
144 * Burst length = 4 - DDR memory
145 * Serial mode
146 * CAS latency = 3
147 */
148 ldr r1, =0x00000032
149 str r1, [r0, #0x84]
150
151 /* Note: You MUST set EMR values */
152 /* EMR1 & EMR2 */
153 ldr r1, =0x00000000
154 str r1, [r0, #0x88]
155 str r1, [r0, #0x8C]
156
157#ifdef OLD_SDRC_DLLA_CTRL
158 /* SDRC_DLLA_CTRL */
159 ldr r1, =0x00007306
160 str r1, [r0, #0x60]
161
162 ldr r1, =0x00007303
163 str r1, [r0, #0x60]
164#else
165 /* SDRC_DLLA_CTRL */
166 ldr r1, =0x00000506
167 str r1, [r0, #0x60]
168
169 ldr r1, =0x00000503
170 str r1, [r0, #0x60]
171#endif
172
173#ifdef __BROKEN_FEATURE__
174 /* SDRC_DLLB_CTRL */
175 ldr r1, =0x00000506
176 str r1, [r0, #0x68]
177
178 ldr r1, =0x00000503
179 str r1, [r0, #0x68]
180#endif
181
182 /* little delay after init */
183 mov r2, #0x1800
1841:
185 subs r2, r2, #0x1
186 bne 1b
187
188 ldr sp, SRAM_STACK
189 str ip, [sp] /* stash old link register */
190 mov ip, lr /* save link reg across call */
191 mov r0, r3 /* pass skip info to s_init */
192
193 bl s_init /* go setup pll,mux,memory */
194
195 ldr ip, [sp] /* restore save ip */
196 mov lr, ip /* restore link reg */
197
198 /* back to arch calling code */
199 mov pc, lr
200
201 /* the literal pools origin */
202 .ltorg
203
204SRAM_STACK:
205 .word LOW_LEVEL_SRAM_STACK