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gerrit.cesnet.cz / github / trini / u-boot / 5d1ee00b1fe1180503f6dfc10e87a6c6e74778f3 / . / board / renesas / sh7785lcr / lowlevel_init.S
blob: 24a0ecdf8e2c8a673a5c3a646fc6e6cb7ce79d55 [file] [log] [blame]
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +0900[diff] [blame]1/*
2 * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of
7 * the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
17 * MA 02111-1307 USA
18 */
19#include <config.h>
20#include <version.h>
21#include <asm/processor.h>
Jean-Christophe PLAGNIOL-VILLARDf7e78f32008-12-20 19:29:49 +0100[diff] [blame]22#include <asm/macro.h>
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +0900[diff] [blame]23
24#include <asm/processor.h>
25
26 .global lowlevel_init
27
28 .text
29 .align 2
30
31lowlevel_init:
32 wait_timer WAIT_200US
33 wait_timer WAIT_200US
34
35 /*------- LBSC -------*/
36 write32 MMSELR_A, MMSELR_D
37
38 /*------- DBSC2 -------*/
39 write32 DBSC2_DBCONF_A, DBSC2_DBCONF_D
40 write32 DBSC2_DBTR0_A, DBSC2_DBTR0_D
41 write32 DBSC2_DBTR1_A, DBSC2_DBTR1_D
42 write32 DBSC2_DBTR2_A, DBSC2_DBTR2_D
43 write32 DBSC2_DBFREQ_A, DBSC2_DBFREQ_D1
44 write32 DBSC2_DBFREQ_A, DBSC2_DBFREQ_D2
45 wait_timer WAIT_200US
46
47 write32 DBSC2_DBDICODTOCD_A, DBSC2_DBDICODTOCD_D
48 write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_CKE_H
49 wait_timer WAIT_200US
50 write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_PALL
51 write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS2
52 write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS3
53 write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS1_1
54 write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_MRS_1
55 write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_PALL
56 write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_REF
57 write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_REF
58 write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_MRS_2
59 wait_timer WAIT_200US
60
61 write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS1_2
62 write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS1_1
63
64 write32 DBSC2_DBEN_A, DBSC2_DBEN_D
65 write32 DBSC2_DBRFCNT1_A, DBSC2_DBRFCNT1_D
66 write32 DBSC2_DBRFCNT2_A, DBSC2_DBRFCNT2_D
67 write32 DBSC2_DBRFCNT0_A, DBSC2_DBRFCNT0_D
68 wait_timer WAIT_200US
69
70 /*------- GPIO -------*/
Nobuhiro Iwamatsu20962772010-07-22 15:14:35 +0900[diff] [blame]71 write16 PACR_A, PXCR_D
72 write16 PBCR_A, PXCR_D
73 write16 PCCR_A, PXCR_D
74 write16 PDCR_A, PXCR_D
75 write16 PECR_A, PXCR_D
76 write16 PFCR_A, PXCR_D
77 write16 PGCR_A, PXCR_D
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +0900[diff] [blame]78 write16 PHCR_A, PHCR_D
79 write16 PJCR_A, PJCR_D
80 write16 PKCR_A, PKCR_D
Nobuhiro Iwamatsu20962772010-07-22 15:14:35 +0900[diff] [blame]81 write16 PLCR_A, PXCR_D
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +0900[diff] [blame]82 write16 PMCR_A, PMCR_D
83 write16 PNCR_A, PNCR_D
Nobuhiro Iwamatsu20962772010-07-22 15:14:35 +0900[diff] [blame]84 write16 PPCR_A, PXCR_D
85 write16 PQCR_A, PXCR_D
86 write16 PRCR_A, PXCR_D
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +0900[diff] [blame]87
88 write8 PEPUPR_A, PEPUPR_D
89 write8 PHPUPR_A, PHPUPR_D
90 write8 PJPUPR_A, PJPUPR_D
91 write8 PKPUPR_A, PKPUPR_D
92 write8 PLPUPR_A, PLPUPR_D
93 write8 PMPUPR_A, PMPUPR_D
94 write8 PNPUPR_A, PNPUPR_D
95 write16 PPUPR1_A, PPUPR1_D
96 write16 PPUPR2_A, PPUPR2_D
97 write16 P1MSELR_A, P1MSELR_D
98 write16 P2MSELR_A, P2MSELR_D
99
100 /*------- LBSC -------*/
101 write32 BCR_A, BCR_D
102 write32 CS0BCR_A, CS0BCR_D
103 write32 CS0WCR_A, CS0WCR_D
104 write32 CS1BCR_A, CS1BCR_D
105 write32 CS1WCR_A, CS1WCR_D
106 write32 CS4BCR_A, CS4BCR_D
107 write32 CS4WCR_A, CS4WCR_D
108
109 mov.l PASCR_A, r0
110 mov.l @r0, r2
111 mov.l PASCR_32BIT_MODE, r1
112 tst r1, r2
113 bt lbsc_29bit
114
115 write32 CS2BCR_A, CS_USB_BCR_D
116 write32 CS2WCR_A, CS_USB_WCR_D
117 write32 CS3BCR_A, CS_SD_BCR_D
118 write32 CS3WCR_A, CS_SD_WCR_D
119 write32 CS5BCR_A, CS_I2C_BCR_D
120 write32 CS5WCR_A, CS_I2C_WCR_D
121 write32 CS6BCR_A, CS0BCR_D
122 write32 CS6WCR_A, CS0WCR_D
123 bra lbsc_end
124 nop
125
126lbsc_29bit:
127 write32 CS5BCR_A, CS_USB_BCR_D
128 write32 CS5WCR_A, CS_USB_WCR_D
129 write32 CS6BCR_A, CS_SD_BCR_D
130 write32 CS6WCR_A, CS_SD_WCR_D
131
132lbsc_end:
Yoshihiro Shimodaada93182009-03-03 15:11:17 +0900[diff] [blame]133#if defined(CONFIG_SH_32BIT)
134 /*------- set PMB -------*/
135 write32 PASCR_A, PASCR_29BIT_D
136 write32 MMUCR_A, MMUCR_D
137
138 /*****************************************************************
139 * ent virt phys v sz c wt
140 * 0 0xa0000000 0x00000000 1 64M 0 0
141 * 1 0xa4000000 0x04000000 1 16M 0 0
142 * 2 0xa6000000 0x08000000 1 16M 0 0
143 * 9 0x88000000 0x48000000 1 128M 1 1
144 * 10 0x90000000 0x50000000 1 128M 1 1
145 * 11 0x98000000 0x58000000 1 128M 1 1
146 * 13 0xa8000000 0x48000000 1 128M 0 0
147 * 14 0xb0000000 0x50000000 1 128M 0 0
148 * 15 0xb8000000 0x58000000 1 128M 0 0
149 */
150 write32 PMB_ADDR_FLASH_A, PMB_ADDR_FLASH_D
151 write32 PMB_DATA_FLASH_A, PMB_DATA_FLASH_D
152 write32 PMB_ADDR_CPLD_A, PMB_ADDR_CPLD_D
153 write32 PMB_DATA_CPLD_A, PMB_DATA_CPLD_D
154 write32 PMB_ADDR_USB_A, PMB_ADDR_USB_D
155 write32 PMB_DATA_USB_A, PMB_DATA_USB_D
156 write32 PMB_ADDR_DDR_C1_A, PMB_ADDR_DDR_C1_D
157 write32 PMB_DATA_DDR_C1_A, PMB_DATA_DDR_C1_D
158 write32 PMB_ADDR_DDR_C2_A, PMB_ADDR_DDR_C2_D
159 write32 PMB_DATA_DDR_C2_A, PMB_DATA_DDR_C2_D
160 write32 PMB_ADDR_DDR_C3_A, PMB_ADDR_DDR_C3_D
161 write32 PMB_DATA_DDR_C3_A, PMB_DATA_DDR_C3_D
162 write32 PMB_ADDR_DDR_N1_A, PMB_ADDR_DDR_N1_D
163 write32 PMB_DATA_DDR_N1_A, PMB_DATA_DDR_N1_D
164 write32 PMB_ADDR_DDR_N2_A, PMB_ADDR_DDR_N2_D
165 write32 PMB_DATA_DDR_N2_A, PMB_DATA_DDR_N2_D
166 write32 PMB_ADDR_DDR_N3_A, PMB_ADDR_DDR_N3_D
167 write32 PMB_DATA_DDR_N3_A, PMB_DATA_DDR_N3_D
168
169 write32 PASCR_A, PASCR_INIT
170 mov.l DUMMY_ADDR, r0
171 icbi @r0
172#endif
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +0900[diff] [blame]173
174 write32 CCR_A, CCR_D
175
176 rts
177 nop
178
179 .align 4
180
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +0900[diff] [blame]181/*------- GPIO -------*/
Wolfgang Denk2d941de2010-09-10 00:16:19 +0200[diff] [blame]182/* P{A,B C,D,E,F,G,L,P,Q,R}CR_D */
Nobuhiro Iwamatsu20962772010-07-22 15:14:35 +0900[diff] [blame]183PXCR_D: .word 0x0000
184
185PHCR_D: .word 0x00c0
186PJCR_D: .word 0xc3fc
187PKCR_D: .word 0x03ff
188PMCR_D: .word 0xffff
189PNCR_D: .word 0xf0c3
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +0900[diff] [blame]190
191PEPUPR_D: .long 0xff
192PHPUPR_D: .long 0x00
193PJPUPR_D: .long 0x00
194PKPUPR_D: .long 0x00
195PLPUPR_D: .long 0x00
196PMPUPR_D: .long 0xfc
197PNPUPR_D: .long 0x00
Nobuhiro Iwamatsu20962772010-07-22 15:14:35 +0900[diff] [blame]198PPUPR1_D: .word 0xffbf
199PPUPR2_D: .word 0xff00
200P1MSELR_D: .word 0x3780
201P2MSELR_D: .word 0x0000
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +0900[diff] [blame]202
Nobuhiro Iwamatsubaa9f9b2009-06-16 22:29:15 +0900[diff] [blame]203#define GPIO_BASE 0xffe70000
204PACR_A: .long GPIO_BASE + 0x00
205PBCR_A: .long GPIO_BASE + 0x02
206PCCR_A: .long GPIO_BASE + 0x04
207PDCR_A: .long GPIO_BASE + 0x06
208PECR_A: .long GPIO_BASE + 0x08
209PFCR_A: .long GPIO_BASE + 0x0a
210PGCR_A: .long GPIO_BASE + 0x0c
211PHCR_A: .long GPIO_BASE + 0x0e
212PJCR_A: .long GPIO_BASE + 0x10
213PKCR_A: .long GPIO_BASE + 0x12
214PLCR_A: .long GPIO_BASE + 0x14
215PMCR_A: .long GPIO_BASE + 0x16
216PNCR_A: .long GPIO_BASE + 0x18
217PPCR_A: .long GPIO_BASE + 0x1a
218PQCR_A: .long GPIO_BASE + 0x1c
219PRCR_A: .long GPIO_BASE + 0x1e
220PEPUPR_A: .long GPIO_BASE + 0x48
221PHPUPR_A: .long GPIO_BASE + 0x4e
222PJPUPR_A: .long GPIO_BASE + 0x50
223PKPUPR_A: .long GPIO_BASE + 0x52
224PLPUPR_A: .long GPIO_BASE + 0x54
225PMPUPR_A: .long GPIO_BASE + 0x56
226PNPUPR_A: .long GPIO_BASE + 0x58
227PPUPR1_A: .long GPIO_BASE + 0x60
228PPUPR2_A: .long GPIO_BASE + 0x62
229P1MSELR_A: .long GPIO_BASE + 0x80
230P2MSELR_A: .long GPIO_BASE + 0x82
231
Nobuhiro Iwamatsuf1cae192009-10-30 10:01:25 +0900[diff] [blame]232MMSELR_A: .long 0xfc400020
233#if defined(CONFIG_SH_32BIT)
234MMSELR_D: .long 0xa5a50005
235#else
236MMSELR_D: .long 0xa5a50002
237#endif
238
239/*------- DBSC2 -------*/
240#define DBSC2_BASE 0xfe800000
241DBSC2_DBSTATE_A: .long DBSC2_BASE + 0x0c
242DBSC2_DBEN_A: .long DBSC2_BASE + 0x10
243DBSC2_DBCMDCNT_A: .long DBSC2_BASE + 0x14
244DBSC2_DBCONF_A: .long DBSC2_BASE + 0x20
245DBSC2_DBTR0_A: .long DBSC2_BASE + 0x30
246DBSC2_DBTR1_A: .long DBSC2_BASE + 0x34
247DBSC2_DBTR2_A: .long DBSC2_BASE + 0x38
248DBSC2_DBRFCNT0_A: .long DBSC2_BASE + 0x40
249DBSC2_DBRFCNT1_A: .long DBSC2_BASE + 0x44
250DBSC2_DBRFCNT2_A: .long DBSC2_BASE + 0x48
251DBSC2_DBRFSTS_A: .long DBSC2_BASE + 0x4c
252DBSC2_DBFREQ_A: .long DBSC2_BASE + 0x50
253DBSC2_DBDICODTOCD_A:.long DBSC2_BASE + 0x54
254DBSC2_DBMRCNT_A: .long DBSC2_BASE + 0x60
255DDR_DUMMY_ACCESS_A: .long 0x40000000
256
257DBSC2_DBCONF_D: .long 0x00630002
258DBSC2_DBTR0_D: .long 0x050b1f04
259DBSC2_DBTR1_D: .long 0x00040204
260DBSC2_DBTR2_D: .long 0x02100308
261DBSC2_DBFREQ_D1: .long 0x00000000
262DBSC2_DBFREQ_D2: .long 0x00000100
263DBSC2_DBDICODTOCD_D:.long 0x000f0907
264
265DBSC2_DBCMDCNT_D_CKE_H: .long 0x00000003
266DBSC2_DBCMDCNT_D_PALL: .long 0x00000002
267DBSC2_DBCMDCNT_D_REF: .long 0x00000004
268
269DBSC2_DBMRCNT_D_EMRS2: .long 0x00020000
270DBSC2_DBMRCNT_D_EMRS3: .long 0x00030000
271DBSC2_DBMRCNT_D_EMRS1_1: .long 0x00010006
272DBSC2_DBMRCNT_D_EMRS1_2: .long 0x00010386
273DBSC2_DBMRCNT_D_MRS_1: .long 0x00000952
274DBSC2_DBMRCNT_D_MRS_2: .long 0x00000852
275
276DBSC2_DBEN_D: .long 0x00000001
277
278DBSC2_DBPDCNT0_D3: .long 0x00000080
279DBSC2_DBRFCNT1_D: .long 0x00000926
280DBSC2_DBRFCNT2_D: .long 0x00fe00fe
281DBSC2_DBRFCNT0_D: .long 0x00010000
282
283WAIT_200US: .long 33333
284
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +0900[diff] [blame]285/*------- LBSC -------*/
286PASCR_A: .long 0xff000070
287PASCR_32BIT_MODE: .long 0x80000000 /* check booting mode */
288
289BCR_A: .long BCR
290CS0BCR_A: .long CS0BCR
291CS0WCR_A: .long CS0WCR
292CS1BCR_A: .long CS1BCR
293CS1WCR_A: .long CS1WCR
294CS2BCR_A: .long CS2BCR
295CS2WCR_A: .long CS2WCR
296CS3BCR_A: .long CS3BCR
297CS3WCR_A: .long CS3WCR
298CS4BCR_A: .long CS4BCR
299CS4WCR_A: .long CS4WCR
300CS5BCR_A: .long CS5BCR
301CS5WCR_A: .long CS5WCR
302CS6BCR_A: .long CS6BCR
303CS6WCR_A: .long CS6WCR
304
305BCR_D: .long 0x80000003
306CS0BCR_D: .long 0x22222340
307CS0WCR_D: .long 0x00111118
308CS1BCR_D: .long 0x11111100
309CS1WCR_D: .long 0x33333303
310CS4BCR_D: .long 0x11111300
311CS4WCR_D: .long 0x00101012
312
313/* USB setting : 32bit mode = CS2, 29bit mode = CS5 */
314CS_USB_BCR_D: .long 0x11111200
315CS_USB_WCR_D: .long 0x00020004
316
Jean-Christophe PLAGNIOL-VILLARDe4430772008-12-20 19:29:48 +0100[diff] [blame]317/* SD setting : 32bit mode = CS3, 29bit mode = CS6 */
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +0900[diff] [blame]318CS_SD_BCR_D: .long 0x00000300
319CS_SD_WCR_D: .long 0x00030108
320
321/* I2C setting : 32bit mode = CS5, 29bit mode = CS1(already setting) */
322CS_I2C_BCR_D: .long 0x11111100
323CS_I2C_WCR_D: .long 0x00000003
324
Yoshihiro Shimodaada93182009-03-03 15:11:17 +0900[diff] [blame]325#if defined(CONFIG_SH_32BIT)
326/*------- set PMB -------*/
327PMB_ADDR_FLASH_A: .long PMB_ADDR_BASE(0)
328PMB_ADDR_CPLD_A: .long PMB_ADDR_BASE(1)
329PMB_ADDR_USB_A: .long PMB_ADDR_BASE(2)
330PMB_ADDR_DDR_C1_A: .long PMB_ADDR_BASE(9)
331PMB_ADDR_DDR_C2_A: .long PMB_ADDR_BASE(10)
332PMB_ADDR_DDR_C3_A: .long PMB_ADDR_BASE(11)
333PMB_ADDR_DDR_N1_A: .long PMB_ADDR_BASE(13)
334PMB_ADDR_DDR_N2_A: .long PMB_ADDR_BASE(14)
335PMB_ADDR_DDR_N3_A: .long PMB_ADDR_BASE(15)
336
337PMB_ADDR_FLASH_D: .long mk_pmb_addr_val(0xa0)
338PMB_ADDR_CPLD_D: .long mk_pmb_addr_val(0xa4)
339PMB_ADDR_USB_D: .long mk_pmb_addr_val(0xa6)
340PMB_ADDR_DDR_C1_D: .long mk_pmb_addr_val(0x88)
341PMB_ADDR_DDR_C2_D: .long mk_pmb_addr_val(0x90)
342PMB_ADDR_DDR_C3_D: .long mk_pmb_addr_val(0x98)
343PMB_ADDR_DDR_N1_D: .long mk_pmb_addr_val(0xa8)
344PMB_ADDR_DDR_N2_D: .long mk_pmb_addr_val(0xb0)
345PMB_ADDR_DDR_N3_D: .long mk_pmb_addr_val(0xb8)
346
347PMB_DATA_FLASH_A: .long PMB_DATA_BASE(0)
348PMB_DATA_CPLD_A: .long PMB_DATA_BASE(1)
349PMB_DATA_USB_A: .long PMB_DATA_BASE(2)
350PMB_DATA_DDR_C1_A: .long PMB_DATA_BASE(9)
351PMB_DATA_DDR_C2_A: .long PMB_DATA_BASE(10)
352PMB_DATA_DDR_C3_A: .long PMB_DATA_BASE(11)
353PMB_DATA_DDR_N1_A: .long PMB_DATA_BASE(13)
354PMB_DATA_DDR_N2_A: .long PMB_DATA_BASE(14)
355PMB_DATA_DDR_N3_A: .long PMB_DATA_BASE(15)
356
357/* ppn ub v s1 s0 c wt */
358PMB_DATA_FLASH_D: .long mk_pmb_data_val(0x00, 1, 1, 0, 1, 0, 1)
359PMB_DATA_CPLD_D: .long mk_pmb_data_val(0x04, 1, 1, 0, 0, 0, 1)
360PMB_DATA_USB_D: .long mk_pmb_data_val(0x08, 1, 1, 0, 0, 0, 1)
361PMB_DATA_DDR_C1_D: .long mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1)
362PMB_DATA_DDR_C2_D: .long mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1)
363PMB_DATA_DDR_C3_D: .long mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1)
364PMB_DATA_DDR_N1_D: .long mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1)
365PMB_DATA_DDR_N2_D: .long mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1)
366PMB_DATA_DDR_N3_D: .long mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1)
367
368DUMMY_ADDR: .long 0xa0000000
369PASCR_29BIT_D: .long 0x00000000
370PASCR_INIT: .long 0x80000080 /* check booting mode */
371MMUCR_A: .long 0xff000010
372MMUCR_D: .long 0x00000004 /* clear ITLB */
373#endif /* CONFIG_SH_32BIT */
374
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +0900[diff] [blame]375CCR_A: .long 0xff00001c
376CCR_D: .long 0x0000090b