blob: a5244fff4d9506b339b20bb5ec0bed933527f6e6 [file] [log] [blame]
Stefan Roese10e8bf82014-11-07 12:37:49 +01001/*
2 * Copyright (C) 2012
3 * Altera Corporation <www.altera.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#include <common.h>
9#include <dm.h>
10#include <fdtdec.h>
11#include <malloc.h>
12#include <spi.h>
13#include <asm/errno.h>
14#include "cadence_qspi.h"
15
16#define CQSPI_STIG_READ 0
17#define CQSPI_STIG_WRITE 1
18#define CQSPI_INDIRECT_READ 2
19#define CQSPI_INDIRECT_WRITE 3
20
21DECLARE_GLOBAL_DATA_PTR;
22
23static int cadence_spi_write_speed(struct udevice *bus, uint hz)
24{
25 struct cadence_spi_platdata *plat = bus->platdata;
26 struct cadence_spi_priv *priv = dev_get_priv(bus);
27
28 cadence_qspi_apb_config_baudrate_div(priv->regbase,
29 CONFIG_CQSPI_REF_CLK, hz);
30
31 /* Reconfigure delay timing if speed is changed. */
32 cadence_qspi_apb_delay(priv->regbase, CONFIG_CQSPI_REF_CLK, hz,
33 plat->tshsl_ns, plat->tsd2d_ns,
34 plat->tchsh_ns, plat->tslch_ns);
35
36 return 0;
37}
38
39/* Calibration sequence to determine the read data capture delay register */
Chin Liang See98fbd712015-10-17 08:31:55 -050040static int spi_calibration(struct udevice *bus, uint hz)
Stefan Roese10e8bf82014-11-07 12:37:49 +010041{
Stefan Roese10e8bf82014-11-07 12:37:49 +010042 struct cadence_spi_priv *priv = dev_get_priv(bus);
43 void *base = priv->regbase;
44 u8 opcode_rdid = 0x9F;
45 unsigned int idcode = 0, temp = 0;
46 int err = 0, i, range_lo = -1, range_hi = -1;
47
48 /* start with slowest clock (1 MHz) */
49 cadence_spi_write_speed(bus, 1000000);
50
51 /* configure the read data capture delay register to 0 */
52 cadence_qspi_apb_readdata_capture(base, 1, 0);
53
54 /* Enable QSPI */
55 cadence_qspi_apb_controller_enable(base);
56
57 /* read the ID which will be our golden value */
58 err = cadence_qspi_apb_command_read(base, 1, &opcode_rdid,
59 3, (u8 *)&idcode);
60 if (err) {
61 puts("SF: Calibration failed (read)\n");
62 return err;
63 }
64
65 /* use back the intended clock and find low range */
Chin Liang See98fbd712015-10-17 08:31:55 -050066 cadence_spi_write_speed(bus, hz);
Stefan Roese10e8bf82014-11-07 12:37:49 +010067 for (i = 0; i < CQSPI_READ_CAPTURE_MAX_DELAY; i++) {
68 /* Disable QSPI */
69 cadence_qspi_apb_controller_disable(base);
70
71 /* reconfigure the read data capture delay register */
72 cadence_qspi_apb_readdata_capture(base, 1, i);
73
74 /* Enable back QSPI */
75 cadence_qspi_apb_controller_enable(base);
76
77 /* issue a RDID to get the ID value */
78 err = cadence_qspi_apb_command_read(base, 1, &opcode_rdid,
79 3, (u8 *)&temp);
80 if (err) {
81 puts("SF: Calibration failed (read)\n");
82 return err;
83 }
84
85 /* search for range lo */
86 if (range_lo == -1 && temp == idcode) {
87 range_lo = i;
88 continue;
89 }
90
91 /* search for range hi */
92 if (range_lo != -1 && temp != idcode) {
93 range_hi = i - 1;
94 break;
95 }
96 range_hi = i;
97 }
98
99 if (range_lo == -1) {
100 puts("SF: Calibration failed (low range)\n");
101 return err;
102 }
103
104 /* Disable QSPI for subsequent initialization */
105 cadence_qspi_apb_controller_disable(base);
106
107 /* configure the final value for read data capture delay register */
108 cadence_qspi_apb_readdata_capture(base, 1, (range_hi + range_lo) / 2);
109 debug("SF: Read data capture delay calibrated to %i (%i - %i)\n",
110 (range_hi + range_lo) / 2, range_lo, range_hi);
111
112 /* just to ensure we do once only when speed or chip select change */
Chin Liang See98fbd712015-10-17 08:31:55 -0500113 priv->qspi_calibrated_hz = hz;
Stefan Roese10e8bf82014-11-07 12:37:49 +0100114 priv->qspi_calibrated_cs = spi_chip_select(bus);
115
116 return 0;
117}
118
119static int cadence_spi_set_speed(struct udevice *bus, uint hz)
120{
121 struct cadence_spi_platdata *plat = bus->platdata;
122 struct cadence_spi_priv *priv = dev_get_priv(bus);
123 int err;
124
Chin Liang See4e609b62015-10-17 08:32:38 -0500125 if (hz > plat->max_hz)
126 hz = plat->max_hz;
127
Stefan Roese10e8bf82014-11-07 12:37:49 +0100128 /* Disable QSPI */
129 cadence_qspi_apb_controller_disable(priv->regbase);
130
Chin Liang See98fbd712015-10-17 08:31:55 -0500131 /*
132 * Calibration required for different current SCLK speed, requested
133 * SCLK speed or chip select
134 */
135 if (priv->previous_hz != hz ||
136 priv->qspi_calibrated_hz != hz ||
Stefan Roese10e8bf82014-11-07 12:37:49 +0100137 priv->qspi_calibrated_cs != spi_chip_select(bus)) {
Chin Liang See98fbd712015-10-17 08:31:55 -0500138 err = spi_calibration(bus, hz);
Stefan Roese10e8bf82014-11-07 12:37:49 +0100139 if (err)
140 return err;
Chin Liang See98fbd712015-10-17 08:31:55 -0500141
142 /* prevent calibration run when same as previous request */
143 priv->previous_hz = hz;
Stefan Roese10e8bf82014-11-07 12:37:49 +0100144 }
145
146 /* Enable QSPI */
147 cadence_qspi_apb_controller_enable(priv->regbase);
148
149 debug("%s: speed=%d\n", __func__, hz);
150
151 return 0;
152}
153
154static int cadence_spi_probe(struct udevice *bus)
155{
156 struct cadence_spi_platdata *plat = bus->platdata;
157 struct cadence_spi_priv *priv = dev_get_priv(bus);
158
159 priv->regbase = plat->regbase;
160 priv->ahbbase = plat->ahbbase;
161
162 if (!priv->qspi_is_init) {
163 cadence_qspi_apb_controller_init(plat);
164 priv->qspi_is_init = 1;
165 }
166
167 return 0;
168}
169
170static int cadence_spi_set_mode(struct udevice *bus, uint mode)
171{
172 struct cadence_spi_priv *priv = dev_get_priv(bus);
173 unsigned int clk_pol = (mode & SPI_CPOL) ? 1 : 0;
174 unsigned int clk_pha = (mode & SPI_CPHA) ? 1 : 0;
175
176 /* Disable QSPI */
177 cadence_qspi_apb_controller_disable(priv->regbase);
178
179 /* Set SPI mode */
180 cadence_qspi_apb_set_clk_mode(priv->regbase, clk_pol, clk_pha);
181
182 /* Enable QSPI */
183 cadence_qspi_apb_controller_enable(priv->regbase);
184
185 return 0;
186}
187
188static int cadence_spi_xfer(struct udevice *dev, unsigned int bitlen,
189 const void *dout, void *din, unsigned long flags)
190{
191 struct udevice *bus = dev->parent;
192 struct cadence_spi_platdata *plat = bus->platdata;
193 struct cadence_spi_priv *priv = dev_get_priv(bus);
Vignesh R2372e142016-07-06 10:20:56 +0530194 struct dm_spi_slave_platdata *dm_plat = dev_get_parent_platdata(dev);
Stefan Roese10e8bf82014-11-07 12:37:49 +0100195 void *base = priv->regbase;
196 u8 *cmd_buf = priv->cmd_buf;
197 size_t data_bytes;
198 int err = 0;
199 u32 mode = CQSPI_STIG_WRITE;
200
201 if (flags & SPI_XFER_BEGIN) {
202 /* copy command to local buffer */
203 priv->cmd_len = bitlen / 8;
204 memcpy(cmd_buf, dout, priv->cmd_len);
205 }
206
207 if (flags == (SPI_XFER_BEGIN | SPI_XFER_END)) {
208 /* if start and end bit are set, the data bytes is 0. */
209 data_bytes = 0;
210 } else {
211 data_bytes = bitlen / 8;
212 }
213 debug("%s: len=%d [bytes]\n", __func__, data_bytes);
214
215 /* Set Chip select */
216 cadence_qspi_apb_chipselect(base, spi_chip_select(dev),
217 CONFIG_CQSPI_DECODER);
218
219 if ((flags & SPI_XFER_END) || (flags == 0)) {
220 if (priv->cmd_len == 0) {
221 printf("QSPI: Error, command is empty.\n");
222 return -1;
223 }
224
225 if (din && data_bytes) {
226 /* read */
227 /* Use STIG if no address. */
228 if (!CQSPI_IS_ADDR(priv->cmd_len))
229 mode = CQSPI_STIG_READ;
230 else
231 mode = CQSPI_INDIRECT_READ;
232 } else if (dout && !(flags & SPI_XFER_BEGIN)) {
233 /* write */
234 if (!CQSPI_IS_ADDR(priv->cmd_len))
235 mode = CQSPI_STIG_WRITE;
236 else
237 mode = CQSPI_INDIRECT_WRITE;
238 }
239
240 switch (mode) {
241 case CQSPI_STIG_READ:
242 err = cadence_qspi_apb_command_read(
243 base, priv->cmd_len, cmd_buf,
244 data_bytes, din);
245
246 break;
247 case CQSPI_STIG_WRITE:
248 err = cadence_qspi_apb_command_write(base,
249 priv->cmd_len, cmd_buf,
250 data_bytes, dout);
251 break;
252 case CQSPI_INDIRECT_READ:
253 err = cadence_qspi_apb_indirect_read_setup(plat,
Vignesh R2372e142016-07-06 10:20:56 +0530254 priv->cmd_len, dm_plat->mode_rx, cmd_buf);
Stefan Roese10e8bf82014-11-07 12:37:49 +0100255 if (!err) {
256 err = cadence_qspi_apb_indirect_read_execute
257 (plat, data_bytes, din);
258 }
259 break;
260 case CQSPI_INDIRECT_WRITE:
261 err = cadence_qspi_apb_indirect_write_setup
262 (plat, priv->cmd_len, cmd_buf);
263 if (!err) {
264 err = cadence_qspi_apb_indirect_write_execute
265 (plat, data_bytes, dout);
266 }
267 break;
268 default:
269 err = -1;
270 break;
271 }
272
273 if (flags & SPI_XFER_END) {
274 /* clear command buffer */
275 memset(cmd_buf, 0, sizeof(priv->cmd_buf));
276 priv->cmd_len = 0;
277 }
278 }
279
280 return err;
281}
282
283static int cadence_spi_ofdata_to_platdata(struct udevice *bus)
284{
285 struct cadence_spi_platdata *plat = bus->platdata;
286 const void *blob = gd->fdt_blob;
287 int node = bus->of_offset;
288 int subnode;
289 u32 data[4];
290 int ret;
291
292 /* 2 base addresses are needed, lets get them from the DT */
293 ret = fdtdec_get_int_array(blob, node, "reg", data, ARRAY_SIZE(data));
294 if (ret) {
295 printf("Error: Can't get base addresses (ret=%d)!\n", ret);
296 return -ENODEV;
297 }
298
299 plat->regbase = (void *)data[0];
300 plat->ahbbase = (void *)data[2];
301
Stefan Roese10e8bf82014-11-07 12:37:49 +0100302 /* All other paramters are embedded in the child node */
303 subnode = fdt_first_subnode(blob, node);
Axel Lin1dc7d002015-01-07 09:54:56 +0800304 if (subnode < 0) {
Stefan Roese10e8bf82014-11-07 12:37:49 +0100305 printf("Error: subnode with SPI flash config missing!\n");
306 return -ENODEV;
307 }
308
Chin Liang See040f4ba2015-10-17 08:32:14 -0500309 /* Use 500 KHz as a suitable default */
310 plat->max_hz = fdtdec_get_uint(blob, subnode, "spi-max-frequency",
311 500000);
312
Stefan Roese10e8bf82014-11-07 12:37:49 +0100313 /* Read other parameters from DT */
314 plat->page_size = fdtdec_get_int(blob, subnode, "page-size", 256);
315 plat->block_size = fdtdec_get_int(blob, subnode, "block-size", 16);
316 plat->tshsl_ns = fdtdec_get_int(blob, subnode, "tshsl-ns", 200);
317 plat->tsd2d_ns = fdtdec_get_int(blob, subnode, "tsd2d-ns", 255);
318 plat->tchsh_ns = fdtdec_get_int(blob, subnode, "tchsh-ns", 20);
319 plat->tslch_ns = fdtdec_get_int(blob, subnode, "tslch-ns", 20);
Vikas Manocha90a2f712015-07-02 18:29:44 -0700320 plat->sram_size = fdtdec_get_int(blob, node, "sram-size", 128);
Stefan Roese10e8bf82014-11-07 12:37:49 +0100321
322 debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n",
323 __func__, plat->regbase, plat->ahbbase, plat->max_hz,
324 plat->page_size);
325
326 return 0;
327}
328
329static const struct dm_spi_ops cadence_spi_ops = {
330 .xfer = cadence_spi_xfer,
331 .set_speed = cadence_spi_set_speed,
332 .set_mode = cadence_spi_set_mode,
333 /*
334 * cs_info is not needed, since we require all chip selects to be
335 * in the device tree explicitly
336 */
337};
338
339static const struct udevice_id cadence_spi_ids[] = {
340 { .compatible = "cadence,qspi" },
341 { }
342};
343
344U_BOOT_DRIVER(cadence_spi) = {
345 .name = "cadence_spi",
346 .id = UCLASS_SPI,
347 .of_match = cadence_spi_ids,
348 .ops = &cadence_spi_ops,
349 .ofdata_to_platdata = cadence_spi_ofdata_to_platdata,
350 .platdata_auto_alloc_size = sizeof(struct cadence_spi_platdata),
351 .priv_auto_alloc_size = sizeof(struct cadence_spi_priv),
Stefan Roese10e8bf82014-11-07 12:37:49 +0100352 .probe = cadence_spi_probe,
353};