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Timur Tabic59e1b42010-06-14 15:28:24 -05001/*
Kumar Gala7c57f3e2011-01-11 00:52:35 -06002 * Copyright 2010-2011 Freescale Semiconductor, Inc.
Timur Tabic59e1b42010-06-14 15:28:24 -05003 * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
4 * Timur Tabi <timur@freescale.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the Free
8 * Software Foundation; either version 2 of the License, or (at your option)
9 * any later version.
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15#include "../board/freescale/common/ics307_clk.h"
16
Jiang Yutang9899ac12011-01-24 18:21:15 +080017#ifdef CONFIG_36BIT
18#define CONFIG_PHYS_64BIT
19#endif
20
Timur Tabic59e1b42010-06-14 15:28:24 -050021/* High Level Configuration Options */
22#define CONFIG_BOOKE /* BOOKE */
23#define CONFIG_E500 /* BOOKE e500 family */
24#define CONFIG_MPC85xx /* MPC8540/60/55/41/48 */
25#define CONFIG_P1022
26#define CONFIG_P1022DS
27#define CONFIG_MP /* support multiple processors */
28
Wolfgang Denk2ae18242010-10-06 09:05:45 +020029#ifndef CONFIG_SYS_TEXT_BASE
30#define CONFIG_SYS_TEXT_BASE 0xeff80000
31#endif
32
Kumar Gala7a577fd2011-01-12 02:48:53 -060033#ifndef CONFIG_RESET_VECTOR_ADDRESS
34#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
35#endif
36
Timur Tabic59e1b42010-06-14 15:28:24 -050037#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
38#define CONFIG_PCI /* Enable PCI/PCIE */
39#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
40#define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */
41#define CONFIG_PCIE3 /* PCIE controler 3 (ULI bridge) */
42#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
43#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
44#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
45
Timur Tabic59e1b42010-06-14 15:28:24 -050046#define CONFIG_ENABLE_36BIT_PHYS
Timur Tabibabb3482011-09-06 09:36:06 -050047
48#ifdef CONFIG_PHYS_64BIT
Timur Tabic59e1b42010-06-14 15:28:24 -050049#define CONFIG_ADDR_MAP
50#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
Jiang Yutang9899ac12011-01-24 18:21:15 +080051#endif
Timur Tabic59e1b42010-06-14 15:28:24 -050052
53#define CONFIG_FSL_LAW /* Use common FSL init code */
54
55#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
56#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
57#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
58
59/*
60 * These can be toggled for performance analysis, otherwise use default.
61 */
62#define CONFIG_L2_CACHE
63#define CONFIG_BTB
64
65#define CONFIG_SYS_MEMTEST_START 0x00000000
66#define CONFIG_SYS_MEMTEST_END 0x7fffffff
67
Timur Tabie46fedf2011-08-04 18:03:41 -050068#define CONFIG_SYS_CCSRBAR 0xffe00000
69#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
Timur Tabic59e1b42010-06-14 15:28:24 -050070
Timur Tabic59e1b42010-06-14 15:28:24 -050071/* DDR Setup */
72#define CONFIG_DDR_SPD
73#define CONFIG_VERY_BIG_RAM
74#define CONFIG_FSL_DDR3
75
76#ifdef CONFIG_DDR_ECC
77#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
78#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
79#endif
80
81#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
82#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
83
84#define CONFIG_NUM_DDR_CONTROLLERS 1
85#define CONFIG_DIMM_SLOTS_PER_CTLR 1
86#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
87
88/* I2C addresses of SPD EEPROMs */
89#define CONFIG_SYS_SPD_BUS_NUM 1
Kumar Galac39f44d2011-01-31 22:18:47 -060090#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
Timur Tabic59e1b42010-06-14 15:28:24 -050091
92/*
93 * Memory map
94 *
95 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
96 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable
97 * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable
98 *
99 * Localbus cacheable (TBD)
100 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
101 *
102 * Localbus non-cacheable
103 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
104 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
105 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
106 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
107 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
108 */
109
110/*
111 * Local Bus Definitions
112 */
113#define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
Jiang Yutang9899ac12011-01-24 18:21:15 +0800114#ifdef CONFIG_PHYS_64BIT
Timur Tabic59e1b42010-06-14 15:28:24 -0500115#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
Jiang Yutang9899ac12011-01-24 18:21:15 +0800116#else
117#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
118#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500119
120#define CONFIG_FLASH_BR_PRELIM \
121 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V)
122#define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7)
123
124#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
125#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
126
127#define CONFIG_SYS_BR1_PRELIM \
128 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
129#define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM
130
131#define CONFIG_SYS_FLASH_BANKS_LIST \
132 {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
133#define CONFIG_SYS_FLASH_QUIET_TEST
134#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
135
136#define CONFIG_SYS_MAX_FLASH_BANKS 2
137#define CONFIG_SYS_MAX_FLASH_SECT 1024
138
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200139#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Timur Tabic59e1b42010-06-14 15:28:24 -0500140
141#define CONFIG_FLASH_CFI_DRIVER
142#define CONFIG_SYS_FLASH_CFI
143#define CONFIG_SYS_FLASH_EMPTY_INFO
144
145#define CONFIG_BOARD_EARLY_INIT_F
146#define CONFIG_BOARD_EARLY_INIT_R
147#define CONFIG_MISC_INIT_R
Timur Tabia2d12f82010-07-21 16:56:19 -0500148#define CONFIG_HWCONFIG
Timur Tabic59e1b42010-06-14 15:28:24 -0500149
150#define CONFIG_FSL_NGPIXIS
151#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
Jiang Yutang9899ac12011-01-24 18:21:15 +0800152#ifdef CONFIG_PHYS_64BIT
Timur Tabic59e1b42010-06-14 15:28:24 -0500153#define PIXIS_BASE_PHYS 0xfffdf0000ull
Jiang Yutang9899ac12011-01-24 18:21:15 +0800154#else
155#define PIXIS_BASE_PHYS PIXIS_BASE
156#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500157
158#define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
159#define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | 0x6ff7)
160
161#define PIXIS_LBMAP_SWITCH 7
York Sun29068452011-01-26 10:30:00 -0800162#define PIXIS_LBMAP_MASK 0xF0
Timur Tabic59e1b42010-06-14 15:28:24 -0500163#define PIXIS_LBMAP_ALTBANK 0x20
Jiang Yutang9b6e9d12011-02-24 16:11:56 +0800164#define PIXIS_ELBC_SPI_MASK 0xc0
165#define PIXIS_SPI 0x80
Timur Tabic59e1b42010-06-14 15:28:24 -0500166
167#define CONFIG_SYS_INIT_RAM_LOCK
168#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200169#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
Timur Tabic59e1b42010-06-14 15:28:24 -0500170
Timur Tabic59e1b42010-06-14 15:28:24 -0500171#define CONFIG_SYS_GBL_DATA_OFFSET \
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200172 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Timur Tabic59e1b42010-06-14 15:28:24 -0500173#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
174
175#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
176#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024)
177
178/*
179 * Serial Port
180 */
181#define CONFIG_CONS_INDEX 1
182#define CONFIG_SYS_NS16550
183#define CONFIG_SYS_NS16550_SERIAL
184#define CONFIG_SYS_NS16550_REG_SIZE 1
185#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
186
187#define CONFIG_SYS_BAUDRATE_TABLE \
188 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
189
190#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
191#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
192
193/* Use the HUSH parser */
194#define CONFIG_SYS_HUSH_PARSER
195#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
196
Timur Tabic59e1b42010-06-14 15:28:24 -0500197/* Video */
Timur Tabiba8e76b2011-04-11 14:18:22 -0500198#define CONFIG_FSL_DIU_FB
199
Timur Tabid5e01e42010-09-24 01:25:53 +0200200#ifdef CONFIG_FSL_DIU_FB
201#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000)
202#define CONFIG_VIDEO
203#define CONFIG_CMD_BMP
Timur Tabic59e1b42010-06-14 15:28:24 -0500204#define CONFIG_CFB_CONSOLE
Timur Tabi7d3053f2011-02-15 17:09:19 -0600205#define CONFIG_VIDEO_SW_CURSOR
Timur Tabic59e1b42010-06-14 15:28:24 -0500206#define CONFIG_VGA_AS_SINGLE_DEVICE
Timur Tabid5e01e42010-09-24 01:25:53 +0200207#define CONFIG_VIDEO_LOGO
208#define CONFIG_VIDEO_BMP_LOGO
Timur Tabi55b05232010-09-16 16:35:44 -0500209#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
210/*
211 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
212 * disable empty flash sector detection, which is I/O-intensive.
213 */
214#undef CONFIG_SYS_FLASH_EMPTY_INFO
Timur Tabic59e1b42010-06-14 15:28:24 -0500215#endif
216
Timur Tabiba8e76b2011-04-11 14:18:22 -0500217#ifndef CONFIG_FSL_DIU_FB
Jiang Yutang218a7582011-01-24 18:21:19 +0800218#define CONFIG_ATI
219#endif
220
221#ifdef CONFIG_ATI
222#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
223#define CONFIG_VIDEO
224#define CONFIG_BIOSEMU
225#define CONFIG_VIDEO_SW_CURSOR
226#define CONFIG_ATI_RADEON_FB
227#define CONFIG_VIDEO_LOGO
228#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
229#define CONFIG_CFB_CONSOLE
230#define CONFIG_VGA_AS_SINGLE_DEVICE
231#endif
232
Timur Tabic59e1b42010-06-14 15:28:24 -0500233/*
234 * Pass open firmware flat tree
235 */
236#define CONFIG_OF_LIBFDT
237#define CONFIG_OF_BOARD_SETUP
238#define CONFIG_OF_STDOUT_VIA_ALIAS
239
240/* new uImage format support */
241#define CONFIG_FIT
242#define CONFIG_FIT_VERBOSE
243
244/* I2C */
245#define CONFIG_FSL_I2C
246#define CONFIG_HARD_I2C
247#define CONFIG_I2C_MULTI_BUS
248#define CONFIG_SYS_I2C_SPEED 400000
249#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
250#define CONFIG_SYS_I2C_SLAVE 0x7F
251#define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}}
252#define CONFIG_SYS_I2C_OFFSET 0x3000
253#define CONFIG_SYS_I2C2_OFFSET 0x3100
254
255/*
256 * I2C2 EEPROM
257 */
258#define CONFIG_ID_EEPROM
259#define CONFIG_SYS_I2C_EEPROM_NXID
260#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
261#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
262#define CONFIG_SYS_EEPROM_BUS_NUM 1
263
264/*
Jiang Yutang9b6e9d12011-02-24 16:11:56 +0800265 * eSPI - Enhanced SPI
266 */
267#define CONFIG_SPI_FLASH
268#define CONFIG_SPI_FLASH_SPANSION
269
270#define CONFIG_HARD_SPI
271#define CONFIG_FSL_ESPI
272
273#define CONFIG_CMD_SF
274#define CONFIG_SF_DEFAULT_SPEED 10000000
275#define CONFIG_SF_DEFAULT_MODE 0
276
277/*
Timur Tabic59e1b42010-06-14 15:28:24 -0500278 * General PCI
279 * Memory space is mapped 1-1, but I/O space must start from 0.
280 */
281
282/* controller 1, Slot 2, tgtid 1, Base address a000 */
283#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
Jiang Yutang9899ac12011-01-24 18:21:15 +0800284#ifdef CONFIG_PHYS_64BIT
Timur Tabic59e1b42010-06-14 15:28:24 -0500285#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
286#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
Jiang Yutang9899ac12011-01-24 18:21:15 +0800287#else
288#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
289#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
290#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500291#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
292#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
293#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
Jiang Yutang9899ac12011-01-24 18:21:15 +0800294#ifdef CONFIG_PHYS_64BIT
Timur Tabic59e1b42010-06-14 15:28:24 -0500295#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
Jiang Yutang9899ac12011-01-24 18:21:15 +0800296#else
297#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
298#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500299#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
300
301/* controller 2, direct to uli, tgtid 2, Base address 9000 */
302#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
Jiang Yutang9899ac12011-01-24 18:21:15 +0800303#ifdef CONFIG_PHYS_64BIT
Timur Tabic59e1b42010-06-14 15:28:24 -0500304#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
305#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
Jiang Yutang9899ac12011-01-24 18:21:15 +0800306#else
307#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
308#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
309#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500310#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
311#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
312#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
Jiang Yutang9899ac12011-01-24 18:21:15 +0800313#ifdef CONFIG_PHYS_64BIT
Timur Tabic59e1b42010-06-14 15:28:24 -0500314#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
Jiang Yutang9899ac12011-01-24 18:21:15 +0800315#else
316#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
317#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500318#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
319
320/* controller 3, Slot 1, tgtid 3, Base address b000 */
321#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
Jiang Yutang9899ac12011-01-24 18:21:15 +0800322#ifdef CONFIG_PHYS_64BIT
Timur Tabic59e1b42010-06-14 15:28:24 -0500323#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
324#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
Jiang Yutang9899ac12011-01-24 18:21:15 +0800325#else
326#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
327#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
328#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500329#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
330#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
331#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
Jiang Yutang9899ac12011-01-24 18:21:15 +0800332#ifdef CONFIG_PHYS_64BIT
Timur Tabic59e1b42010-06-14 15:28:24 -0500333#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
Jiang Yutang9899ac12011-01-24 18:21:15 +0800334#else
335#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
336#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500337#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
338
339#ifdef CONFIG_PCI
Timur Tabic59e1b42010-06-14 15:28:24 -0500340#define CONFIG_PCI_PNP /* do pci plug-and-play */
341#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Kumar Gala16855ec2010-11-09 23:19:50 -0600342#define CONFIG_E1000 /* Define e1000 pci Ethernet card */
Timur Tabic59e1b42010-06-14 15:28:24 -0500343#endif
344
345/* SATA */
346#define CONFIG_LIBATA
347#define CONFIG_FSL_SATA
Jiang Yutang2d7534a2011-01-30 17:06:20 -0600348#define CONFIG_FSL_SATA_V2
Timur Tabic59e1b42010-06-14 15:28:24 -0500349
350#define CONFIG_SYS_SATA_MAX_DEVICE 2
351#define CONFIG_SATA1
352#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
353#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
354#define CONFIG_SATA2
355#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
356#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
357
358#ifdef CONFIG_FSL_SATA
359#define CONFIG_LBA48
360#define CONFIG_CMD_SATA
361#define CONFIG_DOS_PARTITION
362#define CONFIG_CMD_EXT2
363#endif
364
365#define CONFIG_MMC
366#ifdef CONFIG_MMC
367#define CONFIG_CMD_MMC
368#define CONFIG_FSL_ESDHC
369#define CONFIG_GENERIC_MMC
370#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
371#endif
372
373#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
374#define CONFIG_CMD_EXT2
375#define CONFIG_CMD_FAT
376#define CONFIG_DOS_PARTITION
377#endif
378
379#define CONFIG_TSEC_ENET
380#ifdef CONFIG_TSEC_ENET
381
382#define CONFIG_TSECV2
Timur Tabic59e1b42010-06-14 15:28:24 -0500383
384#define CONFIG_MII /* MII PHY management */
385#define CONFIG_TSEC1 1
386#define CONFIG_TSEC1_NAME "eTSEC1"
387#define CONFIG_TSEC2 1
388#define CONFIG_TSEC2_NAME "eTSEC2"
389
390#define TSEC1_PHY_ADDR 1
391#define TSEC2_PHY_ADDR 2
392
393#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
394#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
395
396#define TSEC1_PHYIDX 0
397#define TSEC2_PHYIDX 0
398
399#define CONFIG_ETHPRIME "eTSEC1"
400
401#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
402#endif
403
404/*
405 * Environment
406 */
407#define CONFIG_ENV_IS_IN_FLASH
408#define CONFIG_ENV_OVERWRITE
409#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
410#define CONFIG_ENV_SIZE 0x2000
411#define CONFIG_ENV_SECT_SIZE 0x20000
412
413#define CONFIG_LOADS_ECHO
414#define CONFIG_SYS_LOADS_BAUD_CHANGE
415
416/*
417 * Command line configuration.
418 */
419#include <config_cmd_default.h>
420
Kumar Gala79ee3442010-06-09 22:59:41 -0500421#define CONFIG_CMD_ELF
422#define CONFIG_CMD_ERRATA
Timur Tabic59e1b42010-06-14 15:28:24 -0500423#define CONFIG_CMD_IRQ
Timur Tabic59e1b42010-06-14 15:28:24 -0500424#define CONFIG_CMD_I2C
425#define CONFIG_CMD_MII
Kumar Gala79ee3442010-06-09 22:59:41 -0500426#define CONFIG_CMD_PING
Timur Tabic59e1b42010-06-14 15:28:24 -0500427#define CONFIG_CMD_SETEXPR
Matthew McClintockb8339e22010-12-17 17:26:41 -0600428#define CONFIG_CMD_REGINFO
Timur Tabic59e1b42010-06-14 15:28:24 -0500429
430#ifdef CONFIG_PCI
431#define CONFIG_CMD_PCI
432#define CONFIG_CMD_NET
433#endif
434
435/*
436 * USB
437 */
438#define CONFIG_USB_EHCI
439
440#ifdef CONFIG_USB_EHCI
441#define CONFIG_CMD_USB
442#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
443#define CONFIG_USB_EHCI_FSL
444#define CONFIG_USB_STORAGE
445#define CONFIG_CMD_FAT
446#endif
447
448/*
449 * Miscellaneous configurable options
450 */
451#define CONFIG_SYS_LONGHELP /* undef to save memory */
452#define CONFIG_CMDLINE_EDITING /* Command-line editing */
Kim Phillips5be58f52010-07-14 19:47:18 -0500453#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Timur Tabic59e1b42010-06-14 15:28:24 -0500454#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
455#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
456#ifdef CONFIG_CMD_KGDB
457#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
458#else
459#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
460#endif
461/* Print Buffer Size */
462#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
463#define CONFIG_SYS_MAXARGS 16
464#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
465#define CONFIG_SYS_HZ 1000
466
467/*
468 * For booting Linux, the board info and command line data
Kumar Galaa832ac42011-04-28 10:13:41 -0500469 * have to be in the first 64 MB of memory, since this is
Timur Tabic59e1b42010-06-14 15:28:24 -0500470 * the maximum mapped by the Linux kernel during initialization.
471 */
Kumar Galaa832ac42011-04-28 10:13:41 -0500472#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
473#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
Timur Tabic59e1b42010-06-14 15:28:24 -0500474
Timur Tabic59e1b42010-06-14 15:28:24 -0500475#ifdef CONFIG_CMD_KGDB
476#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
477#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
478#endif
479
480/*
481 * Environment Configuration
482 */
483
484#define CONFIG_HOSTNAME p1022ds
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000485#define CONFIG_ROOTPATH "/opt/nfsroot"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000486#define CONFIG_BOOTFILE "uImage"
Timur Tabic59e1b42010-06-14 15:28:24 -0500487#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
488
489#define CONFIG_LOADADDR 1000000
490
491#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
492#define CONFIG_BOOTARGS
493
494#define CONFIG_BAUDRATE 115200
495
496#define CONFIG_EXTRA_ENV_SETTINGS \
497 "perf_mode=stable\0" \
498 "memctl_intlv_ctl=2\0" \
499 "netdev=eth0\0" \
500 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
501 "tftpflash=tftpboot $loadaddr $uboot; " \
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200502 "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
503 "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
504 "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
505 "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
506 "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
Timur Tabic59e1b42010-06-14 15:28:24 -0500507 "consoledev=ttyS0\0" \
508 "ramdiskaddr=2000000\0" \
509 "ramdiskfile=uramdisk\0" \
510 "fdtaddr=c00000\0" \
511 "fdtfile=p1022ds.dtb\0" \
512 "bdev=sda3\0" \
513 "diuregs=md e002c000 1d\0" \
514 "dium=mw e002c01c\0" \
515 "diuerr=md e002c014 1\0" \
Timur Tabiba8e76b2011-04-11 14:18:22 -0500516 "hwconfig=esdhc;audclk:12\0"
Timur Tabic59e1b42010-06-14 15:28:24 -0500517
518#define CONFIG_HDBOOT \
519 "setenv bootargs root=/dev/$bdev rw " \
520 "console=$consoledev,$baudrate $othbootargs;" \
521 "tftp $loadaddr $bootfile;" \
522 "tftp $fdtaddr $fdtfile;" \
523 "bootm $loadaddr - $fdtaddr"
524
525#define CONFIG_NFSBOOTCOMMAND \
526 "setenv bootargs root=/dev/nfs rw " \
527 "nfsroot=$serverip:$rootpath " \
528 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
529 "console=$consoledev,$baudrate $othbootargs;" \
530 "tftp $loadaddr $bootfile;" \
531 "tftp $fdtaddr $fdtfile;" \
532 "bootm $loadaddr - $fdtaddr"
533
534#define CONFIG_RAMBOOTCOMMAND \
535 "setenv bootargs root=/dev/ram rw " \
536 "console=$consoledev,$baudrate $othbootargs;" \
537 "tftp $ramdiskaddr $ramdiskfile;" \
538 "tftp $loadaddr $bootfile;" \
539 "tftp $fdtaddr $fdtfile;" \
540 "bootm $loadaddr $ramdiskaddr $fdtaddr"
541
542#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
543
544#endif