blob: 62ee7668ab179bf3525e4fbcd1f08274cda10b15 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Wenyou Yang9319a752017-03-23 12:44:37 +08002/*
3 * Atmel PIO pinctrl driver
4 *
5 * Copyright (C) 2016 Atmel Corporation
6 * Wenyou.Yang <wenyou.yang@atmel.com>
Wenyou Yang9319a752017-03-23 12:44:37 +08007 */
8
9#include <common.h>
Simon Glass9d922452017-05-17 17:18:03 -060010#include <dm.h>
Wenyou Yang9319a752017-03-23 12:44:37 +080011#include <dm/pinctrl.h>
Wenyou Yange61ed482017-09-14 11:07:42 +080012#include <asm/hardware.h>
Wenyou Yang9319a752017-03-23 12:44:37 +080013#include <linux/io.h>
14#include <linux/err.h>
15#include <mach/at91_pio.h>
16
17DECLARE_GLOBAL_DATA_PTR;
18
19#define MAX_GPIO_BANKS 5
20#define MAX_NB_GPIO_PER_BANK 32
21
22#define MAX_PINMUX_ENTRIES 200
23
24struct at91_pinctrl_priv {
25 struct at91_port *reg_base[MAX_GPIO_BANKS];
26 u32 nbanks;
27};
28
29#define PULL_UP BIT(0)
30#define MULTI_DRIVE BIT(1)
31#define DEGLITCH BIT(2)
32#define PULL_DOWN BIT(3)
33#define DIS_SCHMIT BIT(4)
34#define DRIVE_STRENGTH_SHIFT 5
35#define DRIVE_STRENGTH_MASK 0x3
36#define DRIVE_STRENGTH (DRIVE_STRENGTH_MASK << DRIVE_STRENGTH_SHIFT)
37#define OUTPUT BIT(7)
38#define OUTPUT_VAL_SHIFT 8
39#define OUTPUT_VAL (0x1 << OUTPUT_VAL_SHIFT)
40#define DEBOUNCE BIT(16)
41#define DEBOUNCE_VAL_SHIFT 17
42#define DEBOUNCE_VAL (0x3fff << DEBOUNCE_VAL_SHIFT)
43
44/**
45 * These defines will translated the dt binding settings to our internal
46 * settings. They are not necessarily the same value as the register setting.
47 * The actual drive strength current of low, medium and high must be looked up
48 * from the corresponding device datasheet. This value is different for pins
49 * that are even in the same banks. It is also dependent on VCC.
50 * DRIVE_STRENGTH_DEFAULT is just a placeholder to avoid changing the drive
51 * strength when there is no dt config for it.
52 */
Claudiu Beznea04d4ec92019-03-25 10:33:56 +000053enum drive_strength_bit {
54 DRIVE_STRENGTH_BIT_DEF,
55 DRIVE_STRENGTH_BIT_LOW,
56 DRIVE_STRENGTH_BIT_MED,
57 DRIVE_STRENGTH_BIT_HI,
58};
59
60#define DRIVE_STRENGTH_BIT_MSK(name) (DRIVE_STRENGTH_BIT_##name << \
61 DRIVE_STRENGTH_SHIFT)
Wenyou Yang9319a752017-03-23 12:44:37 +080062
63enum at91_mux {
64 AT91_MUX_GPIO = 0,
65 AT91_MUX_PERIPH_A = 1,
66 AT91_MUX_PERIPH_B = 2,
67 AT91_MUX_PERIPH_C = 3,
68 AT91_MUX_PERIPH_D = 4,
69};
70
71/**
72 * struct at91_pinctrl_mux_ops - describes an AT91 mux ops group
73 * on new IP with support for periph C and D the way to mux in
74 * periph A and B has changed
75 * So provide the right callbacks
76 * if not present means the IP does not support it
77 * @mux_A_periph: assign the corresponding pin to the peripheral A function.
78 * @mux_B_periph: assign the corresponding pin to the peripheral B function.
79 * @mux_C_periph: assign the corresponding pin to the peripheral C function.
80 * @mux_D_periph: assign the corresponding pin to the peripheral D function.
81 * @set_deglitch: enable/disable the deglitch feature.
82 * @set_debounce: enable/disable the debounce feature.
83 * @set_pulldown: enable/disable the pulldown feature.
84 * @disable_schmitt_trig: disable schmitt trigger
85 */
86struct at91_pinctrl_mux_ops {
87 void (*mux_A_periph)(struct at91_port *pio, u32 mask);
88 void (*mux_B_periph)(struct at91_port *pio, u32 mask);
89 void (*mux_C_periph)(struct at91_port *pio, u32 mask);
90 void (*mux_D_periph)(struct at91_port *pio, u32 mask);
91 void (*set_deglitch)(struct at91_port *pio, u32 mask, bool is_on);
92 void (*set_debounce)(struct at91_port *pio, u32 mask, bool is_on,
93 u32 div);
94 void (*set_pulldown)(struct at91_port *pio, u32 mask, bool is_on);
95 void (*disable_schmitt_trig)(struct at91_port *pio, u32 mask);
96 void (*set_drivestrength)(struct at91_port *pio, u32 pin,
97 u32 strength);
98};
99
100static u32 two_bit_pin_value_shift_amount(u32 pin)
101{
102 /* return the shift value for a pin for "two bit" per pin registers,
103 * i.e. drive strength */
104 return 2 * ((pin >= MAX_NB_GPIO_PER_BANK/2)
105 ? pin - MAX_NB_GPIO_PER_BANK/2 : pin);
106}
107
108static void at91_mux_disable_interrupt(struct at91_port *pio, u32 mask)
109{
110 writel(mask, &pio->idr);
111}
112
113static void at91_mux_set_pullup(struct at91_port *pio, u32 mask, bool on)
114{
115 if (on)
116 writel(mask, &pio->mux.pio3.ppddr);
117
118 writel(mask, (on ? &pio->puer : &pio->pudr));
119}
120
121static void at91_mux_set_output(struct at91_port *pio, unsigned mask,
122 bool is_on, bool val)
123{
124 writel(mask, (val ? &pio->sodr : &pio->codr));
125 writel(mask, (is_on ? &pio->oer : &pio->odr));
126}
127
128static void at91_mux_set_multidrive(struct at91_port *pio, u32 mask, bool on)
129{
130 writel(mask, (on ? &pio->mder : &pio->mddr));
131}
132
133static void at91_mux_set_A_periph(struct at91_port *pio, u32 mask)
134{
135 writel(mask, &pio->mux.pio2.asr);
136}
137
138static void at91_mux_set_B_periph(struct at91_port *pio, u32 mask)
139{
140 writel(mask, &pio->mux.pio2.bsr);
141}
142
143static void at91_mux_pio3_set_A_periph(struct at91_port *pio, u32 mask)
144{
145 writel(readl(&pio->mux.pio3.abcdsr1) & ~mask, &pio->mux.pio3.abcdsr1);
146 writel(readl(&pio->mux.pio3.abcdsr2) & ~mask, &pio->mux.pio3.abcdsr2);
147}
148
149static void at91_mux_pio3_set_B_periph(struct at91_port *pio, u32 mask)
150{
151 writel(readl(&pio->mux.pio3.abcdsr1) | mask, &pio->mux.pio3.abcdsr1);
152 writel(readl(&pio->mux.pio3.abcdsr2) & ~mask, &pio->mux.pio3.abcdsr2);
153}
154
155static void at91_mux_pio3_set_C_periph(struct at91_port *pio, u32 mask)
156{
157 writel(readl(&pio->mux.pio3.abcdsr1) & ~mask, &pio->mux.pio3.abcdsr1);
158 writel(readl(&pio->mux.pio3.abcdsr2) | mask, &pio->mux.pio3.abcdsr2);
159}
160
161static void at91_mux_pio3_set_D_periph(struct at91_port *pio, u32 mask)
162{
163 writel(readl(&pio->mux.pio3.abcdsr1) | mask, &pio->mux.pio3.abcdsr1);
164 writel(readl(&pio->mux.pio3.abcdsr2) | mask, &pio->mux.pio3.abcdsr2);
165}
166
167static void at91_mux_set_deglitch(struct at91_port *pio, u32 mask, bool is_on)
168{
169 writel(mask, (is_on ? &pio->ifer : &pio->ifdr));
170}
171
172static void at91_mux_pio3_set_deglitch(struct at91_port *pio,
173 u32 mask, bool is_on)
174{
175 if (is_on)
176 writel(mask, &pio->mux.pio3.ifscdr);
177 at91_mux_set_deglitch(pio, mask, is_on);
178}
179
180static void at91_mux_pio3_set_debounce(struct at91_port *pio, u32 mask,
181 bool is_on, u32 div)
182{
183 if (is_on) {
184 writel(mask, &pio->mux.pio3.ifscer);
185 writel(div & PIO_SCDR_DIV, &pio->mux.pio3.scdr);
186 writel(mask, &pio->ifer);
187 } else {
188 writel(mask, &pio->mux.pio3.ifscdr);
189 }
190}
191
192static void at91_mux_pio3_set_pulldown(struct at91_port *pio,
193 u32 mask, bool is_on)
194{
195 if (is_on)
196 writel(mask, &pio->pudr);
197
198 writel(mask, (is_on ? &pio->mux.pio3.ppder : &pio->mux.pio3.ppddr));
199}
200
201static void at91_mux_pio3_disable_schmitt_trig(struct at91_port *pio,
202 u32 mask)
203{
204 writel(readl(&pio->schmitt) | mask, &pio->schmitt);
205}
206
207static void set_drive_strength(void *reg, u32 pin, u32 strength)
208{
209 u32 shift = two_bit_pin_value_shift_amount(pin);
210
211 clrsetbits_le32(reg, DRIVE_STRENGTH_MASK << shift, strength << shift);
212}
213
214static void at91_mux_sama5d3_set_drivestrength(struct at91_port *pio,
215 u32 pin, u32 setting)
216{
217 void *reg;
218
219 reg = &pio->driver12;
220 if (pin >= MAX_NB_GPIO_PER_BANK / 2)
221 reg = &pio->driver2;
222
223 /* do nothing if setting is zero */
224 if (!setting)
225 return;
226
227 /* strength is 1 to 1 with setting for SAMA5 */
228 set_drive_strength(reg, pin, setting);
229}
230
231static void at91_mux_sam9x5_set_drivestrength(struct at91_port *pio,
232 u32 pin, u32 setting)
233{
234 void *reg;
235
236 reg = &pio->driver1;
237 if (pin >= MAX_NB_GPIO_PER_BANK / 2)
238 reg = &pio->driver12;
239
240 /* do nothing if setting is zero */
241 if (!setting)
242 return;
243
244 /* strength is inverse on SAM9x5s with our defines
245 * 0 = hi, 1 = med, 2 = low, 3 = rsvd */
Claudiu Beznea04d4ec92019-03-25 10:33:56 +0000246 setting = DRIVE_STRENGTH_BIT_MSK(HI) - setting;
Wenyou Yang9319a752017-03-23 12:44:37 +0800247
248 set_drive_strength(reg, pin, setting);
249}
250
Claudiu Beznea1a6a8282019-03-25 10:33:57 +0000251static void at91_mux_sam9x60_set_drivestrength(struct at91_port *pio, u32 pin,
252 u32 setting)
253{
254 void *reg = &pio->driver12;
255 u32 tmp;
256
257 if (setting <= DRIVE_STRENGTH_BIT_DEF ||
258 setting == DRIVE_STRENGTH_BIT_MED ||
259 setting > DRIVE_STRENGTH_BIT_HI)
260 return;
261
262 tmp = readl(reg);
263
264 /* Strength is 0: low, 1: hi */
265 if (setting == DRIVE_STRENGTH_BIT_LOW)
266 tmp &= ~BIT(pin);
267 else
268 tmp |= BIT(pin);
269
270 writel(tmp, reg);
271}
272
Wenyou Yang9319a752017-03-23 12:44:37 +0800273static struct at91_pinctrl_mux_ops at91rm9200_ops = {
274 .mux_A_periph = at91_mux_set_A_periph,
275 .mux_B_periph = at91_mux_set_B_periph,
276 .set_deglitch = at91_mux_set_deglitch,
277};
278
279static struct at91_pinctrl_mux_ops at91sam9x5_ops = {
280 .mux_A_periph = at91_mux_pio3_set_A_periph,
281 .mux_B_periph = at91_mux_pio3_set_B_periph,
282 .mux_C_periph = at91_mux_pio3_set_C_periph,
283 .mux_D_periph = at91_mux_pio3_set_D_periph,
284 .set_deglitch = at91_mux_pio3_set_deglitch,
285 .set_debounce = at91_mux_pio3_set_debounce,
286 .set_pulldown = at91_mux_pio3_set_pulldown,
287 .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
288 .set_drivestrength = at91_mux_sam9x5_set_drivestrength,
289};
290
291static struct at91_pinctrl_mux_ops sama5d3_ops = {
292 .mux_A_periph = at91_mux_pio3_set_A_periph,
293 .mux_B_periph = at91_mux_pio3_set_B_periph,
294 .mux_C_periph = at91_mux_pio3_set_C_periph,
295 .mux_D_periph = at91_mux_pio3_set_D_periph,
296 .set_deglitch = at91_mux_pio3_set_deglitch,
297 .set_debounce = at91_mux_pio3_set_debounce,
298 .set_pulldown = at91_mux_pio3_set_pulldown,
299 .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
300 .set_drivestrength = at91_mux_sama5d3_set_drivestrength,
301};
302
Claudiu Beznea1a6a8282019-03-25 10:33:57 +0000303static struct at91_pinctrl_mux_ops sam9x60_ops = {
304 .mux_A_periph = at91_mux_pio3_set_A_periph,
305 .mux_B_periph = at91_mux_pio3_set_B_periph,
306 .mux_C_periph = at91_mux_pio3_set_C_periph,
307 .mux_D_periph = at91_mux_pio3_set_D_periph,
308 .set_deglitch = at91_mux_pio3_set_deglitch,
309 .set_debounce = at91_mux_pio3_set_debounce,
310 .set_pulldown = at91_mux_pio3_set_pulldown,
311 .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
312 .set_drivestrength = at91_mux_sam9x60_set_drivestrength,
313};
314
Wenyou Yang9319a752017-03-23 12:44:37 +0800315static void at91_mux_gpio_disable(struct at91_port *pio, u32 mask)
316{
317 writel(mask, &pio->pdr);
318}
319
320static void at91_mux_gpio_enable(struct at91_port *pio, u32 mask, bool input)
321{
322 writel(mask, &pio->per);
323 writel(mask, (input ? &pio->odr : &pio->oer));
324}
325
326static int at91_pmx_set(struct at91_pinctrl_mux_ops *ops,
327 struct at91_port *pio, u32 mask, enum at91_mux mux)
328{
329 at91_mux_disable_interrupt(pio, mask);
330 switch (mux) {
331 case AT91_MUX_GPIO:
332 at91_mux_gpio_enable(pio, mask, 1);
333 break;
334 case AT91_MUX_PERIPH_A:
335 ops->mux_A_periph(pio, mask);
336 break;
337 case AT91_MUX_PERIPH_B:
338 ops->mux_B_periph(pio, mask);
339 break;
340 case AT91_MUX_PERIPH_C:
341 if (!ops->mux_C_periph)
342 return -EINVAL;
343 ops->mux_C_periph(pio, mask);
344 break;
345 case AT91_MUX_PERIPH_D:
346 if (!ops->mux_D_periph)
347 return -EINVAL;
348 ops->mux_D_periph(pio, mask);
349 break;
350 }
351 if (mux)
352 at91_mux_gpio_disable(pio, mask);
353
354 return 0;
355}
356
357static int at91_pinconf_set(struct at91_pinctrl_mux_ops *ops,
358 struct at91_port *pio, u32 pin, u32 config)
359{
360 u32 mask = BIT(pin);
361
362 if ((config & PULL_UP) && (config & PULL_DOWN))
363 return -EINVAL;
364
365 at91_mux_set_output(pio, mask, config & OUTPUT,
366 (config & OUTPUT_VAL) >> OUTPUT_VAL_SHIFT);
367 at91_mux_set_pullup(pio, mask, config & PULL_UP);
368 at91_mux_set_multidrive(pio, mask, config & MULTI_DRIVE);
369 if (ops->set_deglitch)
370 ops->set_deglitch(pio, mask, config & DEGLITCH);
371 if (ops->set_debounce)
372 ops->set_debounce(pio, mask, config & DEBOUNCE,
373 (config & DEBOUNCE_VAL) >> DEBOUNCE_VAL_SHIFT);
374 if (ops->set_pulldown)
375 ops->set_pulldown(pio, mask, config & PULL_DOWN);
376 if (ops->disable_schmitt_trig && config & DIS_SCHMIT)
377 ops->disable_schmitt_trig(pio, mask);
378 if (ops->set_drivestrength)
379 ops->set_drivestrength(pio, pin,
380 (config & DRIVE_STRENGTH) >> DRIVE_STRENGTH_SHIFT);
381
382 return 0;
383}
384
385static int at91_pin_check_config(struct udevice *dev, u32 bank, u32 pin)
386{
387 struct at91_pinctrl_priv *priv = dev_get_priv(dev);
388
389 if (bank >= priv->nbanks) {
390 debug("pin conf bank %d >= nbanks %d\n", bank, priv->nbanks);
391 return -EINVAL;
392 }
393
394 if (pin >= MAX_NB_GPIO_PER_BANK) {
395 debug("pin conf pin %d >= %d\n", pin, MAX_NB_GPIO_PER_BANK);
396 return -EINVAL;
397 }
398
399 return 0;
400}
401
402static int at91_pinctrl_set_state(struct udevice *dev, struct udevice *config)
403{
404 struct at91_pinctrl_priv *priv = dev_get_priv(dev);
405 const void *blob = gd->fdt_blob;
Simon Glassda409cc2017-05-17 17:18:09 -0600406 int node = dev_of_offset(config);
Wenyou Yang9319a752017-03-23 12:44:37 +0800407 u32 cells[MAX_PINMUX_ENTRIES];
408 const u32 *list = cells;
409 u32 bank, pin;
410 u32 conf, mask, count, i;
411 int size;
412 int ret;
413 enum at91_mux mux;
414 struct at91_port *pio;
415 struct at91_pinctrl_mux_ops *ops =
416 (struct at91_pinctrl_mux_ops *)dev_get_driver_data(dev);
417
418 /*
419 * the binding format is atmel,pins = <bank pin mux CONFIG ...>,
420 * do sanity check and calculate pins number
421 */
422 size = fdtdec_get_int_array_count(blob, node, "atmel,pins",
423 cells, ARRAY_SIZE(cells));
424
425 /* we do not check return since it's safe node passed down */
426 count = size >> 2;
427 if (!count)
428 return -EINVAL;
429
430 for (i = 0; i < count; i++) {
431 bank = *list++;
432 pin = *list++;
433 mux = *list++;
434 conf = *list++;
435
436 ret = at91_pin_check_config(dev, bank, pin);
437 if (ret)
438 return ret;
439
440 pio = priv->reg_base[bank];
441 mask = BIT(pin);
442
443 ret = at91_pmx_set(ops, pio, mask, mux);
444 if (ret)
445 return ret;
446
447 ret = at91_pinconf_set(ops, pio, pin, conf);
448 if (ret)
449 return ret;
450 }
451
452 return 0;
453}
454
455const struct pinctrl_ops at91_pinctrl_ops = {
456 .set_state = at91_pinctrl_set_state,
457};
458
459static int at91_pinctrl_probe(struct udevice *dev)
460{
461 struct at91_pinctrl_priv *priv = dev_get_priv(dev);
462 fdt_addr_t addr_base;
463 int index;
464
465 for (index = 0; index < MAX_GPIO_BANKS; index++) {
Simon Glassa821c4a2017-05-17 17:18:05 -0600466 addr_base = devfdt_get_addr_index(dev, index);
Wenyou Yang9319a752017-03-23 12:44:37 +0800467 if (addr_base == FDT_ADDR_T_NONE)
468 break;
469
470 priv->reg_base[index] = (struct at91_port *)addr_base;
471 }
472
473 priv->nbanks = index;
474
475 return 0;
476}
477
478static const struct udevice_id at91_pinctrl_match[] = {
479 { .compatible = "atmel,sama5d3-pinctrl", .data = (ulong)&sama5d3_ops },
480 { .compatible = "atmel,at91sam9x5-pinctrl", .data = (ulong)&at91sam9x5_ops },
481 { .compatible = "atmel,at91rm9200-pinctrl", .data = (ulong)&at91rm9200_ops },
Claudiu Bezneabe6e2402019-03-25 10:33:59 +0000482 { .compatible = "microchip,sam9x60-pinctrl", .data = (ulong)&sam9x60_ops },
Wenyou Yang9319a752017-03-23 12:44:37 +0800483 {}
484};
485
486U_BOOT_DRIVER(at91_pinctrl) = {
487 .name = "pinctrl_at91",
488 .id = UCLASS_PINCTRL,
489 .of_match = at91_pinctrl_match,
490 .probe = at91_pinctrl_probe,
491 .priv_auto_alloc_size = sizeof(struct at91_pinctrl_priv),
492 .ops = &at91_pinctrl_ops,
493};