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wdenkc6097192002-11-03 00:24:07 +00001/*
2 * (C) Copyright 2000
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 * Keith Outwater, keith_outwater@mvis.com
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <virtex2.h>
26#include <common.h>
27#include <mpc8xx.h>
28#include <asm/8xx_immap.h>
29#include "beeper.h"
30#include "fpga.h"
31#include "ioport.h"
32
Wolfgang Denkd87080b2006-03-31 18:32:53 +020033DECLARE_GLOBAL_DATA_PTR;
34
wdenkc6097192002-11-03 00:24:07 +000035#ifdef CONFIG_STATUS_LED
36#include <status_led.h>
37#endif
38
Jon Loeliger77a31852007-07-10 10:39:10 -050039#if defined(CONFIG_CMD_MII) && defined(CONFIG_MII)
wdenkc6097192002-11-03 00:24:07 +000040#include <net.h>
41#endif
42
43#if 0
44#define GEN860T_DEBUG
45#endif
46
47#ifdef GEN860T_DEBUG
48#define PRINTF(fmt,args...) printf (fmt ,##args)
49#else
50#define PRINTF(fmt,args...)
51#endif
52
53/*
54 * The following UPM init tables were generated automatically by
55 * Motorola's MCUINIT program. See the README file for UPM to
56 * SDRAM pin assignments if you want to type this data into
57 * MCUINIT in order to reverse engineer the waveforms.
58 */
59
60/*
61 * UPM initialization tables for MICRON MT48LC16M16A2TG SDRAM devices
62 * (UPMA) and Virtex FPGA SelectMap interface (UPMB).
63 * NOTE that unused areas of the table are used to hold NOP, precharge
64 * and mode register set sequences.
65 *
66 */
67#define UPMA_NOP_ADDR 0x5
68#define UPMA_PRECHARGE_ADDR 0x6
69#define UPMA_MRS_ADDR 0x12
70
71#define UPM_SINGLE_READ_ADDR 0x00
72#define UPM_BURST_READ_ADDR 0x08
73#define UPM_SINGLE_WRITE_ADDR 0x18
74#define UPM_BURST_WRITE_ADDR 0x20
75#define UPM_REFRESH_ADDR 0x30
76
77const uint sdram_upm_table[] = {
78 /* single read (offset 0x00 in upm ram) */
79 0x0e0fdc04, 0x01adfc04, 0x0fbffc00, 0x1fff5c05,
80 0xffffffff, 0x0fffffcd, 0x0fff0fce, 0xefcfffff,
81 /* burst read (offset 0x08 in upm ram) */
82 0x0f0fdc04, 0x00fdfc04, 0xf0fffc00, 0xf0fffc00,
83 0xf1fffc00, 0xfffffc00, 0xfffffc05, 0xffffffff,
84 0xffffffff, 0xffffffff, 0x0ffffff4, 0x1f3d5ff4,
85 0xfffffff4, 0xfffffff5, 0xffffffff, 0xffffffff,
86 /* single write (offset 0x18 in upm ram) */
87 0x0f0fdc04, 0x00ad3c00, 0x1fff5c05, 0xffffffff,
88 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
89 /* burst write (offset 0x20 in upm ram) */
90 0x0f0fdc00, 0x10fd7c00, 0xf0fffc00, 0xf0fffc00,
91 0xf1fffc04, 0xfffffc05, 0xffffffff, 0xffffffff,
92 0xffffffff, 0xffffffff, 0xffffffff, 0xfffff7ff,
93 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
94 /* refresh (offset 0x30 in upm ram) */
95 0x1ffddc84, 0xfffffc04, 0xfffffc04, 0xfffffc84,
96 0xfffffc05, 0xffffffff, 0xffffffff, 0xffffffff,
97 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
98 /* exception (offset 0x3C in upm ram) */
wdenkbf9e3b32004-02-12 00:47:09 +000099};
wdenkc6097192002-11-03 00:24:07 +0000100
101const uint selectmap_upm_table[] = {
102 /* single read (offset 0x00 in upm ram) */
103 0x88fffc06, 0x00fff404, 0x00fffc04, 0x33fffc00,
104 0xfffffc05, 0xffffffff, 0xffffffff, 0xffffffff,
105 /* burst read (offset 0x08 in upm ram) */
106 0xfffffc04, 0xfffffc05, 0xffffffff, 0xffffffff,
107 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
108 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
109 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
110 /* single write (offset 0x18 in upm ram) */
111 0x88fffc04, 0x00fff400, 0x77fffc05, 0xffffffff,
112 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
113 /* burst write (offset 0x20 in upm ram) */
114 0xfffffc04, 0xfffffc05, 0xffffffff, 0xffffffff,
115 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
116 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
117 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
118 /* refresh (offset 0x30 in upm ram) */
119 0xfffffc04, 0xfffffc05, 0xffffffff, 0xffffffff,
120 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
121 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
122 /* exception (offset 0x3C in upm ram) */
123 0xfffffc05, 0xffffffff, 0xffffffff, 0xffffffff
124};
125
126/*
127 * Check board identity. Always successful (gives information only)
128 */
wdenkbf9e3b32004-02-12 00:47:09 +0000129int checkboard (void)
wdenkc6097192002-11-03 00:24:07 +0000130{
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200131 char *s;
132 char buf[64];
wdenkbf9e3b32004-02-12 00:47:09 +0000133 int i;
wdenkc6097192002-11-03 00:24:07 +0000134
wdenkbf9e3b32004-02-12 00:47:09 +0000135 i = getenv_r ("board_id", buf, sizeof (buf));
136 s = (i > 0) ? buf : NULL;
wdenkc6097192002-11-03 00:24:07 +0000137
138 if (s) {
wdenkbf9e3b32004-02-12 00:47:09 +0000139 printf ("%s ", s);
wdenkc6097192002-11-03 00:24:07 +0000140 } else {
wdenkbf9e3b32004-02-12 00:47:09 +0000141 printf ("<unknown> ");
wdenkc6097192002-11-03 00:24:07 +0000142 }
143
wdenkbf9e3b32004-02-12 00:47:09 +0000144 i = getenv_r ("serial#", buf, sizeof (buf));
145 s = (i > 0) ? buf : NULL;
wdenkc6097192002-11-03 00:24:07 +0000146
147 if (s) {
wdenkbf9e3b32004-02-12 00:47:09 +0000148 printf ("S/N %s\n", s);
wdenkc6097192002-11-03 00:24:07 +0000149 } else {
wdenkbf9e3b32004-02-12 00:47:09 +0000150 printf ("S/N <unknown>\n");
wdenkc6097192002-11-03 00:24:07 +0000151 }
152
wdenkbf9e3b32004-02-12 00:47:09 +0000153 printf ("CPU at %s MHz, ", strmhz (buf, gd->cpu_clk));
154 printf ("local bus at %s MHz\n", strmhz (buf, gd->bus_clk));
155 return (0);
wdenkc6097192002-11-03 00:24:07 +0000156}
157
158/*
159 * Initialize SDRAM
160 */
wdenkbf9e3b32004-02-12 00:47:09 +0000161long int initdram (int board_type)
wdenkc6097192002-11-03 00:24:07 +0000162{
wdenkbf9e3b32004-02-12 00:47:09 +0000163 volatile immap_t *immr = (immap_t *) CFG_IMMR;
164 volatile memctl8xx_t *memctl = &immr->im_memctl;
wdenkc6097192002-11-03 00:24:07 +0000165
wdenkbf9e3b32004-02-12 00:47:09 +0000166 upmconfig (UPMA,
167 (uint *) sdram_upm_table,
168 sizeof (sdram_upm_table) / sizeof (uint)
169 );
wdenkc6097192002-11-03 00:24:07 +0000170
wdenkbf9e3b32004-02-12 00:47:09 +0000171 /*
172 * Setup MAMR register
173 */
174 memctl->memc_mptpr = CFG_MPTPR_1BK_8K;
175 memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
wdenkc6097192002-11-03 00:24:07 +0000176
wdenkbf9e3b32004-02-12 00:47:09 +0000177 /*
178 * Map CS1* to SDRAM bank
179 */
180 memctl->memc_or1 = CFG_OR1;
181 memctl->memc_br1 = CFG_BR1;
wdenkc6097192002-11-03 00:24:07 +0000182
183 /*
184 * Perform SDRAM initialization sequence:
185 * 1. Apply at least one NOP command
186 * 2. 100 uS delay (JEDEC standard says 200 uS)
187 * 3. Issue 4 precharge commands
188 * 4. Perform two refresh cycles
189 * 5. Program mode register
190 *
191 * Program SDRAM for standard operation, sequential burst, burst length
192 * of 4, CAS latency of 2.
193 */
wdenkbf9e3b32004-02-12 00:47:09 +0000194 memctl->memc_mar = 0x00000000;
wdenkc6097192002-11-03 00:24:07 +0000195 memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 |
wdenkbf9e3b32004-02-12 00:47:09 +0000196 MCR_MLCF (0) | UPMA_NOP_ADDR;
197 udelay (200);
198 memctl->memc_mar = 0x00000000;
wdenkc6097192002-11-03 00:24:07 +0000199 memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 |
wdenkbf9e3b32004-02-12 00:47:09 +0000200 MCR_MLCF (4) | UPMA_PRECHARGE_ADDR;
wdenkc6097192002-11-03 00:24:07 +0000201
wdenkbf9e3b32004-02-12 00:47:09 +0000202 memctl->memc_mar = 0x00000000;
wdenkc6097192002-11-03 00:24:07 +0000203 memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 |
wdenkbf9e3b32004-02-12 00:47:09 +0000204 MCR_MLCF (2) | UPM_REFRESH_ADDR;
wdenkc6097192002-11-03 00:24:07 +0000205
wdenkbf9e3b32004-02-12 00:47:09 +0000206 memctl->memc_mar = 0x00000088;
wdenkc6097192002-11-03 00:24:07 +0000207 memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 |
wdenkbf9e3b32004-02-12 00:47:09 +0000208 MCR_MLCF (1) | UPMA_MRS_ADDR;
wdenkc6097192002-11-03 00:24:07 +0000209
wdenkbf9e3b32004-02-12 00:47:09 +0000210 memctl->memc_mar = 0x00000000;
wdenkc6097192002-11-03 00:24:07 +0000211 memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 |
wdenkbf9e3b32004-02-12 00:47:09 +0000212 MCR_MLCF (0) | UPMA_NOP_ADDR;
wdenkc6097192002-11-03 00:24:07 +0000213 /*
214 * Enable refresh
215 */
wdenkbf9e3b32004-02-12 00:47:09 +0000216 memctl->memc_mamr |= MAMR_PTAE;
wdenkc6097192002-11-03 00:24:07 +0000217
wdenkbf9e3b32004-02-12 00:47:09 +0000218 return (SDRAM_SIZE);
wdenkc6097192002-11-03 00:24:07 +0000219}
220
221/*
222 * Disk On Chip (DOC) Millenium initialization.
223 * The DOC lives in the CS2* space
224 */
Jon Loeligerc508a4c2007-07-09 18:31:28 -0500225#if defined(CONFIG_CMD_DOC)
wdenkbf9e3b32004-02-12 00:47:09 +0000226extern void doc_probe (ulong physadr);
wdenkc6097192002-11-03 00:24:07 +0000227
wdenkbf9e3b32004-02-12 00:47:09 +0000228void doc_init (void)
wdenkc6097192002-11-03 00:24:07 +0000229{
wdenkbf9e3b32004-02-12 00:47:09 +0000230 printf ("Probing at 0x%.8x: ", DOC_BASE);
231 doc_probe (DOC_BASE);
wdenkc6097192002-11-03 00:24:07 +0000232}
233#endif
234
235/*
236 * Miscellaneous intialization
237 */
wdenkbf9e3b32004-02-12 00:47:09 +0000238int misc_init_r (void)
wdenkc6097192002-11-03 00:24:07 +0000239{
wdenkbf9e3b32004-02-12 00:47:09 +0000240 volatile immap_t *immr = (immap_t *) CFG_IMMR;
241 volatile memctl8xx_t *memctl = &immr->im_memctl;
wdenkc6097192002-11-03 00:24:07 +0000242
243 /*
244 * Set up UPMB to handle the Virtex FPGA SelectMap interface
245 */
wdenkbf9e3b32004-02-12 00:47:09 +0000246 upmconfig (UPMB, (uint *) selectmap_upm_table,
247 sizeof (selectmap_upm_table) / sizeof (uint));
wdenkc6097192002-11-03 00:24:07 +0000248
wdenkbf9e3b32004-02-12 00:47:09 +0000249 memctl->memc_mbmr = 0x0;
wdenkc6097192002-11-03 00:24:07 +0000250
wdenkbf9e3b32004-02-12 00:47:09 +0000251 config_mpc8xx_ioports (immr);
wdenkc6097192002-11-03 00:24:07 +0000252
Jon Loeligerc508a4c2007-07-09 18:31:28 -0500253#if defined(CONFIG_CMD_MII)
wdenkbf9e3b32004-02-12 00:47:09 +0000254 mii_init ();
wdenkc6097192002-11-03 00:24:07 +0000255#endif
256
257#if (CONFIG_FPGA)
wdenkbf9e3b32004-02-12 00:47:09 +0000258 gen860t_init_fpga ();
wdenkc6097192002-11-03 00:24:07 +0000259#endif
260 return 0;
261}
262
263/*
264 * Final init hook before entering command loop.
265 */
wdenkbf9e3b32004-02-12 00:47:09 +0000266int last_stage_init (void)
wdenkc6097192002-11-03 00:24:07 +0000267{
wdenk7aa78612003-05-03 15:50:43 +0000268#if !defined(CONFIG_SC)
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200269 char buf[256];
wdenkc6097192002-11-03 00:24:07 +0000270 int i;
271
272 /*
wdenk7aa78612003-05-03 15:50:43 +0000273 * Turn the beeper volume all the way down in case this is a warm boot.
wdenkc6097192002-11-03 00:24:07 +0000274 */
wdenkbf9e3b32004-02-12 00:47:09 +0000275 set_beeper_volume (-64);
276 init_beeper ();
wdenkc6097192002-11-03 00:24:07 +0000277
278 /*
279 * Read the environment to see what to do with the beeper
280 */
wdenkbf9e3b32004-02-12 00:47:09 +0000281 i = getenv_r ("beeper", buf, sizeof (buf));
wdenkc6097192002-11-03 00:24:07 +0000282 if (i > 0) {
wdenkbf9e3b32004-02-12 00:47:09 +0000283 do_beeper (buf);
wdenkc6097192002-11-03 00:24:07 +0000284 }
wdenk7aa78612003-05-03 15:50:43 +0000285#endif
wdenkc6097192002-11-03 00:24:07 +0000286 return 0;
287}
wdenk7aa78612003-05-03 15:50:43 +0000288
289/*
290 * Stub to make POST code happy. Can't self-poweroff, so just hang.
291 */
wdenkbf9e3b32004-02-12 00:47:09 +0000292void board_poweroff (void)
wdenk7aa78612003-05-03 15:50:43 +0000293{
wdenkbf9e3b32004-02-12 00:47:09 +0000294 puts ("### Please power off the board ###\n");
295 while (1);
wdenk7aa78612003-05-03 15:50:43 +0000296}
297
wdenk8564acf2003-07-14 22:13:32 +0000298#ifdef CONFIG_POST
wdenk945af8d2003-07-16 21:53:01 +0000299/*
wdenk8564acf2003-07-14 22:13:32 +0000300 * Returns 1 if keys pressed to start the power-on long-running tests
301 * Called from board_init_f().
302 */
wdenkbf9e3b32004-02-12 00:47:09 +0000303int post_hotkeys_pressed (void)
wdenk8564acf2003-07-14 22:13:32 +0000304{
wdenkbf9e3b32004-02-12 00:47:09 +0000305 return 0; /* No hotkeys supported */
wdenk8564acf2003-07-14 22:13:32 +0000306}
307#endif