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wdenkc6097192002-11-03 00:24:07 +00001/*
Stefan Roesea47a12b2010-04-15 16:07:28 +02002 * arch/powerpc/kernel/pci_auto.c
wdenkc6097192002-11-03 00:24:07 +00003 *
4 * PCI autoconfiguration library
5 *
6 * Author: Matt Porter <mporter@mvista.com>
7 *
8 * Copyright 2000 MontaVista Software Inc.
9 *
Wolfgang Denk1a459662013-07-08 09:37:19 +020010 * SPDX-License-Identifier: GPL-2.0+
wdenkc6097192002-11-03 00:24:07 +000011 */
12
13#include <common.h>
14
wdenkc6097192002-11-03 00:24:07 +000015#include <pci.h>
16
17#undef DEBUG
18#ifdef DEBUG
19#define DEBUGF(x...) printf(x)
20#else
21#define DEBUGF(x...)
22#endif /* DEBUG */
23
24#define PCIAUTO_IDE_MODE_MASK 0x05
25
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020026/* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */
27#ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE
28#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8
Gary Jennejohn81b73de2007-08-31 15:21:46 +020029#endif
30
wdenkc6097192002-11-03 00:24:07 +000031/*
32 *
33 */
34
Andrew Sharpcb2bf932012-08-29 14:16:29 +000035void pciauto_region_init(struct pci_region *res)
wdenkc6097192002-11-03 00:24:07 +000036{
Sergei Shtylyovb7598a42007-04-23 15:30:39 +020037 /*
38 * Avoid allocating PCI resources from address 0 -- this is illegal
39 * according to PCI 2.1 and moreover, this is known to cause Linux IDE
40 * drivers to fail. Use a reasonable starting value of 0x1000 instead.
41 */
42 res->bus_lower = res->bus_start ? res->bus_start : 0x1000;
wdenkc6097192002-11-03 00:24:07 +000043}
44
Kumar Gala30e76d52008-10-21 08:36:08 -050045void pciauto_region_align(struct pci_region *res, pci_size_t size)
wdenkc6097192002-11-03 00:24:07 +000046{
47 res->bus_lower = ((res->bus_lower - 1) | (size - 1)) + 1;
48}
49
Andrew Sharpcb2bf932012-08-29 14:16:29 +000050int pciauto_region_allocate(struct pci_region *res, pci_size_t size,
51 pci_addr_t *bar)
wdenkc6097192002-11-03 00:24:07 +000052{
Kumar Gala30e76d52008-10-21 08:36:08 -050053 pci_addr_t addr;
wdenkc6097192002-11-03 00:24:07 +000054
wdenk3c74e322004-02-22 23:46:08 +000055 if (!res) {
wdenkc6097192002-11-03 00:24:07 +000056 DEBUGF("No resource");
57 goto error;
58 }
59
60 addr = ((res->bus_lower - 1) | (size - 1)) + 1;
61
wdenk3c74e322004-02-22 23:46:08 +000062 if (addr - res->bus_start + size > res->size) {
wdenkc6097192002-11-03 00:24:07 +000063 DEBUGF("No room in resource");
64 goto error;
65 }
66
67 res->bus_lower = addr + size;
68
Kumar Gala30e76d52008-10-21 08:36:08 -050069 DEBUGF("address=0x%llx bus_lower=0x%llx", (u64)addr, (u64)res->bus_lower);
wdenkc6097192002-11-03 00:24:07 +000070
71 *bar = addr;
72 return 0;
73
74 error:
Kumar Gala30e76d52008-10-21 08:36:08 -050075 *bar = (pci_addr_t)-1;
wdenkc6097192002-11-03 00:24:07 +000076 return -1;
77}
78
79/*
80 *
81 */
82
83void pciauto_setup_device(struct pci_controller *hose,
84 pci_dev_t dev, int bars_num,
85 struct pci_region *mem,
Kumar Galaa1790122006-01-11 13:24:15 -060086 struct pci_region *prefetch,
wdenkc6097192002-11-03 00:24:07 +000087 struct pci_region *io)
88{
Kumar Galacf5787f2012-09-19 04:47:36 +000089 u32 bar_response;
Kumar Gala30e76d52008-10-21 08:36:08 -050090 pci_size_t bar_size;
Andrew Sharpaf778c62012-08-01 12:27:16 +000091 u16 cmdstat = 0;
wdenkc6097192002-11-03 00:24:07 +000092 int bar, bar_nr = 0;
Andrew Sharp69fd2d32012-08-29 14:16:32 +000093#ifndef CONFIG_PCI_ENUM_ONLY
94 pci_addr_t bar_value;
95 struct pci_region *bar_res;
wdenkc6097192002-11-03 00:24:07 +000096 int found_mem64 = 0;
Andrew Sharp69fd2d32012-08-29 14:16:32 +000097#endif
wdenkc6097192002-11-03 00:24:07 +000098
Andrew Sharpaf778c62012-08-01 12:27:16 +000099 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
wdenkc6097192002-11-03 00:24:07 +0000100 cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | PCI_COMMAND_MASTER;
101
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000102 for (bar = PCI_BASE_ADDRESS_0;
103 bar < PCI_BASE_ADDRESS_0 + (bars_num * 4); bar += 4) {
wdenkc6097192002-11-03 00:24:07 +0000104 /* Tickle the BAR and get the response */
Andrew Sharp69fd2d32012-08-29 14:16:32 +0000105#ifndef CONFIG_PCI_ENUM_ONLY
wdenkc6097192002-11-03 00:24:07 +0000106 pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
Andrew Sharp69fd2d32012-08-29 14:16:32 +0000107#endif
wdenkc6097192002-11-03 00:24:07 +0000108 pci_hose_read_config_dword(hose, dev, bar, &bar_response);
109
110 /* If BAR is not implemented go to the next BAR */
111 if (!bar_response)
112 continue;
113
Andrew Sharp69fd2d32012-08-29 14:16:32 +0000114#ifndef CONFIG_PCI_ENUM_ONLY
wdenkc6097192002-11-03 00:24:07 +0000115 found_mem64 = 0;
Andrew Sharp69fd2d32012-08-29 14:16:32 +0000116#endif
wdenkc6097192002-11-03 00:24:07 +0000117
118 /* Check the BAR type and set our address mask */
wdenk3c74e322004-02-22 23:46:08 +0000119 if (bar_response & PCI_BASE_ADDRESS_SPACE) {
Jin Zhengxiong-R64188bd22c2b2006-06-27 18:12:02 +0800120 bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK))
121 & 0xffff) + 1;
Andrew Sharp69fd2d32012-08-29 14:16:32 +0000122#ifndef CONFIG_PCI_ENUM_ONLY
wdenkc6097192002-11-03 00:24:07 +0000123 bar_res = io;
Andrew Sharp69fd2d32012-08-29 14:16:32 +0000124#endif
wdenkc6097192002-11-03 00:24:07 +0000125
Kumar Gala30e76d52008-10-21 08:36:08 -0500126 DEBUGF("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ", bar_nr, (u64)bar_size);
wdenk3c74e322004-02-22 23:46:08 +0000127 } else {
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000128 if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
Kumar Gala30e76d52008-10-21 08:36:08 -0500129 PCI_BASE_ADDRESS_MEM_TYPE_64) {
130 u32 bar_response_upper;
131 u64 bar64;
Andrew Sharp69fd2d32012-08-29 14:16:32 +0000132
133#ifndef CONFIG_PCI_ENUM_ONLY
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000134 pci_hose_write_config_dword(hose, dev, bar + 4,
135 0xffffffff);
Andrew Sharp69fd2d32012-08-29 14:16:32 +0000136#endif
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000137 pci_hose_read_config_dword(hose, dev, bar + 4,
138 &bar_response_upper);
wdenkc6097192002-11-03 00:24:07 +0000139
Kumar Gala30e76d52008-10-21 08:36:08 -0500140 bar64 = ((u64)bar_response_upper << 32) | bar_response;
141
142 bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
Andrew Sharp69fd2d32012-08-29 14:16:32 +0000143#ifndef CONFIG_PCI_ENUM_ONLY
Kumar Gala30e76d52008-10-21 08:36:08 -0500144 found_mem64 = 1;
Andrew Sharp69fd2d32012-08-29 14:16:32 +0000145#endif
Kumar Gala30e76d52008-10-21 08:36:08 -0500146 } else {
147 bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
148 }
Andrew Sharp69fd2d32012-08-29 14:16:32 +0000149#ifndef CONFIG_PCI_ENUM_ONLY
Kumar Galaa1790122006-01-11 13:24:15 -0600150 if (prefetch && (bar_response & PCI_BASE_ADDRESS_MEM_PREFETCH))
151 bar_res = prefetch;
152 else
153 bar_res = mem;
Andrew Sharp69fd2d32012-08-29 14:16:32 +0000154#endif
wdenkc6097192002-11-03 00:24:07 +0000155
Kumar Gala30e76d52008-10-21 08:36:08 -0500156 DEBUGF("PCI Autoconfig: BAR %d, Mem, size=0x%llx, ", bar_nr, (u64)bar_size);
wdenkc6097192002-11-03 00:24:07 +0000157 }
158
Andrew Sharp69fd2d32012-08-29 14:16:32 +0000159#ifndef CONFIG_PCI_ENUM_ONLY
wdenk3c74e322004-02-22 23:46:08 +0000160 if (pciauto_region_allocate(bar_res, bar_size, &bar_value) == 0) {
wdenkc6097192002-11-03 00:24:07 +0000161 /* Write it out and update our limit */
Kumar Gala30e76d52008-10-21 08:36:08 -0500162 pci_hose_write_config_dword(hose, dev, bar, (u32)bar_value);
wdenkc6097192002-11-03 00:24:07 +0000163
wdenk3c74e322004-02-22 23:46:08 +0000164 if (found_mem64) {
wdenkc6097192002-11-03 00:24:07 +0000165 bar += 4;
Kumar Gala30e76d52008-10-21 08:36:08 -0500166#ifdef CONFIG_SYS_PCI_64BIT
167 pci_hose_write_config_dword(hose, dev, bar, (u32)(bar_value>>32));
168#else
169 /*
170 * If we are a 64-bit decoder then increment to the
171 * upper 32 bits of the bar and force it to locate
172 * in the lower 4GB of memory.
173 */
wdenkc6097192002-11-03 00:24:07 +0000174 pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
Kumar Gala30e76d52008-10-21 08:36:08 -0500175#endif
wdenkc6097192002-11-03 00:24:07 +0000176 }
177
wdenkc6097192002-11-03 00:24:07 +0000178 }
Andrew Sharp69fd2d32012-08-29 14:16:32 +0000179#endif
180 cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
181 PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
wdenkc6097192002-11-03 00:24:07 +0000182
183 DEBUGF("\n");
184
185 bar_nr++;
186 }
187
Andrew Sharpaf778c62012-08-01 12:27:16 +0000188 pci_hose_write_config_word(hose, dev, PCI_COMMAND, cmdstat);
Gary Jennejohn81b73de2007-08-31 15:21:46 +0200189 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200190 CONFIG_SYS_PCI_CACHE_LINE_SIZE);
wdenkc6097192002-11-03 00:24:07 +0000191 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
192}
193
Ed Swarthoutba5feb12007-07-11 14:51:48 -0500194void pciauto_prescan_setup_bridge(struct pci_controller *hose,
wdenkc6097192002-11-03 00:24:07 +0000195 pci_dev_t dev, int sub_bus)
196{
197 struct pci_region *pci_mem = hose->pci_mem;
Kumar Galaa1790122006-01-11 13:24:15 -0600198 struct pci_region *pci_prefetch = hose->pci_prefetch;
wdenkc6097192002-11-03 00:24:07 +0000199 struct pci_region *pci_io = hose->pci_io;
Andrew Sharpaf778c62012-08-01 12:27:16 +0000200 u16 cmdstat;
wdenkc6097192002-11-03 00:24:07 +0000201
Andrew Sharpaf778c62012-08-01 12:27:16 +0000202 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
wdenkc6097192002-11-03 00:24:07 +0000203
204 /* Configure bus number registers */
Ed Swarthoute8b85f32007-07-11 14:52:08 -0500205 pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS,
206 PCI_BUS(dev) - hose->first_busno);
207 pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS,
208 sub_bus - hose->first_busno);
wdenkc6097192002-11-03 00:24:07 +0000209 pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 0xff);
210
wdenk3c74e322004-02-22 23:46:08 +0000211 if (pci_mem) {
wdenkc6097192002-11-03 00:24:07 +0000212 /* Round memory allocator to 1MB boundary */
213 pciauto_region_align(pci_mem, 0x100000);
214
215 /* Set up memory and I/O filter limits, assume 32-bit I/O space */
216 pci_hose_write_config_word(hose, dev, PCI_MEMORY_BASE,
217 (pci_mem->bus_lower & 0xfff00000) >> 16);
218
219 cmdstat |= PCI_COMMAND_MEMORY;
220 }
221
Kumar Galaa1790122006-01-11 13:24:15 -0600222 if (pci_prefetch) {
223 /* Round memory allocator to 1MB boundary */
224 pciauto_region_align(pci_prefetch, 0x100000);
225
226 /* Set up memory and I/O filter limits, assume 32-bit I/O space */
227 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
228 (pci_prefetch->bus_lower & 0xfff00000) >> 16);
229
230 cmdstat |= PCI_COMMAND_MEMORY;
231 } else {
232 /* We don't support prefetchable memory for now, so disable */
233 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000);
Matthew McClintocka4e11552006-06-28 10:44:23 -0500234 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x0);
Kumar Galaa1790122006-01-11 13:24:15 -0600235 }
236
wdenk3c74e322004-02-22 23:46:08 +0000237 if (pci_io) {
wdenkc6097192002-11-03 00:24:07 +0000238 /* Round I/O allocator to 4KB boundary */
239 pciauto_region_align(pci_io, 0x1000);
240
241 pci_hose_write_config_byte(hose, dev, PCI_IO_BASE,
242 (pci_io->bus_lower & 0x0000f000) >> 8);
243 pci_hose_write_config_word(hose, dev, PCI_IO_BASE_UPPER16,
244 (pci_io->bus_lower & 0xffff0000) >> 16);
245
246 cmdstat |= PCI_COMMAND_IO;
247 }
248
wdenkc6097192002-11-03 00:24:07 +0000249 /* Enable memory and I/O accesses, enable bus master */
Andrew Sharpaf778c62012-08-01 12:27:16 +0000250 pci_hose_write_config_word(hose, dev, PCI_COMMAND,
251 cmdstat | PCI_COMMAND_MASTER);
wdenkc6097192002-11-03 00:24:07 +0000252}
253
Ed Swarthoutba5feb12007-07-11 14:51:48 -0500254void pciauto_postscan_setup_bridge(struct pci_controller *hose,
wdenkc6097192002-11-03 00:24:07 +0000255 pci_dev_t dev, int sub_bus)
256{
257 struct pci_region *pci_mem = hose->pci_mem;
Kumar Galaa1790122006-01-11 13:24:15 -0600258 struct pci_region *pci_prefetch = hose->pci_prefetch;
wdenkc6097192002-11-03 00:24:07 +0000259 struct pci_region *pci_io = hose->pci_io;
260
261 /* Configure bus number registers */
Ed Swarthoute8b85f32007-07-11 14:52:08 -0500262 pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS,
263 sub_bus - hose->first_busno);
wdenkc6097192002-11-03 00:24:07 +0000264
wdenk3c74e322004-02-22 23:46:08 +0000265 if (pci_mem) {
wdenkc6097192002-11-03 00:24:07 +0000266 /* Round memory allocator to 1MB boundary */
267 pciauto_region_align(pci_mem, 0x100000);
268
269 pci_hose_write_config_word(hose, dev, PCI_MEMORY_LIMIT,
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000270 (pci_mem->bus_lower - 1) >> 16);
wdenkc6097192002-11-03 00:24:07 +0000271 }
272
Kumar Galaa1790122006-01-11 13:24:15 -0600273 if (pci_prefetch) {
274 /* Round memory allocator to 1MB boundary */
275 pciauto_region_align(pci_prefetch, 0x100000);
276
277 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT,
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000278 (pci_prefetch->bus_lower - 1) >> 16);
Kumar Galaa1790122006-01-11 13:24:15 -0600279 }
280
wdenk3c74e322004-02-22 23:46:08 +0000281 if (pci_io) {
wdenkc6097192002-11-03 00:24:07 +0000282 /* Round I/O allocator to 4KB boundary */
283 pciauto_region_align(pci_io, 0x1000);
284
285 pci_hose_write_config_byte(hose, dev, PCI_IO_LIMIT,
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000286 ((pci_io->bus_lower - 1) & 0x0000f000) >> 8);
wdenkc6097192002-11-03 00:24:07 +0000287 pci_hose_write_config_word(hose, dev, PCI_IO_LIMIT_UPPER16,
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000288 ((pci_io->bus_lower - 1) & 0xffff0000) >> 16);
wdenkc6097192002-11-03 00:24:07 +0000289 }
290}
291
292/*
293 *
294 */
295
296void pciauto_config_init(struct pci_controller *hose)
297{
298 int i;
299
300 hose->pci_io = hose->pci_mem = NULL;
301
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000302 for (i = 0; i < hose->region_count; i++) {
wdenk3c74e322004-02-22 23:46:08 +0000303 switch(hose->regions[i].flags) {
wdenkc6097192002-11-03 00:24:07 +0000304 case PCI_REGION_IO:
305 if (!hose->pci_io ||
306 hose->pci_io->size < hose->regions[i].size)
307 hose->pci_io = hose->regions + i;
308 break;
309 case PCI_REGION_MEM:
310 if (!hose->pci_mem ||
311 hose->pci_mem->size < hose->regions[i].size)
312 hose->pci_mem = hose->regions + i;
313 break;
Kumar Galaa1790122006-01-11 13:24:15 -0600314 case (PCI_REGION_MEM | PCI_REGION_PREFETCH):
315 if (!hose->pci_prefetch ||
316 hose->pci_prefetch->size < hose->regions[i].size)
317 hose->pci_prefetch = hose->regions + i;
318 break;
wdenkc6097192002-11-03 00:24:07 +0000319 }
320 }
321
322
wdenk3c74e322004-02-22 23:46:08 +0000323 if (hose->pci_mem) {
wdenkc6097192002-11-03 00:24:07 +0000324 pciauto_region_init(hose->pci_mem);
325
Kumar Gala30e76d52008-10-21 08:36:08 -0500326 DEBUGF("PCI Autoconfig: Bus Memory region: [0x%llx-0x%llx],\n"
327 "\t\tPhysical Memory [%llx-%llxx]\n",
328 (u64)hose->pci_mem->bus_start,
329 (u64)(hose->pci_mem->bus_start + hose->pci_mem->size - 1),
330 (u64)hose->pci_mem->phys_start,
331 (u64)(hose->pci_mem->phys_start + hose->pci_mem->size - 1));
wdenkc6097192002-11-03 00:24:07 +0000332 }
333
Kumar Galaa1790122006-01-11 13:24:15 -0600334 if (hose->pci_prefetch) {
335 pciauto_region_init(hose->pci_prefetch);
336
Kumar Gala30e76d52008-10-21 08:36:08 -0500337 DEBUGF("PCI Autoconfig: Bus Prefetchable Mem: [0x%llx-0x%llx],\n"
338 "\t\tPhysical Memory [%llx-%llx]\n",
339 (u64)hose->pci_prefetch->bus_start,
340 (u64)(hose->pci_prefetch->bus_start +
341 hose->pci_prefetch->size - 1),
342 (u64)hose->pci_prefetch->phys_start,
343 (u64)(hose->pci_prefetch->phys_start +
344 hose->pci_prefetch->size - 1));
Kumar Galaa1790122006-01-11 13:24:15 -0600345 }
346
wdenk3c74e322004-02-22 23:46:08 +0000347 if (hose->pci_io) {
wdenkc6097192002-11-03 00:24:07 +0000348 pciauto_region_init(hose->pci_io);
349
Kumar Gala30e76d52008-10-21 08:36:08 -0500350 DEBUGF("PCI Autoconfig: Bus I/O region: [0x%llx-0x%llx],\n"
351 "\t\tPhysical Memory: [%llx-%llx]\n",
352 (u64)hose->pci_io->bus_start,
353 (u64)(hose->pci_io->bus_start + hose->pci_io->size - 1),
354 (u64)hose->pci_io->phys_start,
355 (u64)(hose->pci_io->phys_start + hose->pci_io->size - 1));
Ed Swarthoutba5feb12007-07-11 14:51:48 -0500356
wdenkc6097192002-11-03 00:24:07 +0000357 }
358}
359
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000360/*
361 * HJF: Changed this to return int. I think this is required
wdenkc7de8292002-11-19 11:04:11 +0000362 * to get the correct result when scanning bridges
363 */
364int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
wdenkc6097192002-11-03 00:24:07 +0000365{
wdenkc7de8292002-11-19 11:04:11 +0000366 unsigned int sub_bus = PCI_BUS(dev);
wdenkc6097192002-11-03 00:24:07 +0000367 unsigned short class;
368 unsigned char prg_iface;
wdenk5653fc32004-02-08 22:55:38 +0000369 int n;
wdenkc6097192002-11-03 00:24:07 +0000370
371 pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
372
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000373 switch (class) {
wdenkc6097192002-11-03 00:24:07 +0000374 case PCI_CLASS_BRIDGE_PCI:
wdenkdb2f721f2003-03-06 00:58:30 +0000375 hose->current_busno++;
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000376 pciauto_setup_device(hose, dev, 2, hose->pci_mem,
377 hose->pci_prefetch, hose->pci_io);
wdenkc6097192002-11-03 00:24:07 +0000378
wdenkdb2f721f2003-03-06 00:58:30 +0000379 DEBUGF("PCI Autoconfig: Found P2P bridge, device %d\n", PCI_DEV(dev));
wdenkcd37d9e2004-02-10 00:03:41 +0000380
wdenk3c74e322004-02-22 23:46:08 +0000381 /* Passing in current_busno allows for sibling P2P bridges */
wdenk5653fc32004-02-08 22:55:38 +0000382 pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
wdenkcd37d9e2004-02-10 00:03:41 +0000383 /*
wdenk3c74e322004-02-22 23:46:08 +0000384 * need to figure out if this is a subordinate bridge on the bus
wdenk5653fc32004-02-08 22:55:38 +0000385 * to be able to properly set the pri/sec/sub bridge registers.
386 */
387 n = pci_hose_scan_bus(hose, hose->current_busno);
wdenk8bde7f72003-06-27 21:31:46 +0000388
wdenk3c74e322004-02-22 23:46:08 +0000389 /* figure out the deepest we've gone for this leg */
wdenk5653fc32004-02-08 22:55:38 +0000390 sub_bus = max(n, sub_bus);
wdenkdb2f721f2003-03-06 00:58:30 +0000391 pciauto_postscan_setup_bridge(hose, dev, sub_bus);
wdenk5653fc32004-02-08 22:55:38 +0000392
wdenkdb2f721f2003-03-06 00:58:30 +0000393 sub_bus = hose->current_busno;
wdenkc6097192002-11-03 00:24:07 +0000394 break;
395
396 case PCI_CLASS_STORAGE_IDE:
397 pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prg_iface);
wdenk3c74e322004-02-22 23:46:08 +0000398 if (!(prg_iface & PCIAUTO_IDE_MODE_MASK)) {
399 DEBUGF("PCI Autoconfig: Skipping legacy mode IDE controller\n");
400 return sub_bus;
401 }
wdenkc6097192002-11-03 00:24:07 +0000402
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000403 pciauto_setup_device(hose, dev, 6, hose->pci_mem,
404 hose->pci_prefetch, hose->pci_io);
wdenkc6097192002-11-03 00:24:07 +0000405 break;
406
wdenk1cb8e982003-03-06 21:55:29 +0000407 case PCI_CLASS_BRIDGE_CARDBUS:
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000408 /*
409 * just do a minimal setup of the bridge,
410 * let the OS take care of the rest
411 */
412 pciauto_setup_device(hose, dev, 0, hose->pci_mem,
413 hose->pci_prefetch, hose->pci_io);
wdenk1cb8e982003-03-06 21:55:29 +0000414
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000415 DEBUGF("PCI Autoconfig: Found P2CardBus bridge, device %d\n",
416 PCI_DEV(dev));
wdenk1cb8e982003-03-06 21:55:29 +0000417
418 hose->current_busno++;
419 break;
420
TsiChung Liewf33fca22008-03-30 01:19:06 -0500421#if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE)
wdenke0ac62d2003-08-17 18:55:18 +0000422 case PCI_CLASS_BRIDGE_OTHER:
423 DEBUGF("PCI Autoconfig: Skipping bridge device %d\n",
424 PCI_DEV(dev));
425 break;
426#endif
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200427#if defined(CONFIG_MPC834x) && !defined(CONFIG_VME8349)
Rafal Jaworowski6902df52005-10-17 02:39:53 +0200428 case PCI_CLASS_BRIDGE_OTHER:
429 /*
430 * The host/PCI bridge 1 seems broken in 8349 - it presents
431 * itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_
432 * device claiming resources io/mem/irq.. we only allow for
433 * the PIMMR window to be allocated (BAR0 - 1MB size)
434 */
435 DEBUGF("PCI Autoconfig: Broken bridge found, only minimal config\n");
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000436 pciauto_setup_device(hose, dev, 0, hose->pci_mem,
437 hose->pci_prefetch, hose->pci_io);
Rafal Jaworowski6902df52005-10-17 02:39:53 +0200438 break;
439#endif
Andrew Sharp69fd2d32012-08-29 14:16:32 +0000440
441 case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */
442 DEBUGF("PCI AutoConfig: Found PowerPC device\n");
443
wdenkc6097192002-11-03 00:24:07 +0000444 default:
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000445 pciauto_setup_device(hose, dev, 6, hose->pci_mem,
446 hose->pci_prefetch, hose->pci_io);
wdenkc6097192002-11-03 00:24:07 +0000447 break;
448 }
wdenkc7de8292002-11-19 11:04:11 +0000449
450 return sub_bus;
wdenkc6097192002-11-03 00:24:07 +0000451}