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Tang Yuantian83c484d2011-10-07 19:26:58 +00001/*
2 * Copyright (C) 2011 Freescale Semiconductor, Inc.
3 * Author: Tang Yuantian <b29983@freescale.com>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18 * MA 02111-1307 USA
19 */
20
21#include <common.h>
22#include <pci.h>
23#include <command.h>
24#include <asm/byteorder.h>
25#include <malloc.h>
26#include <asm/io.h>
27#include <fis.h>
Pavel Herrmanne46a4352012-09-27 23:18:04 +000028#include <sata.h>
Tang Yuantian83c484d2011-10-07 19:26:58 +000029#include <libata.h>
30#include "sata_sil.h"
31
32/* Convert sectorsize to wordsize */
33#define ATA_SECTOR_WORDS (ATA_SECT_SIZE/2)
Tang Yuantian83c484d2011-10-07 19:26:58 +000034#define virt_to_bus(devno, v) pci_virt_to_mem(devno, (void *) (v))
35
36static struct sata_info sata_info;
37
38static struct pci_device_id supported[] = {
39 {PCI_VENDOR_ID_SILICONIMAGE, PCI_DEVICE_ID_SIL3131},
40 {PCI_VENDOR_ID_SILICONIMAGE, PCI_DEVICE_ID_SIL3132},
41 {PCI_VENDOR_ID_SILICONIMAGE, PCI_DEVICE_ID_SIL3124},
42 {}
43};
44
45static void sil_sata_dump_fis(struct sata_fis_d2h *s)
46{
47 printf("Status FIS dump:\n");
48 printf("fis_type: %02x\n", s->fis_type);
49 printf("pm_port_i: %02x\n", s->pm_port_i);
50 printf("status: %02x\n", s->status);
51 printf("error: %02x\n", s->error);
52 printf("lba_low: %02x\n", s->lba_low);
53 printf("lba_mid: %02x\n", s->lba_mid);
54 printf("lba_high: %02x\n", s->lba_high);
55 printf("device: %02x\n", s->device);
56 printf("lba_low_exp: %02x\n", s->lba_low_exp);
57 printf("lba_mid_exp: %02x\n", s->lba_mid_exp);
58 printf("lba_high_exp: %02x\n", s->lba_high_exp);
59 printf("res1: %02x\n", s->res1);
60 printf("sector_count: %02x\n", s->sector_count);
61 printf("sector_count_exp: %02x\n", s->sector_count_exp);
62}
63
64static const char *sata_spd_string(unsigned int speed)
65{
66 static const char * const spd_str[] = {
67 "1.5 Gbps",
68 "3.0 Gbps",
69 "6.0 Gbps",
70 };
71
72 if ((speed - 1) > 2)
73 return "<unknown>";
74
75 return spd_str[speed - 1];
76}
77
78static u32 ata_wait_register(void *reg, u32 mask,
79 u32 val, int timeout_msec)
80{
81 u32 tmp;
82
83 tmp = readl(reg);
84 while ((tmp & mask) == val && timeout_msec > 0) {
85 mdelay(1);
86 timeout_msec--;
87 tmp = readl(reg);
88 }
89
90 return tmp;
91}
92
93static void sil_config_port(void *port)
94{
95 /* configure IRQ WoC */
96 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
97
98 /* zero error counters. */
99 writew(0x8000, port + PORT_DECODE_ERR_THRESH);
100 writew(0x8000, port + PORT_CRC_ERR_THRESH);
101 writew(0x8000, port + PORT_HSHK_ERR_THRESH);
102 writew(0x0000, port + PORT_DECODE_ERR_CNT);
103 writew(0x0000, port + PORT_CRC_ERR_CNT);
104 writew(0x0000, port + PORT_HSHK_ERR_CNT);
105
106 /* always use 64bit activation */
107 writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR);
108
109 /* clear port multiplier enable and resume bits */
110 writel(PORT_CS_PMP_EN | PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR);
111}
112
113static int sil_init_port(void *port)
114{
115 u32 tmp;
116
117 writel(PORT_CS_INIT, port + PORT_CTRL_STAT);
118 ata_wait_register(port + PORT_CTRL_STAT,
119 PORT_CS_INIT, PORT_CS_INIT, 100);
120 tmp = ata_wait_register(port + PORT_CTRL_STAT,
121 PORT_CS_RDY, 0, 100);
122
123 if ((tmp & (PORT_CS_INIT | PORT_CS_RDY)) != PORT_CS_RDY)
124 return 1;
125
126 return 0;
127}
128
129static void sil_read_fis(int dev, int tag, struct sata_fis_d2h *fis)
130{
131 struct sil_sata *sata = sata_dev_desc[dev].priv;
132 void *port = sata->port;
133 struct sil_prb *prb;
134 int i;
135 u32 *src, *dst;
136
137 prb = port + PORT_LRAM + tag * PORT_LRAM_SLOT_SZ;
138 src = (u32 *)&prb->fis;
139 dst = (u32 *)fis;
140 for (i = 0; i < sizeof(struct sata_fis_h2d); i += 4)
141 *dst++ = readl(src++);
142}
143
144static int sil_exec_cmd(int dev, struct sil_cmd_block *pcmd, int tag)
145{
146 struct sil_sata *sata = sata_dev_desc[dev].priv;
147 void *port = sata->port;
148 u64 paddr = virt_to_bus(sata->devno, pcmd);
149 u32 irq_mask, irq_stat;
150 int rc;
151
152 writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR, port + PORT_IRQ_ENABLE_CLR);
153
154 /* better to add momery barrior here */
155 writel((u32)paddr, port + PORT_CMD_ACTIVATE + tag * 8);
156 writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + tag * 8 + 4);
157
158 irq_mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT;
159 irq_stat = ata_wait_register(port + PORT_IRQ_STAT, irq_mask,
160 0, 10000);
161
162 /* clear IRQs */
163 writel(irq_mask, port + PORT_IRQ_STAT);
164 irq_stat >>= PORT_IRQ_RAW_SHIFT;
165
166 if (irq_stat & PORT_IRQ_COMPLETE)
167 rc = 0;
168 else {
169 /* force port into known state */
170 sil_init_port(port);
171 if (irq_stat & PORT_IRQ_ERROR)
172 rc = 1; /* error */
173 else
174 rc = 2; /* busy */
175 }
176
177 return rc;
178}
179
180static int sil_cmd_set_feature(int dev)
181{
182 struct sil_sata *sata = sata_dev_desc[dev].priv;
183 struct sil_cmd_block cmdb, *pcmd = &cmdb;
184 struct sata_fis_d2h fis;
185 u8 udma_cap;
186 int ret;
187
188 memset((void *)&cmdb, 0, sizeof(struct sil_cmd_block));
189 pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
190 pcmd->prb.fis.pm_port_c = (1 << 7);
191 pcmd->prb.fis.command = ATA_CMD_SET_FEATURES;
192 pcmd->prb.fis.features = SETFEATURES_XFER;
193
194 /* First check the device capablity */
195 udma_cap = (u8)(sata->udma & 0xff);
196 debug("udma_cap %02x\n", udma_cap);
197
198 if (udma_cap == ATA_UDMA6)
199 pcmd->prb.fis.sector_count = XFER_UDMA_6;
200 if (udma_cap == ATA_UDMA5)
201 pcmd->prb.fis.sector_count = XFER_UDMA_5;
202 if (udma_cap == ATA_UDMA4)
203 pcmd->prb.fis.sector_count = XFER_UDMA_4;
204 if (udma_cap == ATA_UDMA3)
205 pcmd->prb.fis.sector_count = XFER_UDMA_3;
206
207 ret = sil_exec_cmd(dev, pcmd, 0);
208 if (ret) {
209 sil_read_fis(dev, 0, &fis);
210 printf("Err: exe cmd(0x%x).\n",
211 readl(sata->port + PORT_SERROR));
212 sil_sata_dump_fis(&fis);
213 return 1;
214 }
215
216 return 0;
217}
218
219static int sil_cmd_identify_device(int dev, u16 *id)
220{
221 struct sil_sata *sata = sata_dev_desc[dev].priv;
222 struct sil_cmd_block cmdb, *pcmd = &cmdb;
223 struct sata_fis_d2h fis;
224 int ret;
225
226 memset((void *)&cmdb, 0, sizeof(struct sil_cmd_block));
227 pcmd->prb.ctrl = cpu_to_le16(PRB_CTRL_PROTOCOL);
228 pcmd->prb.prot = cpu_to_le16(PRB_PROT_READ);
229 pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
230 pcmd->prb.fis.pm_port_c = (1 << 7);
231 pcmd->prb.fis.command = ATA_CMD_ID_ATA;
232 pcmd->sge.addr = cpu_to_le64(virt_to_bus(sata->devno, id));
233 pcmd->sge.cnt = cpu_to_le32(sizeof(id[0]) * ATA_ID_WORDS);
234 pcmd->sge.flags = cpu_to_le32(SGE_TRM);
235
236 ret = sil_exec_cmd(dev, pcmd, 0);
237 if (ret) {
238 sil_read_fis(dev, 0, &fis);
239 printf("Err: id cmd(0x%x).\n", readl(sata->port + PORT_SERROR));
240 sil_sata_dump_fis(&fis);
241 return 1;
242 }
243 ata_swap_buf_le16(id, ATA_ID_WORDS);
244
245 return 0;
246}
247
248static int sil_cmd_soft_reset(int dev)
249{
250 struct sil_cmd_block cmdb, *pcmd = &cmdb;
251 struct sil_sata *sata = sata_dev_desc[dev].priv;
252 struct sata_fis_d2h fis;
253 void *port = sata->port;
254 int ret;
255
256 /* put the port into known state */
257 if (sil_init_port(port)) {
258 printf("SRST: port %d not ready\n", dev);
259 return 1;
260 }
261
262 memset((void *)&cmdb, 0, sizeof(struct sil_cmd_block));
263
264 pcmd->prb.ctrl = cpu_to_le16(PRB_CTRL_SRST);
265 pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
266 pcmd->prb.fis.pm_port_c = 0xf;
267
268 ret = sil_exec_cmd(dev, &cmdb, 0);
269 if (ret) {
270 sil_read_fis(dev, 0, &fis);
271 printf("SRST cmd error.\n");
272 sil_sata_dump_fis(&fis);
273 return 1;
274 }
275
276 return 0;
277}
278
279static ulong sil_sata_rw_cmd(int dev, ulong start, ulong blkcnt,
280 u8 *buffer, int is_write)
281{
282 struct sil_sata *sata = sata_dev_desc[dev].priv;
283 struct sil_cmd_block cmdb, *pcmd = &cmdb;
284 struct sata_fis_d2h fis;
285 u64 block;
286 int ret;
287
288 block = (u64)start;
289 memset(pcmd, 0, sizeof(struct sil_cmd_block));
290 pcmd->prb.ctrl = cpu_to_le16(PRB_CTRL_PROTOCOL);
291 pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
292 pcmd->prb.fis.pm_port_c = (1 << 7);
293 if (is_write) {
294 pcmd->prb.fis.command = ATA_CMD_WRITE;
295 pcmd->prb.prot = cpu_to_le16(PRB_PROT_WRITE);
296 } else {
297 pcmd->prb.fis.command = ATA_CMD_READ;
298 pcmd->prb.prot = cpu_to_le16(PRB_PROT_READ);
299 }
300
301 pcmd->prb.fis.device = ATA_LBA;
302 pcmd->prb.fis.device |= (block >> 24) & 0xf;
303 pcmd->prb.fis.lba_high = (block >> 16) & 0xff;
304 pcmd->prb.fis.lba_mid = (block >> 8) & 0xff;
305 pcmd->prb.fis.lba_low = block & 0xff;
306 pcmd->prb.fis.sector_count = (u8)blkcnt & 0xff;
307
308 pcmd->sge.addr = cpu_to_le64(virt_to_bus(sata->devno, buffer));
309 pcmd->sge.cnt = cpu_to_le32(blkcnt * ATA_SECT_SIZE);
310 pcmd->sge.flags = cpu_to_le32(SGE_TRM);
311
312 ret = sil_exec_cmd(dev, pcmd, 0);
313 if (ret) {
314 sil_read_fis(dev, 0, &fis);
315 printf("Err: rw cmd(0x%08x).\n",
316 readl(sata->port + PORT_SERROR));
317 sil_sata_dump_fis(&fis);
318 return 1;
319 }
320
321 return blkcnt;
322}
323
324static ulong sil_sata_rw_cmd_ext(int dev, ulong start, ulong blkcnt,
325 u8 *buffer, int is_write)
326{
327 struct sil_sata *sata = sata_dev_desc[dev].priv;
328 struct sil_cmd_block cmdb, *pcmd = &cmdb;
329 struct sata_fis_d2h fis;
330 u64 block;
331 int ret;
332
333 block = (u64)start;
334 memset(pcmd, 0, sizeof(struct sil_cmd_block));
335 pcmd->prb.ctrl = cpu_to_le16(PRB_CTRL_PROTOCOL);
336 pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
337 pcmd->prb.fis.pm_port_c = (1 << 7);
338 if (is_write) {
339 pcmd->prb.fis.command = ATA_CMD_WRITE_EXT;
340 pcmd->prb.prot = cpu_to_le16(PRB_PROT_WRITE);
341 } else {
342 pcmd->prb.fis.command = ATA_CMD_READ_EXT;
343 pcmd->prb.prot = cpu_to_le16(PRB_PROT_READ);
344 }
345
346 pcmd->prb.fis.lba_high_exp = (block >> 40) & 0xff;
347 pcmd->prb.fis.lba_mid_exp = (block >> 32) & 0xff;
348 pcmd->prb.fis.lba_low_exp = (block >> 24) & 0xff;
349 pcmd->prb.fis.lba_high = (block >> 16) & 0xff;
350 pcmd->prb.fis.lba_mid = (block >> 8) & 0xff;
351 pcmd->prb.fis.lba_low = block & 0xff;
352 pcmd->prb.fis.device = ATA_LBA;
353 pcmd->prb.fis.sector_count_exp = (blkcnt >> 8) & 0xff;
354 pcmd->prb.fis.sector_count = blkcnt & 0xff;
355
356 pcmd->sge.addr = cpu_to_le64(virt_to_bus(sata->devno, buffer));
357 pcmd->sge.cnt = cpu_to_le32(blkcnt * ATA_SECT_SIZE);
358 pcmd->sge.flags = cpu_to_le32(SGE_TRM);
359
360 ret = sil_exec_cmd(dev, pcmd, 0);
361 if (ret) {
362 sil_read_fis(dev, 0, &fis);
363 printf("Err: rw ext cmd(0x%08x).\n",
364 readl(sata->port + PORT_SERROR));
365 sil_sata_dump_fis(&fis);
366 return 1;
367 }
368
369 return blkcnt;
370}
371
372ulong sil_sata_rw_lba28(int dev, ulong blknr, lbaint_t blkcnt,
Tom Rini0e7d8562012-09-29 07:57:25 -0700373 const void *buffer, int is_write)
Tang Yuantian83c484d2011-10-07 19:26:58 +0000374{
375 ulong start, blks, max_blks;
376 u8 *addr;
377
378 start = blknr;
379 blks = blkcnt;
380 addr = (u8 *)buffer;
381
382 max_blks = ATA_MAX_SECTORS;
383 do {
384 if (blks > max_blks) {
385 sil_sata_rw_cmd(dev, start, max_blks, addr, is_write);
386 start += max_blks;
387 blks -= max_blks;
388 addr += ATA_SECT_SIZE * max_blks;
389 } else {
390 sil_sata_rw_cmd(dev, start, blks, addr, is_write);
391 start += blks;
392 blks = 0;
393 addr += ATA_SECT_SIZE * blks;
394 }
395 } while (blks != 0);
396
397 return blkcnt;
398}
399
400ulong sil_sata_rw_lba48(int dev, ulong blknr, lbaint_t blkcnt,
Tom Rini0e7d8562012-09-29 07:57:25 -0700401 const void *buffer, int is_write)
Tang Yuantian83c484d2011-10-07 19:26:58 +0000402{
403 ulong start, blks, max_blks;
404 u8 *addr;
405
406 start = blknr;
407 blks = blkcnt;
408 addr = (u8 *)buffer;
409
410 max_blks = ATA_MAX_SECTORS_LBA48;
411 do {
412 if (blks > max_blks) {
413 sil_sata_rw_cmd_ext(dev, start, max_blks,
414 addr, is_write);
415 start += max_blks;
416 blks -= max_blks;
417 addr += ATA_SECT_SIZE * max_blks;
418 } else {
419 sil_sata_rw_cmd_ext(dev, start, blks,
420 addr, is_write);
421 start += blks;
422 blks = 0;
423 addr += ATA_SECT_SIZE * blks;
424 }
425 } while (blks != 0);
426
427 return blkcnt;
428}
429
430void sil_sata_cmd_flush_cache(int dev)
431{
432 struct sil_cmd_block cmdb, *pcmd = &cmdb;
433
434 memset((void *)pcmd, 0, sizeof(struct sil_cmd_block));
435 pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
436 pcmd->prb.fis.pm_port_c = (1 << 7);
437 pcmd->prb.fis.command = ATA_CMD_FLUSH;
438
439 sil_exec_cmd(dev, pcmd, 0);
440}
441
442void sil_sata_cmd_flush_cache_ext(int dev)
443{
444 struct sil_cmd_block cmdb, *pcmd = &cmdb;
445
446 memset((void *)pcmd, 0, sizeof(struct sil_cmd_block));
447 pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
448 pcmd->prb.fis.pm_port_c = (1 << 7);
449 pcmd->prb.fis.command = ATA_CMD_FLUSH_EXT;
450
451 sil_exec_cmd(dev, pcmd, 0);
452}
453
454static void sil_sata_init_wcache(int dev, u16 *id)
455{
456 struct sil_sata *sata = sata_dev_desc[dev].priv;
457
458 if (ata_id_has_wcache(id) && ata_id_wcache_enabled(id))
459 sata->wcache = 1;
460 if (ata_id_has_flush(id))
461 sata->flush = 1;
462 if (ata_id_has_flush_ext(id))
463 sata->flush_ext = 1;
464}
465
466static int sil_sata_get_wcache(int dev)
467{
468 struct sil_sata *sata = sata_dev_desc[dev].priv;
469
470 return sata->wcache;
471}
472
473static int sil_sata_get_flush(int dev)
474{
475 struct sil_sata *sata = sata_dev_desc[dev].priv;
476
477 return sata->flush;
478}
479
480static int sil_sata_get_flush_ext(int dev)
481{
482 struct sil_sata *sata = sata_dev_desc[dev].priv;
483
484 return sata->flush_ext;
485}
486
487/*
488 * SATA interface between low level driver and command layer
489 */
490ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer)
491{
492 struct sil_sata *sata = sata_dev_desc[dev].priv;
493 ulong rc;
494
495 if (sata->lba48)
496 rc = sil_sata_rw_lba48(dev, blknr, blkcnt, buffer, READ_CMD);
497 else
498 rc = sil_sata_rw_lba28(dev, blknr, blkcnt, buffer, READ_CMD);
499
500 return rc;
501}
502
503/*
504 * SATA interface between low level driver and command layer
505 */
Tom Rini0e7d8562012-09-29 07:57:25 -0700506ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer)
Tang Yuantian83c484d2011-10-07 19:26:58 +0000507{
508 struct sil_sata *sata = sata_dev_desc[dev].priv;
509 ulong rc;
510
511 if (sata->lba48) {
512 rc = sil_sata_rw_lba48(dev, blknr, blkcnt, buffer, WRITE_CMD);
513 if (sil_sata_get_wcache(dev) && sil_sata_get_flush_ext(dev))
514 sil_sata_cmd_flush_cache_ext(dev);
515 } else {
516 rc = sil_sata_rw_lba28(dev, blknr, blkcnt, buffer, WRITE_CMD);
517 if (sil_sata_get_wcache(dev) && sil_sata_get_flush(dev))
518 sil_sata_cmd_flush_cache(dev);
519 }
520
521 return rc;
522}
523
524/*
525 * SATA interface between low level driver and command layer
526 */
527int init_sata(int dev)
528{
529 static int init_done, idx;
530 pci_dev_t devno;
531 u16 word;
532
533 if (init_done == 1 && dev < sata_info.maxport)
534 return 1;
535
536 init_done = 1;
537
538 /* Find PCI device(s) */
539 devno = pci_find_devices(supported, idx++);
540 if (devno == -1)
541 return 1;
542
543 pci_read_config_word(devno, PCI_DEVICE_ID, &word);
544
545 /* get the port count */
546 word &= 0xf;
547
548 sata_info.portbase = sata_info.maxport;
549 sata_info.maxport = sata_info.portbase + word;
550 sata_info.devno = devno;
551
552 /* Read out all BARs */
553 sata_info.iobase[0] = (ulong)pci_map_bar(devno,
554 PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
555 sata_info.iobase[1] = (ulong)pci_map_bar(devno,
556 PCI_BASE_ADDRESS_2, PCI_REGION_MEM);
557 sata_info.iobase[2] = (ulong)pci_map_bar(devno,
558 PCI_BASE_ADDRESS_4, PCI_REGION_MEM);
559
560 /* mask out the unused bits */
561 sata_info.iobase[0] &= 0xffffff80;
562 sata_info.iobase[1] &= 0xfffffc00;
563 sata_info.iobase[2] &= 0xffffff80;
564
565 /* Enable Bus Mastering and memory region */
566 pci_write_config_word(devno, PCI_COMMAND,
567 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
568
569 /* Check if mem accesses and Bus Mastering are enabled. */
570 pci_read_config_word(devno, PCI_COMMAND, &word);
571 if (!(word & PCI_COMMAND_MEMORY) ||
572 (!(word & PCI_COMMAND_MASTER))) {
573 printf("Error: Can not enable MEM access or Bus Mastering.\n");
574 debug("PCI command: %04x\n", word);
575 return 1;
576 }
577
578 /* GPIO off */
579 writel(0, (void *)(sata_info.iobase[0] + HOST_FLASH_CMD));
580 /* clear global reset & mask interrupts during initialization */
581 writel(0, (void *)(sata_info.iobase[0] + HOST_CTRL));
582
583 return 0;
584}
585
586/*
587 * SATA interface between low level driver and command layer
588 */
589int scan_sata(int dev)
590{
591 unsigned char serial[ATA_ID_SERNO_LEN + 1];
592 unsigned char firmware[ATA_ID_FW_REV_LEN + 1];
593 unsigned char product[ATA_ID_PROD_LEN + 1];
594 struct sil_sata *sata;
595 void *port;
596 int cnt;
597 u16 *id;
598 u32 tmp;
599
600 if (dev >= sata_info.maxport) {
601 printf("SATA#%d is not present\n", dev);
602 return 1;
603 }
604
605 printf("SATA#%d\n", dev);
606 port = (void *)sata_info.iobase[1] +
607 PORT_REGS_SIZE * (dev - sata_info.portbase);
608
609 /* Initial PHY setting */
610 writel(0x20c, port + PORT_PHY_CFG);
611
612 /* clear port RST */
613 tmp = readl(port + PORT_CTRL_STAT);
614 if (tmp & PORT_CS_PORT_RST) {
615 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
616 tmp = ata_wait_register(port + PORT_CTRL_STAT,
617 PORT_CS_PORT_RST, PORT_CS_PORT_RST, 100);
618 if (tmp & PORT_CS_PORT_RST)
619 printf("Err: Failed to clear port RST\n");
620 }
621
622 /* Check if device is present */
623 for (cnt = 0; cnt < 100; cnt++) {
624 tmp = readl(port + PORT_SSTATUS);
625 if ((tmp & 0xF) == 0x3)
626 break;
627 mdelay(1);
628 }
629
630 tmp = readl(port + PORT_SSTATUS);
631 if ((tmp & 0xf) != 0x3) {
632 printf(" (No RDY)\n");
633 return 1;
634 }
635
636 /* Wait for port ready */
637 tmp = ata_wait_register(port + PORT_CTRL_STAT,
638 PORT_CS_RDY, PORT_CS_RDY, 100);
639 if ((tmp & PORT_CS_RDY) != PORT_CS_RDY) {
640 printf("%d port not ready.\n", dev);
641 return 1;
642 }
643
644 /* configure port */
645 sil_config_port(port);
646
647 /* Reset port */
648 writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
649 readl(port + PORT_CTRL_STAT);
650 tmp = ata_wait_register(port + PORT_CTRL_STAT, PORT_CS_DEV_RST,
651 PORT_CS_DEV_RST, 100);
652 if (tmp & PORT_CS_DEV_RST) {
653 printf("%d port reset failed.\n", dev);
654 return 1;
655 }
656
657 sata = (struct sil_sata *)malloc(sizeof(struct sil_sata));
658 if (!sata) {
659 printf("%d no memory.\n", dev);
660 return 1;
661 }
662 memset((void *)sata, 0, sizeof(struct sil_sata));
663
664 /* turn on port interrupt */
665 tmp = readl((void *)(sata_info.iobase[0] + HOST_CTRL));
666 tmp |= (1 << (dev - sata_info.portbase));
667 writel(tmp, (void *)(sata_info.iobase[0] + HOST_CTRL));
668
669 /* Save the private struct to block device struct */
670 sata_dev_desc[dev].priv = (void *)sata;
671 sata->port = port;
672 sata->devno = sata_info.devno;
673 sprintf(sata->name, "SATA#%d", dev);
674 sil_cmd_soft_reset(dev);
675 tmp = readl(port + PORT_SSTATUS);
676 tmp = (tmp >> 4) & 0xf;
677 printf(" (%s)\n", sata_spd_string(tmp));
678
679 id = (u16 *)malloc(ATA_ID_WORDS * 2);
680 if (!id) {
681 printf("Id malloc failed\n");
682 free((void *)sata);
683 return 1;
684 }
685 sil_cmd_identify_device(dev, id);
686
687#ifdef CONFIG_LBA48
688 /* Check if support LBA48 */
689 if (ata_id_has_lba48(id)) {
690 sata_dev_desc[dev].lba48 = 1;
691 sata->lba48 = 1;
692 debug("Device supports LBA48\n");
693 } else
694 debug("Device supports LBA28\n");
695#endif
696
697 /* Serial number */
698 ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial));
699 memcpy(sata_dev_desc[dev].product, serial, sizeof(serial));
700
701 /* Firmware version */
702 ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware));
703 memcpy(sata_dev_desc[dev].revision, firmware, sizeof(firmware));
704
705 /* Product model */
706 ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
707 memcpy(sata_dev_desc[dev].vendor, product, sizeof(product));
708
709 /* Totoal sectors */
710 sata_dev_desc[dev].lba = ata_id_n_sectors(id);
711
712 sil_sata_init_wcache(dev, id);
713 sil_cmd_set_feature(dev);
714
715#ifdef DEBUG
716 sil_cmd_identify_device(dev, id);
717 ata_dump_id(id);
718#endif
719 free((void *)id);
720
721 return 0;
722}