| commit | d1d256e1635684615182aaf62b077233c3360f7e | [log] [tgz] |
|---|---|---|
| author | Bin Meng <bmeng.cn@gmail.com> | Tue Jun 15 13:45:57 2021 +0800 |
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | Wed Jun 16 16:20:13 2021 +0800 |
| tree | e1a797ad7a9495cfc391fc9930a636b241199428 | |
| parent | efbcd66af3c83b14efb72eb38f73cd4af8128208 [diff] |
riscv: andes_plic: Fix riscv_get_ipi() mask
Current logic in riscv_get_ipi() for Andes PLICSW does not look
correct. The mask to test IPI pending bits for a hart should be
left shifted by (8 * gd->arch.boot_hart), just the same as what
is done in riscv_send_ipi().
Fixes: 8b3e97badf97 ("riscv: add functions for reading the IPI status")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Tested-by: Rick Chen <rick@andestech.com>