| commit | 77ff61a5bb437b5b19c50d8791f14a3b917e882c | [log] [tgz] |
|---|---|---|
| author | Tom Rini <trini@konsulko.com> | Wed Feb 14 15:23:10 2024 -0500 |
| committer | Tom Rini <trini@konsulko.com> | Wed Feb 14 15:23:10 2024 -0500 |
| tree | ee0d8f7efd458c4246b41eb10a0d2fcdf8ffe86e | |
| parent | 37345abb97ef0dd9c50a03b2a72617612dcae585 [diff] | |
| parent | c2ad5fb616d4e8aa2ac00e224030589847731fbe [diff] |
Merge tag 'xilinx-for-v2024.04-rc3' of https://source.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2024.04-rc3 zynqmp: - Cover missing _SE chip variants to fix fpga programming versal: - Enable LTO for mini configurations versal-net: - Enable LTO for mini configurations - Fix GIC address to aligned with real silicon xilinx: - DTs cleanup and fixups - Enable HTTP boot - Add missing spl header to zynqmp.c