efikamx: remove drive strength function and roll its functionality into the DCD
Efika MX boards configure their DDR pad settings twice, one in the DCD generated
from imximage_*.cfg and again in init_drive_strength called before relocation.
Rather than doing this, roll the changes it makes into the DCD so DDR is set up
before a single line of code in U-Boot is run.
The settings are identical with this DCD block which is shorter (by 7 entries)
than the old one, and after the output of init_drive_strength since a lot of the
functionality in the existing DCD and init_drive_strength function was just
setting the POR defaults. This goes to explain some now-missing entries.
Several hundred rounds of mtest have been run to test the settings before and
after to confirm DDR is stable and no ill-effects have been found.
Signed-off-by: Matt Sealey <matt@genesi-usa.com>
Acked-by: Stefano Babic <sbabic@denx.de>
diff --git a/board/genesi/mx51_efikamx/efikamx.c b/board/genesi/mx51_efikamx/efikamx.c
index e88b2ed..12371c9 100644
--- a/board/genesi/mx51_efikamx/efikamx.c
+++ b/board/genesi/mx51_efikamx/efikamx.c
@@ -597,85 +597,8 @@
/*
* Board initialization
*/
-static void init_drive_strength(void)
-{
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_DDR_INPUT_CMOS);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEADDR, PAD_CTL_PKE_ENABLE);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPKS, PAD_CTL_PUE_KEEPER);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPUS, PAD_CTL_100K_PU);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_A1, PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A0, PAD_CTL_DRV_HIGH);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A1, PAD_CTL_DRV_HIGH);
- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_RAS,
- PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CAS,
- PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_PKE_ENABLE);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPKS, PAD_CTL_PUE_KEEPER);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR0, PAD_CTL_HYS_NONE);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR1, PAD_CTL_HYS_NONE);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR2, PAD_CTL_HYS_NONE);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR3, PAD_CTL_HYS_NONE);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B0, PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B1, PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B2, PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B4, PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPUS, PAD_CTL_100K_PU);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_INMODE1, PAD_CTL_DDR_INPUT_CMOS);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B0, PAD_CTL_DRV_MEDIUM);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B1, PAD_CTL_DRV_MEDIUM);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B2, PAD_CTL_DRV_MEDIUM);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B4, PAD_CTL_DRV_MEDIUM);
-
- /* Setting pad options */
- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDWE,
- PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
- PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE0,
- PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
- PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE1,
- PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
- PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCLK,
- PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
- PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS0,
- PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
- PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS1,
- PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
- PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS2,
- PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
- PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS3,
- PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
- PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS0,
- PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
- PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS1,
- PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
- PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM0,
- PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
- PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM1,
- PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
- PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM2,
- PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
- PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM3,
- PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
- PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
-}
-
int board_early_init_f(void)
{
- init_drive_strength();
-
setup_iomux_uart();
setup_iomux_spi();
setup_iomux_led();
diff --git a/board/genesi/mx51_efikamx/imximage_mx.cfg b/board/genesi/mx51_efikamx/imximage_mx.cfg
index 6fe0ff9..ea6b271 100644
--- a/board/genesi/mx51_efikamx/imximage_mx.cfg
+++ b/board/genesi/mx51_efikamx/imximage_mx.cfg
@@ -1,5 +1,7 @@
#
+# Copyright (C) 2009 Pegatron Corporation
# Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+# Copyright (C) 2009-2012 Genesi USA, Inc.
#
# BASED ON: imx51evk
#
@@ -43,30 +45,22 @@
# Address absolute address of the register
# value value to be stored in the register
-# Setting IOMUXC
-DATA 4 0x73fa88a0 0x000
-DATA 4 0x73fa850c 0x20c5
-DATA 4 0x73fa8510 0x20c5
-DATA 4 0x73fa883c 0x5
-DATA 4 0x73fa8848 0x5
-DATA 4 0x73fa84b8 0xe7
-DATA 4 0x73fa84bc 0x45
-DATA 4 0x73fa84c0 0x45
-DATA 4 0x73fa84c4 0x45
-DATA 4 0x73fa84c8 0x45
-DATA 4 0x73fa8820 0x0
-DATA 4 0x73fa84a4 0x5
-DATA 4 0x73fa84a8 0x5
-DATA 4 0x73fa84ac 0xe5
-DATA 4 0x73fa84b0 0xe5
-DATA 4 0x73fa84b4 0xe5
-DATA 4 0x73fa84cc 0xe5
-DATA 4 0x73fa84d0 0xe4
-
-DATA 4 0x73fa882c 0x4
-DATA 4 0x73fa88a4 0x4
-DATA 4 0x73fa88ac 0x4
-DATA 4 0x73fa88b8 0x4
+# DDR bus IOMUX PAD settings
+DATA 4 0x73fa850c 0x20c5 # SDODT1
+DATA 4 0x73fa8510 0x20c5 # SDODT0
+DATA 4 0x73fa84ac 0xc5 # SDWE
+DATA 4 0x73fa84b0 0xc5 # SDCKE0
+DATA 4 0x73fa84b4 0xc5 # SDCKE1
+DATA 4 0x73fa84cc 0xc5 # DRAM_CS0
+DATA 4 0x73fa84d0 0xc5 # DRAM_CS1
+DATA 4 0x73fa882c 0x2 # DRAM_B4
+DATA 4 0x73fa88a4 0x2 # DRAM_B0
+DATA 4 0x73fa88ac 0x2 # DRAM_B1
+DATA 4 0x73fa88b8 0x2 # DRAM_B2
+DATA 4 0x73fa84d4 0xc5 # DRAM_DQM0
+DATA 4 0x73fa84d8 0xc5 # DRAM_DQM1
+DATA 4 0x73fa84dc 0xc5 # DRAM_DQM2
+DATA 4 0x73fa84e0 0xc5 # DRAM_DQM3
# Setting DDR for micron
# 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model