| commit | 64eeb1585428b71e29022e22d1aae86b65b9e052 | [log] [tgz] |
|---|---|---|
| author | Marek Vasut <marex@denx.de> | Mon May 07 22:22:26 2018 +0200 |
| committer | Marek Vasut <marex@denx.de> | Wed Jul 25 00:13:32 2018 +0200 |
| tree | e81ae5caa33279729457ea7ab0e93ff6c7ef5417 | |
| parent | 42f4b83b52735d698bf3f3de2665bf6d42db9f1c [diff] |
ARM: dts: socfpga: Adjust NAND register layout on Arria10 Adjust the NAND register size on Arria10 to reflect reality. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org>