tree 9e4f87a13d4f6530ccbc3566aa6fdc1f57d0b578
parent 2b7721552a4cb4046a365a665fba3a3a848eb966
author Michael Walle <michael@walle.cc> 1588803117 +0200
committer Tom Rini <trini@konsulko.com> 1588863900 -0400

phy: atheros: add device tree bindings and config

Add support for configuring the CLK_25M pin as well as the RGMII I/O
voltage by the device tree.

By default the AT803x PHYs outputs the 25MHz clock of the XTAL input.
But this output can also be changed by software to other frequencies.
This commit introduces a generic way to configure this output.

Also the PHY supports different RGMII I/O voltages: 1.5V, 1.8V and 2.5V.
An internal LDO is able to provide 1.5V (default) and 1.8V. The 2.5V
option needs an external supply voltage. This commit adds support to
switch the internal LDO to 1.8V.

Signed-off-by: Michael Walle <michael@walle.cc>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>