diff --git a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
index 55ac73e..940ee58 100644
--- a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
+++ b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
@@ -41,6 +41,16 @@
 	struct rk3288_grf *grf;
 	struct rk3288_sgrf *sgrf;
 	struct rk3288_pmu *pmu;
+	bool is_veyron;
+};
+
+struct rk3288_sdram_params {
+	struct rk3288_sdram_channel ch[2];
+	struct rk3288_sdram_pctl_timing pctl_timing;
+	struct rk3288_sdram_phy_timing phy_timing;
+	struct rk3288_base_params base;
+	int num_channels;
+	struct regmap *map;
 };
 
 #ifdef CONFIG_SPL_BUILD
@@ -703,7 +713,7 @@
 
 	return 0;
 }
-#endif
+#endif /* CONFIG_SPL_BUILD */
 
 size_t sdram_size_mb(struct rk3288_pmu *pmu)
 {
@@ -779,18 +789,35 @@
 static int setup_sdram(struct udevice *dev)
 {
 	struct dram_info *priv = dev_get_priv(dev);
-	struct rk3288_sdram_params params;
+	struct rk3288_sdram_params *params = dev_get_platdata(dev);
+
+# ifdef CONFIG_ROCKCHIP_FAST_SPL
+	if (priv->is_veyron) {
+		int ret;
+
+		ret = veyron_init(priv);
+		if (ret)
+			return ret;
+	}
+# endif
+
+	return sdram_init(priv, params);
+}
+
+static int rk3288_dmc_ofdata_to_platdata(struct udevice *dev)
+{
+	struct rk3288_sdram_params *params = dev_get_platdata(dev);
 	const void *blob = gd->fdt_blob;
 	int node = dev->of_offset;
 	int i, ret;
 
-	params.num_channels = fdtdec_get_int(blob, node,
-					     "rockchip,num-channels", 1);
-	for (i = 0; i < params.num_channels; i++) {
+	params->num_channels = fdtdec_get_int(blob, node,
+					      "rockchip,num-channels", 1);
+	for (i = 0; i < params->num_channels; i++) {
 		ret = fdtdec_get_byte_array(blob, node,
 					    "rockchip,sdram-channel",
-					    (u8 *)&params.ch[i],
-					    sizeof(params.ch[i]));
+					    (u8 *)&params->ch[i],
+					    sizeof(params->ch[i]));
 		if (ret) {
 			debug("%s: Cannot read rockchip,sdram-channel\n",
 			      __func__);
@@ -798,41 +825,44 @@
 		}
 	}
 	ret = fdtdec_get_int_array(blob, node, "rockchip,pctl-timing",
-				   (u32 *)&params.pctl_timing,
-				   sizeof(params.pctl_timing) / sizeof(u32));
+				   (u32 *)&params->pctl_timing,
+				   sizeof(params->pctl_timing) / sizeof(u32));
 	if (ret) {
 		debug("%s: Cannot read rockchip,pctl-timing\n", __func__);
 		return -EINVAL;
 	}
 	ret = fdtdec_get_int_array(blob, node, "rockchip,phy-timing",
-				   (u32 *)&params.phy_timing,
-				   sizeof(params.phy_timing) / sizeof(u32));
+				   (u32 *)&params->phy_timing,
+				   sizeof(params->phy_timing) / sizeof(u32));
 	if (ret) {
 		debug("%s: Cannot read rockchip,phy-timing\n", __func__);
 		return -EINVAL;
 	}
 	ret = fdtdec_get_int_array(blob, node, "rockchip,sdram-params",
-				   (u32 *)&params.base,
-				   sizeof(params.base) / sizeof(u32));
+				   (u32 *)&params->base,
+				   sizeof(params->base) / sizeof(u32));
 	if (ret) {
 		debug("%s: Cannot read rockchip,sdram-params\n", __func__);
 		return -EINVAL;
 	}
+#ifdef CONFIG_ROCKCHIP_FAST_SPL
+	struct dram_info *priv = dev_get_priv(dev);
 
-# ifdef CONFIG_ROCKCHIP_FAST_SPL
-	if (!fdt_node_check_compatible(blob, 0, "google,veyron")) {
-		ret = veyron_init(priv);
-		if (ret)
-			return ret;
-	}
-# endif
-
-	return sdram_init(priv, &params);
-}
+	priv->is_veyron = !fdt_node_check_compatible(blob, 0, "google,veyron");
 #endif
+	ret = regmap_init_mem(dev, &params->map);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+#endif /* CONFIG_SPL_BUILD */
 
 static int rk3288_dmc_probe(struct udevice *dev)
 {
+#ifdef CONFIG_SPL_BUILD
+	struct rk3288_sdram_params *plat = dev_get_platdata(dev);
+#endif
 	struct dram_info *priv = dev_get_priv(dev);
 	struct regmap *map;
 	int ret;
@@ -849,14 +879,12 @@
 	priv->sgrf = syscon_get_first_range(ROCKCHIP_SYSCON_SGRF);
 	priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU);
 
-	ret = regmap_init_mem(dev, &map);
-	if (ret)
-		return ret;
-	priv->chan[0].pctl = regmap_get_range(map, 0);
-	priv->chan[0].publ = regmap_get_range(map, 1);
-	priv->chan[1].pctl = regmap_get_range(map, 2);
-	priv->chan[1].publ = regmap_get_range(map, 3);
-
+#ifdef CONFIG_SPL_BUILD
+	priv->chan[0].pctl = regmap_get_range(plat->map, 0);
+	priv->chan[0].publ = regmap_get_range(plat->map, 1);
+	priv->chan[1].pctl = regmap_get_range(plat->map, 2);
+	priv->chan[1].publ = regmap_get_range(plat->map, 3);
+#endif
 	ret = uclass_get_device(UCLASS_CLK, 0, &dev_clk);
 	if (ret)
 		return ret;
@@ -902,6 +930,12 @@
 	.id = UCLASS_RAM,
 	.of_match = rk3288_dmc_ids,
 	.ops = &rk3288_dmc_ops,
+#ifdef CONFIG_SPL_BUILD
+	.ofdata_to_platdata = rk3288_dmc_ofdata_to_platdata,
+#endif
 	.probe = rk3288_dmc_probe,
 	.priv_auto_alloc_size = sizeof(struct dram_info),
+#ifdef CONFIG_SPL_BUILD
+	.platdata_auto_alloc_size = sizeof(struct rk3288_sdram_params),
+#endif
 };