| commit | faa75ad9e6de20776e4629a2eb71c372b9fcfa7d | [log] [tgz] |
|---|---|---|
| author | Kever Yang <kever.yang@rock-chips.com> | Thu Nov 30 16:51:19 2017 +0800 |
| committer | Philipp Tomsich <philipp.tomsich@theobroma-systems.com> | Thu Nov 30 22:55:27 2017 +0100 |
| tree | 049a59419c5b3071168505cb745ce228290e655b | |
| parent | f9cf8cbb9e23952c5585ab3a548af3599a925578 [diff] |
rockchip: rk3036: fix pll config for correct frequency There is a fixed div-2 between PLL and clk_ddr/clk_ddrphy, so we need to double to pll output and then ddr can work in correct frequency. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>