commit f9932d38a326e18113cc2daf8449c332e46c97a6
author Tom Rini <trini@konsulko.com> Sun Dec 04 10:13:41 2022 -0500
committer Tom Rini <trini@konsulko.com> Fri Dec 23 10:15:11 2022 -0500
tree e48f4024021a99e9f9b5b9768aacba150e2ea197
parent 3db78c830fda7cac7ef1a9b739f1a603bcfb58be

global: Migrate CONFIG_SAR2_REG to CFG

Perform a simple rename of CONFIG_SAR2_REG to CFG_SAR2_REG

Signed-off-by: Tom Rini <trini@konsulko.com>

arch/arm/mach-mvebu/cpu.c

diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c
index 67ad5e5..9139df1 100644
--- a/arch/arm/mach-mvebu/cpu.c
+++ b/arch/arm/mach-mvebu/cpu.c
@@ -195,7 +195,7 @@
 	int i;
 
 #if defined(CONFIG_ARMADA_375) || defined(CONFIG_ARMADA_MSYS)
-	val = readl(CONFIG_SAR2_REG);	/* SAR - Sample At Reset */
+	val = readl(CFG_SAR2_REG);	/* SAR - Sample At Reset */
 #else
 	val = readl(CONFIG_SAR_REG);	/* SAR - Sample At Reset */
 #endif
@@ -205,7 +205,7 @@
 	 * Shift CPU0 clock frequency select bit from SAR2 register
 	 * into correct position
 	 */
-	freq |= ((readl(CONFIG_SAR2_REG) & SAR2_CPU_FREQ_MASK)
+	freq |= ((readl(CFG_SAR2_REG) & SAR2_CPU_FREQ_MASK)
 		 >> SAR2_CPU_FREQ_OFFS) << 3;
 #endif
 	for (i = 0; sar_freq_tab[i].val != 0xff; i++) {

arch/arm/mach-mvebu/include/mach/soc.h

diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h
index e6383d4..1210d26 100644
--- a/arch/arm/mach-mvebu/include/mach/soc.h
+++ b/arch/arm/mach-mvebu/include/mach/soc.h
@@ -135,7 +135,7 @@
 #if defined(CONFIG_ARMADA_375)
 /* SAR values for Armada 375 */
 #define CONFIG_SAR_REG		(MVEBU_REGISTER(0xe8200))
-#define CONFIG_SAR2_REG		(MVEBU_REGISTER(0xe8204))
+#define CFG_SAR2_REG		(MVEBU_REGISTER(0xe8204))
 
 #define SAR_CPU_FREQ_OFFS	17
 #define SAR_CPU_FREQ_MASK	(0x1f << SAR_CPU_FREQ_OFFS)
@@ -174,7 +174,7 @@
 #elif defined(CONFIG_ARMADA_MSYS)
 /* SAR values for MSYS */
 #define CONFIG_SAR_REG		(MBUS_DFX_BASE  + 0xf8200)
-#define CONFIG_SAR2_REG		(MBUS_DFX_BASE  + 0xf8204)
+#define CFG_SAR2_REG		(MBUS_DFX_BASE  + 0xf8204)
 
 #define SAR_CPU_FREQ_OFFS	18
 #define SAR_CPU_FREQ_MASK	(0x7 << SAR_CPU_FREQ_OFFS)
@@ -192,7 +192,7 @@
 #elif defined(CONFIG_ARMADA_XP)
 /* SAR values for Armada XP */
 #define CONFIG_SAR_REG		(MVEBU_REGISTER(0x18230))
-#define CONFIG_SAR2_REG		(MVEBU_REGISTER(0x18234))
+#define CFG_SAR2_REG		(MVEBU_REGISTER(0x18234))
 
 #define SAR_CPU_FREQ_OFFS	21
 #define SAR_CPU_FREQ_MASK	(0x7 << SAR_CPU_FREQ_OFFS)