crypto/fsl: SEC driver cleanup for 64 bit and endianness
The SEC driver code has been cleaned up to work for 64 bit
physical addresses and systems where endianess of SEC block
is different from the Core.
Changes:
1. Descriptor created on Core is modified as per SEC block
endianness before the job is submitted.
2. The read/write of physical addresses to Job Rings will
be depend on endianness of SEC block as 32 bit low and
high part of the 64 bit address will vary.
3. The 32 bit low and high part of the 64 bit address in
descriptor will vary depending on endianness of SEC.
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
diff --git a/drivers/crypto/fsl/jr.h b/drivers/crypto/fsl/jr.h
index 1526060..5899696 100644
--- a/drivers/crypto/fsl/jr.h
+++ b/drivers/crypto/fsl/jr.h
@@ -37,14 +37,13 @@
#define JQ_ENQ_ERR -3
struct op_ring {
- dma_addr_t desc;
+ phys_addr_t desc;
uint32_t status;
} __packed;
struct jr_info {
- void (*callback)(dma_addr_t desc, uint32_t status, void *arg);
- dma_addr_t desc_phys_addr;
- uint32_t desc_addr;
+ void (*callback)(uint32_t status, void *arg);
+ phys_addr_t desc_phys_addr;
uint32_t desc_len;
uint32_t op_done;
void *arg;