commit f404b66ce118343b77ae58f78cccd6381b329dd1
author York Sun <york.sun@nxp.com> Thu Nov 17 13:53:33 2016 -0800
committer York Sun <york.sun@nxp.com> Wed Nov 23 23:42:08 2016 -0800
tree 4f18f40b061b23ff13e1cb1a2a1ff697daac18d3
parent aa14620c2ef46d6e3094a20189d819a05de67cd0

powerpc: P1020RDB-PD: Separate from P1_P2_RDB_PC in Kconfig

Use TARGET_P1020RDB_PD instead of sharing with P1_P2_RDB_PC
to simplify Kconfig and config macros.

Remove macro CONFIG_P1020RDB_PD.

Signed-off-by: York Sun <york.sun@nxp.com>

include/configs/p1_p2_rdb_pc.h

diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index edb5395..010a9ed 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -58,7 +58,7 @@
  * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off
  * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off
  */
-#if defined(CONFIG_P1020RDB_PD)
+#if defined(CONFIG_TARGET_P1020RDB_PD)
 #define CONFIG_BOARDNAME "P1020RDB-PD"
 #define CONFIG_NAND_FSL_ELBC
 #define CONFIG_P1020
@@ -336,7 +336,7 @@
 #define SPD_EEPROM_ADDRESS 0x52
 #undef CONFIG_FSL_DDR_INTERACTIVE
 
-#if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_P1020RDB_PD))
+#if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
 #define CONFIG_SYS_SDRAM_SIZE_LAW	LAW_SIZE_2G
 #define CONFIG_CHIP_SELECTS_PER_CTRL	2
 #else
@@ -406,7 +406,7 @@
 /*
  * Local Bus Definitions
  */
-#if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_P1020RDB_PD))
+#if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
 #define CONFIG_SYS_MAX_FLASH_SECT	512	/* 64M */
 #define CONFIG_SYS_FLASH_BASE		0xec000000
 #elif defined(CONFIG_P1020UTM)
@@ -455,7 +455,7 @@
 #define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
 #define CONFIG_CMD_NAND
-#if defined(CONFIG_P1020RDB_PD)
+#if defined(CONFIG_TARGET_P1020RDB_PD)
 #define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
 #else
 #define CONFIG_SYS_NAND_BLOCK_SIZE	(16 * 1024)
@@ -466,7 +466,7 @@
 	| BR_PS_8	/* Port Size = 8 bit */ \
 	| BR_MS_FCM	/* MSEL = FCM */ \
 	| BR_V)	/* valid */
-#if defined(CONFIG_P1020RDB_PD)
+#if defined(CONFIG_TARGET_P1020RDB_PD)
 #define CONFIG_SYS_NAND_OR_PRELIM	(OR_AM_32KB \
 	| OR_FCM_PGS	/* Large Page*/ \
 	| OR_FCM_CSCT \
@@ -853,7 +853,7 @@
 #endif
 #endif
 
-#if defined(CONFIG_P1020RDB_PD)
+#if defined(CONFIG_TARGET_P1020RDB_PD)
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	1
 #endif