8548cds PCIE support.
Make the early L1 cache stack region guarded to prevent speculative
fetches outside the locked range.
Use _PHYS defines, not _MEM for cpu-side PCI memory mapped regions.
init.S whitespace cleanup.
Allow TEXT_BASE value to be specified on command line. This allows it
to be set to 0xfffc0000 which cuts the uboot binary in half.
Clear and enable lbc and ecm errors.
Update last_busno in device-tree for pci and pcie.
Remove load of obsolete cpu/mpc85xx/pci.0
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
diff --git a/board/cds/mpc8548cds/init.S b/board/cds/mpc8548cds/init.S
index d468f5b..72940b0 100644
--- a/board/cds/mpc8548cds/init.S
+++ b/board/cds/mpc8548cds/init.S
@@ -1,5 +1,5 @@
/*
- * Copyright 2004 Freescale Semiconductor.
+ * Copyright 2004, 2007 Freescale Semiconductor.
* Copyright 2002,2003, Motorola Inc.
*
* See file CREDITS for list of people who contributed to this
@@ -28,6 +28,12 @@
#include <config.h>
#include <mpc85xx.h>
+#define LAWAR_TRGT_PCI1 0x00000000
+#define LAWAR_TRGT_PCI2 0x00100000
+#define LAWAR_TRGT_PCIE 0x00200000
+#define LAWAR_TRGT_RIO 0x00c00000
+#define LAWAR_TRGT_LBC 0x00400000
+#define LAWAR_TRGT_DDR 0x00f00000
/*
* TLB0 and TLB1 Entries
@@ -47,8 +53,8 @@
*/
#define entry_start \
- mflr r1 ; \
- bl 0f ;
+ mflr r1 ; \
+ bl 0f ;
#define entry_end \
0: mflr r0 ; \
@@ -84,8 +90,8 @@
#endif
/*
- * TLB0 16K Cacheable, non-guarded
- * 0xd001_0000 16K Temporary Global data for initialization
+ * TLB0 16K Cacheable, guarded
+ * Temporary Global data for initialization
*
* Use four 4K TLB0 entries. These entries must be cacheable
* as they provide the bootstrap memory before the memory
@@ -97,28 +103,28 @@
.long TLB1_MAS0(0, 0, 0)
.long TLB1_MAS1(1, 0, 0, 0, 0)
.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
- 0,0,0,0,0,0,0,0)
+ 0,0,0,0,0,0,1,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(0, 0, 0)
.long TLB1_MAS1(1, 0, 0, 0, 0)
.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
- 0,0,0,0,0,0,0,0)
+ 0,0,0,0,0,0,1,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(0, 0, 0)
.long TLB1_MAS1(1, 0, 0, 0, 0)
.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
- 0,0,0,0,0,0,0,0)
+ 0,0,0,0,0,0,1,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(0, 0, 0)
.long TLB1_MAS1(1, 0, 0, 0, 0)
.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
- 0,0,0,0,0,0,0,0)
+ 0,0,0,0,0,0,1,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
0,0,0,0,0,1,0,1,0,1)
@@ -130,51 +136,44 @@
*/
.long TLB1_MAS0(1, 0, 0)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_BOOT_BLOCK), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_BOOT_BLOCK), 0,0,0,0,0,1,0,1,0,1)
/*
- * TLB 1: 256M Non-cacheable, guarded
- * 0x80000000 256M PCI1 MEM
+ * TLB 1: 1G Non-cacheable, guarded
+ * 0x80000000 1G PCI1/PCIE 8,9,a,b
*/
.long TLB1_MAS0(1, 1, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI_PHYS), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI_PHYS), 0,0,0,0,0,1,0,1,0,1)
+#ifdef CFG_RIO_MEM_PHYS
/*
* TLB 2: 256M Non-cacheable, guarded
- * 0x90000000 256M PCI2 MEM
*/
.long TLB1_MAS0(1, 2, 0)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE),
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_PHYS),
0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE),
- 0,0,0,0,0,1,0,1,0,1)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_PHYS), 0,0,0,0,0,1,0,1,0,1)
/*
- * TLB 3: 1GB Non-cacheable, guarded
- * 0xa0000000 256M PEX MEM First half
- * 0xb0000000 256M PEX MEM Second half
- * 0xc0000000 256M Rapid IO MEM First half
- * 0xd0000000 256M Rapid IO MEM Second half
+ * TLB 3: 256M Non-cacheable, guarded
*/
.long TLB1_MAS0(1, 3, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_PEX_MEM_BASE), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_PEX_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
-
- /*
- * TLB 4: Reserved for future usage
- */
-
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_PHYS + 0x10000000),
+ 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_PHYS + 0x10000000),
+ 0,0,0,0,0,1,0,1,0,1)
+#endif
/*
* TLB 5: 64M Non-cacheable, guarded
* 0xe000_0000 1M CCSRBAR
- * 0xe200_0000 8M PCI1 IO
- * 0xe280_0000 8M PCI2 IO
- * 0xe300_0000 16M PEX IO
+ * 0xe200_0000 1M PCI1 IO
+ * 0xe210_0000 1M PCI2 IO
+ * 0xe300_0000 1M PCIe IO
*/
.long TLB1_MAS0(1, 5, 0)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
@@ -187,17 +186,18 @@
*/
.long TLB1_MAS0(1, 6, 0)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_CACHE_BASE), 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_CACHE_BASE), 0,0,0,0,0,1,0,1,0,1)
/*
- * TLB 7: 1M Non-cacheable, guarded
- * 0xf8000000 1M CADMUS registers
+ * TLB 7: 64M Non-cacheable, guarded
+ * 0xf8000000 64M CADMUS registers, relocated L2SRAM
*/
.long TLB1_MAS0(1, 7, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)
- .long TLB1_MAS2(E500_TLB_EPN(CADMUS_BASE_ADDR), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CADMUS_BASE_ADDR), 0,0,0,0,0,1,0,1,0,1)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_NONCACHE_BASE), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_NONCACHE_BASE), 0,0,0,0,0,1,0,1,0,1)
+
2:
entry_end
@@ -205,14 +205,13 @@
* LAW(Local Access Window) configuration:
*
* 0x0000_0000 0x7fff_ffff DDR 2G
- * 0x8000_0000 0x8fff_ffff PCI1 MEM 256M
- * 0x9000_0000 0x9fff_ffff PCI2 MEM 256M
- * 0xa000_0000 0xbfff_ffff PEX MEM 512M
+ * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
+ * 0xa000_0000 0xbfff_ffff PCIe MEM 512M
* 0xc000_0000 0xdfff_ffff RapidIO 512M
* 0xe000_0000 0xe000_ffff CCSR 1M
- * 0xe200_0000 0xe27f_ffff PCI1 IO 8M
- * 0xe280_0000 0xe2ff_ffff PCI2 IO 8M
- * 0xe300_0000 0xe3ff_ffff PEX IO 16M
+ * 0xe200_0000 0xe10f_ffff PCI1 IO 1M
+ * 0xe280_0000 0xe20f_ffff PCI2 IO 1M
+ * 0xe300_0000 0xe30f_ffff PCIe IO 1M
* 0xf000_0000 0xf3ff_ffff SDRAM 64M
* 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M
* 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M
@@ -222,47 +221,50 @@
* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
* If flash is 8M at default position (last 8M), no LAW needed.
*
- * The defines below are 1-off of the actual LAWAR0 usage.
- * So LAWAR3 define uses the LAWAR4 register in the ECM.
+ * LAW 0 is reserved for boot mapping
*/
-#define LAWBAR0 0
-#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
-
-#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
-#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_256M))
-
-#define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff)
-#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_256M))
-
-#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff)
-#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_8M))
-
-#define LAWBAR4 ((CFG_PCI2_IO_PHYS>>12) & 0xfffff)
-#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_8M))
-
-/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
-#define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
-#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
-
-#define LAWBAR6 ((CFG_PEX_MEM_BASE>>12) & 0xfffff)
-#define LAWAR6 (LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_512M))
-
-#define LAWBAR7 ((CFG_PEX_IO_PHYS>>12) & 0xfffff)
-#define LAWAR7 (LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_16M))
-
-#define LAWBAR8 ((CFG_RIO_MEM_BASE>>12) & 0xfffff)
-#define LAWAR8 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
-
.section .bootpg, "ax"
.globl law_entry
-
law_entry:
entry_start
+
.long (4f-3f)/8
3:
- .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
- .long LAWBAR4,LAWAR4,LAWBAR5,LAWAR5,LAWBAR6,LAWAR6,LAWBAR7,LAWAR7
- .long LAWBAR8,LAWAR8
+ .long 0
+ .long (LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN
+
+#ifdef CFG_PCI1_MEM_PHYS
+ .long (CFG_PCI1_MEM_PHYS>>12) & 0xfffff
+ .long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)
+
+ .long (CFG_PCI1_IO_PHYS>>12) & 0xfffff
+ .long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M)
+#endif
+
+#ifdef CFG_PCI2_MEM_PHYS
+ .long (CFG_PCI2_MEM_PHYS>>12) & 0xfffff
+ .long LAWAR_EN | LAWAR_TRGT_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)
+
+ .long (CFG_PCI2_IO_PHYS>>12) & 0xfffff
+ .long LAWAR_EN | LAWAR_TRGT_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M)
+#endif
+
+#ifdef CFG_PCIE1_MEM_PHYS
+ .long (CFG_PCIE1_MEM_PHYS>>12) & 0xfffff
+ .long LAWAR_EN | LAWAR_TRGT_PCIE | (LAWAR_SIZE & LAWAR_SIZE_512M)
+
+ .long (CFG_PCIE1_IO_PHYS>>12) & 0xfffff
+ .long LAWAR_EN | LAWAR_TRGT_PCIE | (LAWAR_SIZE & LAWAR_SIZE_1M)
+#endif
+
+ /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
+ .long (CFG_LBC_CACHE_BASE>>12) & 0xfffff
+ .long LAWAR_EN | LAWAR_TRGT_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)
+
+#ifdef CFG_RIO_MEM_PHYS
+ .long (CFG_RIO_MEM_PHYS>>12) & 0xfffff
+ .long LAWAR_EN | LAWAR_TRGT_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)
+#endif
4:
entry_end