dm: x86: spi: Convert ICH SPI driver to driver model PCI API
At present this SPI driver works by searching the PCI buses for its
peripheral. It also uses the legacy PCI API.
In addition the driver has code to determine the type of Intel PCH that is
used (version 7 or version 9). Now that we have proper PCH drivers we can
use those to obtain the information we need.
While the device tree has a node for the SPI peripheral it is not in the
right place. It should be on the PCI bus as a sub-peripheral of the LPC
device.
Update the device tree files to show the SPI controller within the PCH, so
that PCI access works as expected.
This patch includes Bin's fix-up patch from here:
https://patchwork.ozlabs.org/patch/569478/
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
diff --git a/arch/x86/cpu/coreboot/pci.c b/arch/x86/cpu/coreboot/pci.c
index 41e29a6..7f5087a 100644
--- a/arch/x86/cpu/coreboot/pci.c
+++ b/arch/x86/cpu/coreboot/pci.c
@@ -14,7 +14,8 @@
#include <pci.h>
static const struct udevice_id generic_pch_ids[] = {
- { .compatible = "intel,pch" },
+ { .compatible = "intel,pch7" },
+ { .compatible = "intel,pch9" },
{ }
};
diff --git a/arch/x86/cpu/irq.c b/arch/x86/cpu/irq.c
index 35b29f6..205405b 100644
--- a/arch/x86/cpu/irq.c
+++ b/arch/x86/cpu/irq.c
@@ -97,6 +97,7 @@
struct irq_routing_table *rt;
struct irq_info *slot, *slot_base;
int irq_entries = 0;
+ int parent;
int i;
int ret;
@@ -106,7 +107,11 @@
return -EINVAL;
}
- ret = fdtdec_get_pci_addr(blob, node, FDT_PCI_SPACE_CONFIG,
+ /* TODO(sjg@chromium.org): Drop this when PIRQ is a driver */
+ parent = fdt_parent_offset(blob, node);
+ if (parent < 0)
+ return -EINVAL;
+ ret = fdtdec_get_pci_addr(blob, parent, FDT_PCI_SPACE_CONFIG,
"reg", &addr);
if (ret)
return ret;
diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c
index 434dfd6..c000aca 100644
--- a/arch/x86/cpu/ivybridge/bd82x6x.c
+++ b/arch/x86/cpu/ivybridge/bd82x6x.c
@@ -3,12 +3,12 @@
*
* SPDX-License-Identifier: GPL-2.0+
*/
-
#include <common.h>
#include <dm.h>
#include <errno.h>
#include <fdtdec.h>
#include <malloc.h>
+#include <pch.h>
#include <asm/lapic.h>
#include <asm/pci.h>
#include <asm/arch/bd82x6x.h>
@@ -16,6 +16,8 @@
#include <asm/arch/pch.h>
#include <asm/arch/sandybridge.h>
+#define BIOS_CTRL 0xdc
+
void bd82x6x_pci_init(pci_dev_t dev)
{
u16 reg16;
@@ -96,6 +98,7 @@
return 0;
}
+/* TODO(sjg@chromium.org): Move this to the PCH init() method */
int bd82x6x_init(void)
{
const void *blob = gd->fdt_blob;
@@ -116,6 +119,47 @@
return 0;
}
+static int bd82x6x_pch_get_sbase(struct udevice *dev, ulong *sbasep)
+{
+ u32 rcba;
+
+ dm_pci_read_config32(dev, PCH_RCBA, &rcba);
+ /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable */
+ rcba = rcba & 0xffffc000;
+ *sbasep = rcba + 0x3800;
+
+ return 0;
+}
+
+static enum pch_version bd82x6x_pch_get_version(struct udevice *dev)
+{
+ return PCHV_9;
+}
+
+static int bd82x6x_set_spi_protect(struct udevice *dev, bool protect)
+{
+ uint8_t bios_cntl;
+
+ /* Adjust the BIOS write protect and SMM BIOS Write Protect Disable */
+ dm_pci_read_config8(dev, BIOS_CTRL, &bios_cntl);
+ if (protect) {
+ bios_cntl &= ~BIOS_CTRL_BIOSWE;
+ bios_cntl |= BIT(5);
+ } else {
+ bios_cntl |= BIOS_CTRL_BIOSWE;
+ bios_cntl &= ~BIT(5);
+ }
+ dm_pci_write_config8(dev, BIOS_CTRL, bios_cntl);
+
+ return 0;
+}
+
+static const struct pch_ops bd82x6x_pch_ops = {
+ .get_sbase = bd82x6x_pch_get_sbase,
+ .get_version = bd82x6x_pch_get_version,
+ .set_spi_protect = bd82x6x_set_spi_protect,
+};
+
static const struct udevice_id bd82x6x_ids[] = {
{ .compatible = "intel,bd82x6x" },
{ }
@@ -126,4 +170,5 @@
.id = UCLASS_PCH,
.of_match = bd82x6x_ids,
.probe = bd82x6x_probe,
+ .ops = &bd82x6x_pch_ops,
};
diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts
index d3380de..9bf707b 100644
--- a/arch/x86/dts/bayleybay.dts
+++ b/arch/x86/dts/bayleybay.dts
@@ -65,23 +65,6 @@
};
};
- spi {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "intel,ich-spi";
- spi-flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0>;
- compatible = "winbond,w25q64dw", "spi-flash";
- memory-map = <0xff800000 0x00800000>;
- rw-mrc-cache {
- label = "rw-mrc-cache";
- reg = <0x006e0000 0x00010000>;
- };
- };
- };
-
gpioa {
compatible = "intel,ich6-gpio";
u-boot,dm-pre-reloc;
@@ -133,66 +116,91 @@
0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
0x01000000 0x0 0x2000 0x2000 0 0xe000>;
- irq-router@1f,0 {
+ pch@1f,0 {
reg = <0x0000f800 0 0 0 0>;
- compatible = "intel,irq-router";
- intel,pirq-config = "ibase";
- intel,ibase-offset = <0x50>;
- intel,pirq-link = <8 8>;
- intel,pirq-mask = <0xdee0>;
- intel,pirq-routing = <
- /* BayTrail PCI devices */
- PCI_BDF(0, 2, 0) INTA PIRQA
- PCI_BDF(0, 3, 0) INTA PIRQA
- PCI_BDF(0, 16, 0) INTA PIRQA
- PCI_BDF(0, 17, 0) INTA PIRQA
- PCI_BDF(0, 18, 0) INTA PIRQA
- PCI_BDF(0, 19, 0) INTA PIRQA
- PCI_BDF(0, 20, 0) INTA PIRQA
- PCI_BDF(0, 21, 0) INTA PIRQA
- PCI_BDF(0, 22, 0) INTA PIRQA
- PCI_BDF(0, 23, 0) INTA PIRQA
- PCI_BDF(0, 24, 0) INTA PIRQA
- PCI_BDF(0, 24, 1) INTC PIRQC
- PCI_BDF(0, 24, 2) INTD PIRQD
- PCI_BDF(0, 24, 3) INTB PIRQB
- PCI_BDF(0, 24, 4) INTA PIRQA
- PCI_BDF(0, 24, 5) INTC PIRQC
- PCI_BDF(0, 24, 6) INTD PIRQD
- PCI_BDF(0, 24, 7) INTB PIRQB
- PCI_BDF(0, 26, 0) INTA PIRQA
- PCI_BDF(0, 27, 0) INTA PIRQA
- PCI_BDF(0, 28, 0) INTA PIRQA
- PCI_BDF(0, 28, 1) INTB PIRQB
- PCI_BDF(0, 28, 2) INTC PIRQC
- PCI_BDF(0, 28, 3) INTD PIRQD
- PCI_BDF(0, 29, 0) INTA PIRQA
- PCI_BDF(0, 30, 0) INTA PIRQA
- PCI_BDF(0, 30, 1) INTD PIRQD
- PCI_BDF(0, 30, 2) INTB PIRQB
- PCI_BDF(0, 30, 3) INTC PIRQC
- PCI_BDF(0, 30, 4) INTD PIRQD
- PCI_BDF(0, 30, 5) INTB PIRQB
- PCI_BDF(0, 31, 3) INTB PIRQB
+ compatible = "intel,pch9";
- /* PCIe root ports downstream interrupts */
- PCI_BDF(1, 0, 0) INTA PIRQA
- PCI_BDF(1, 0, 0) INTB PIRQB
- PCI_BDF(1, 0, 0) INTC PIRQC
- PCI_BDF(1, 0, 0) INTD PIRQD
- PCI_BDF(2, 0, 0) INTA PIRQB
- PCI_BDF(2, 0, 0) INTB PIRQC
- PCI_BDF(2, 0, 0) INTC PIRQD
- PCI_BDF(2, 0, 0) INTD PIRQA
- PCI_BDF(3, 0, 0) INTA PIRQC
- PCI_BDF(3, 0, 0) INTB PIRQD
- PCI_BDF(3, 0, 0) INTC PIRQA
- PCI_BDF(3, 0, 0) INTD PIRQB
- PCI_BDF(4, 0, 0) INTA PIRQD
- PCI_BDF(4, 0, 0) INTB PIRQA
- PCI_BDF(4, 0, 0) INTC PIRQB
- PCI_BDF(4, 0, 0) INTD PIRQC
- >;
+ irq-router {
+ compatible = "intel,irq-router";
+ intel,pirq-config = "ibase";
+ intel,ibase-offset = <0x50>;
+ intel,pirq-link = <8 8>;
+ intel,pirq-mask = <0xdee0>;
+ intel,pirq-routing = <
+ /* BayTrail PCI devices */
+ PCI_BDF(0, 2, 0) INTA PIRQA
+ PCI_BDF(0, 3, 0) INTA PIRQA
+ PCI_BDF(0, 16, 0) INTA PIRQA
+ PCI_BDF(0, 17, 0) INTA PIRQA
+ PCI_BDF(0, 18, 0) INTA PIRQA
+ PCI_BDF(0, 19, 0) INTA PIRQA
+ PCI_BDF(0, 20, 0) INTA PIRQA
+ PCI_BDF(0, 21, 0) INTA PIRQA
+ PCI_BDF(0, 22, 0) INTA PIRQA
+ PCI_BDF(0, 23, 0) INTA PIRQA
+ PCI_BDF(0, 24, 0) INTA PIRQA
+ PCI_BDF(0, 24, 1) INTC PIRQC
+ PCI_BDF(0, 24, 2) INTD PIRQD
+ PCI_BDF(0, 24, 3) INTB PIRQB
+ PCI_BDF(0, 24, 4) INTA PIRQA
+ PCI_BDF(0, 24, 5) INTC PIRQC
+ PCI_BDF(0, 24, 6) INTD PIRQD
+ PCI_BDF(0, 24, 7) INTB PIRQB
+ PCI_BDF(0, 26, 0) INTA PIRQA
+ PCI_BDF(0, 27, 0) INTA PIRQA
+ PCI_BDF(0, 28, 0) INTA PIRQA
+ PCI_BDF(0, 28, 1) INTB PIRQB
+ PCI_BDF(0, 28, 2) INTC PIRQC
+ PCI_BDF(0, 28, 3) INTD PIRQD
+ PCI_BDF(0, 29, 0) INTA PIRQA
+ PCI_BDF(0, 30, 0) INTA PIRQA
+ PCI_BDF(0, 30, 1) INTD PIRQD
+ PCI_BDF(0, 30, 2) INTB PIRQB
+ PCI_BDF(0, 30, 3) INTC PIRQC
+ PCI_BDF(0, 30, 4) INTD PIRQD
+ PCI_BDF(0, 30, 5) INTB PIRQB
+ PCI_BDF(0, 31, 3) INTB PIRQB
+
+ /*
+ * PCIe root ports downstream
+ * interrupts
+ */
+ PCI_BDF(1, 0, 0) INTA PIRQA
+ PCI_BDF(1, 0, 0) INTB PIRQB
+ PCI_BDF(1, 0, 0) INTC PIRQC
+ PCI_BDF(1, 0, 0) INTD PIRQD
+ PCI_BDF(2, 0, 0) INTA PIRQB
+ PCI_BDF(2, 0, 0) INTB PIRQC
+ PCI_BDF(2, 0, 0) INTC PIRQD
+ PCI_BDF(2, 0, 0) INTD PIRQA
+ PCI_BDF(3, 0, 0) INTA PIRQC
+ PCI_BDF(3, 0, 0) INTB PIRQD
+ PCI_BDF(3, 0, 0) INTC PIRQA
+ PCI_BDF(3, 0, 0) INTD PIRQB
+ PCI_BDF(4, 0, 0) INTA PIRQD
+ PCI_BDF(4, 0, 0) INTB PIRQA
+ PCI_BDF(4, 0, 0) INTC PIRQB
+ PCI_BDF(4, 0, 0) INTD PIRQC
+ >;
+ };
+
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "intel,ich-spi";
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>;
+ compatible = "winbond,w25q64dw",
+ "spi-flash";
+ memory-map = <0xff800000 0x00800000>;
+ rw-mrc-cache {
+ label = "rw-mrc-cache";
+ reg = <0x006e0000 0x00010000>;
+ };
+ };
+ };
};
};
diff --git a/arch/x86/dts/broadwell_som-6896.dts b/arch/x86/dts/broadwell_som-6896.dts
index 194f0eb..4e9e410 100644
--- a/arch/x86/dts/broadwell_som-6896.dts
+++ b/arch/x86/dts/broadwell_som-6896.dts
@@ -29,16 +29,22 @@
ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000
0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
0x01000000 0x0 0x2000 0x2000 0 0xe000>;
- };
- spi {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "intel,ich-spi";
- spi-flash@0 {
- reg = <0>;
- compatible = "winbond,w25q128", "spi-flash";
- memory-map = <0xff000000 0x01000000>;
+ pch@1f,0 {
+ reg = <0x0000f800 0 0 0 0>;
+ compatible = "intel,pch9";
+
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "intel,ich-spi";
+ spi-flash@0 {
+ reg = <0>;
+ compatible = "winbond,w25q128", "spi-flash";
+ memory-map = <0xff000000 0x01000000>;
+ };
+ };
};
};
+
};
diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts
index c4469a9..a5c5dc1 100644
--- a/arch/x86/dts/chromebook_link.dts
+++ b/arch/x86/dts/chromebook_link.dts
@@ -186,9 +186,9 @@
intel,pch-backlight = <0x04000000>;
};
- pch {
+ pch@1f,0 {
reg = <0x0000f800 0 0 0 0>;
- compatible = "intel,bd82x6x", "intel,pch";
+ compatible = "intel,bd82x6x", "intel,pch9";
u-boot,dm-pre-reloc;
#address-cells = <1>;
#size-cells = <1>;
@@ -200,6 +200,7 @@
1 0 0 0 0 0 0 0>;
/* Enable EC SMI source */
intel,alt-gp-smi-enable = <0x0100>;
+
spi {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/x86/dts/chromebox_panther.dts b/arch/x86/dts/chromebox_panther.dts
index 4e2b517..2302701 100644
--- a/arch/x86/dts/chromebox_panther.dts
+++ b/arch/x86/dts/chromebox_panther.dts
@@ -51,21 +51,27 @@
ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000
0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
0x01000000 0x0 0x1000 0x1000 0 0xf000>;
- };
- spi {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "intel,ich-spi";
- spi-flash@0 {
- #size-cells = <1>;
- #address-cells = <1>;
- reg = <0>;
- compatible = "winbond,w25q64", "spi-flash";
- memory-map = <0xff800000 0x00800000>;
- rw-mrc-cache {
- label = "rw-mrc-cache";
- reg = <0x003e0000 0x00010000>;
+ pch@1f,0 {
+ reg = <0x0000f800 0 0 0 0>;
+ compatible = "intel,pch9";
+
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "intel,ich-spi";
+ spi-flash@0 {
+ #size-cells = <1>;
+ #address-cells = <1>;
+ reg = <0>;
+ compatible = "winbond,w25q64",
+ "spi-flash";
+ memory-map = <0xff800000 0x00800000>;
+ rw-mrc-cache {
+ label = "rw-mrc-cache";
+ reg = <0x003e0000 0x00010000>;
+ };
+ };
};
};
};
diff --git a/arch/x86/dts/crownbay.dts b/arch/x86/dts/crownbay.dts
index 84231b3..2a18be0 100644
--- a/arch/x86/dts/crownbay.dts
+++ b/arch/x86/dts/crownbay.dts
@@ -72,17 +72,6 @@
stdout-path = "/serial";
};
- spi {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "intel,ich-spi";
- spi-flash@0 {
- reg = <0>;
- compatible = "sst,25vf016b", "spi-flash";
- memory-map = <0xffe00000 0x00200000>;
- };
- };
-
microcode {
update@0 {
#include "microcode/m0220661105_cv.dtsi"
@@ -170,68 +159,85 @@
};
};
- irq-router@1f,0 {
+ pch@1f,0 {
reg = <0x0000f800 0 0 0 0>;
- compatible = "intel,irq-router";
- intel,pirq-config = "pci";
- intel,pirq-link = <0x60 8>;
- intel,pirq-mask = <0xcee0>;
- intel,pirq-routing = <
- /* TunnelCreek PCI devices */
- PCI_BDF(0, 2, 0) INTA PIRQE
- PCI_BDF(0, 3, 0) INTA PIRQF
- PCI_BDF(0, 23, 0) INTA PIRQA
- PCI_BDF(0, 23, 0) INTB PIRQB
- PCI_BDF(0, 23, 0) INTC PIRQC
- PCI_BDF(0, 23, 0) INTD PIRQD
- PCI_BDF(0, 24, 0) INTA PIRQB
- PCI_BDF(0, 24, 0) INTB PIRQC
- PCI_BDF(0, 24, 0) INTC PIRQD
- PCI_BDF(0, 24, 0) INTD PIRQA
- PCI_BDF(0, 25, 0) INTA PIRQC
- PCI_BDF(0, 25, 0) INTB PIRQD
- PCI_BDF(0, 25, 0) INTC PIRQA
- PCI_BDF(0, 25, 0) INTD PIRQB
- PCI_BDF(0, 26, 0) INTA PIRQD
- PCI_BDF(0, 26, 0) INTB PIRQA
- PCI_BDF(0, 26, 0) INTC PIRQB
- PCI_BDF(0, 26, 0) INTD PIRQC
- PCI_BDF(0, 27, 0) INTA PIRQG
- /*
- * Topcliff PCI devices
- *
- * Note on the Crown Bay board, Topcliff chipset
- * is connected to TunnelCreek PCIe port 0, so
- * its bus number is 1 for its PCIe port and 2
- * for its PCI devices per U-Boot current PCI
- * bus enumeration algorithm.
- */
- PCI_BDF(1, 0, 0) INTA PIRQA
- PCI_BDF(2, 0, 1) INTA PIRQA
- PCI_BDF(2, 0, 2) INTA PIRQA
- PCI_BDF(2, 2, 0) INTB PIRQD
- PCI_BDF(2, 2, 1) INTB PIRQD
- PCI_BDF(2, 2, 2) INTB PIRQD
- PCI_BDF(2, 2, 3) INTB PIRQD
- PCI_BDF(2, 2, 4) INTB PIRQD
- PCI_BDF(2, 4, 0) INTC PIRQC
- PCI_BDF(2, 4, 1) INTC PIRQC
- PCI_BDF(2, 6, 0) INTD PIRQB
- PCI_BDF(2, 8, 0) INTA PIRQA
- PCI_BDF(2, 8, 1) INTA PIRQA
- PCI_BDF(2, 8, 2) INTA PIRQA
- PCI_BDF(2, 8, 3) INTA PIRQA
- PCI_BDF(2, 10, 0) INTB PIRQD
- PCI_BDF(2, 10, 1) INTB PIRQD
- PCI_BDF(2, 10, 2) INTB PIRQD
- PCI_BDF(2, 10, 3) INTB PIRQD
- PCI_BDF(2, 10, 4) INTB PIRQD
- PCI_BDF(2, 12, 0) INTC PIRQC
- PCI_BDF(2, 12, 1) INTC PIRQC
- PCI_BDF(2, 12, 2) INTC PIRQC
- PCI_BDF(2, 12, 3) INTC PIRQC
- PCI_BDF(2, 12, 4) INTC PIRQC
- >;
+ compatible = "intel,pch7";
+
+ irq-router {
+ compatible = "intel,irq-router";
+ intel,pirq-config = "pci";
+ intel,pirq-link = <0x60 8>;
+ intel,pirq-mask = <0xcee0>;
+ intel,pirq-routing = <
+ /* TunnelCreek PCI devices */
+ PCI_BDF(0, 2, 0) INTA PIRQE
+ PCI_BDF(0, 3, 0) INTA PIRQF
+ PCI_BDF(0, 23, 0) INTA PIRQA
+ PCI_BDF(0, 23, 0) INTB PIRQB
+ PCI_BDF(0, 23, 0) INTC PIRQC
+ PCI_BDF(0, 23, 0) INTD PIRQD
+ PCI_BDF(0, 24, 0) INTA PIRQB
+ PCI_BDF(0, 24, 0) INTB PIRQC
+ PCI_BDF(0, 24, 0) INTC PIRQD
+ PCI_BDF(0, 24, 0) INTD PIRQA
+ PCI_BDF(0, 25, 0) INTA PIRQC
+ PCI_BDF(0, 25, 0) INTB PIRQD
+ PCI_BDF(0, 25, 0) INTC PIRQA
+ PCI_BDF(0, 25, 0) INTD PIRQB
+ PCI_BDF(0, 26, 0) INTA PIRQD
+ PCI_BDF(0, 26, 0) INTB PIRQA
+ PCI_BDF(0, 26, 0) INTC PIRQB
+ PCI_BDF(0, 26, 0) INTD PIRQC
+ PCI_BDF(0, 27, 0) INTA PIRQG
+ /*
+ * Topcliff PCI devices
+ *
+ * Note on the Crown Bay board, Topcliff
+ * chipset is connected to TunnelCreek
+ * PCIe port 0, so its bus number is 1
+ * for its PCIe port and 2 for its PCI
+ * devices per U-Boot current PCI bus
+ * enumeration algorithm.
+ */
+ PCI_BDF(1, 0, 0) INTA PIRQA
+ PCI_BDF(2, 0, 1) INTA PIRQA
+ PCI_BDF(2, 0, 2) INTA PIRQA
+ PCI_BDF(2, 2, 0) INTB PIRQD
+ PCI_BDF(2, 2, 1) INTB PIRQD
+ PCI_BDF(2, 2, 2) INTB PIRQD
+ PCI_BDF(2, 2, 3) INTB PIRQD
+ PCI_BDF(2, 2, 4) INTB PIRQD
+ PCI_BDF(2, 4, 0) INTC PIRQC
+ PCI_BDF(2, 4, 1) INTC PIRQC
+ PCI_BDF(2, 6, 0) INTD PIRQB
+ PCI_BDF(2, 8, 0) INTA PIRQA
+ PCI_BDF(2, 8, 1) INTA PIRQA
+ PCI_BDF(2, 8, 2) INTA PIRQA
+ PCI_BDF(2, 8, 3) INTA PIRQA
+ PCI_BDF(2, 10, 0) INTB PIRQD
+ PCI_BDF(2, 10, 1) INTB PIRQD
+ PCI_BDF(2, 10, 2) INTB PIRQD
+ PCI_BDF(2, 10, 3) INTB PIRQD
+ PCI_BDF(2, 10, 4) INTB PIRQD
+ PCI_BDF(2, 12, 0) INTC PIRQC
+ PCI_BDF(2, 12, 1) INTC PIRQC
+ PCI_BDF(2, 12, 2) INTC PIRQC
+ PCI_BDF(2, 12, 3) INTC PIRQC
+ PCI_BDF(2, 12, 4) INTC PIRQC
+ >;
+ };
+
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "intel,ich-spi";
+ spi-flash@0 {
+ reg = <0>;
+ compatible = "sst,25vf016b",
+ "spi-flash";
+ memory-map = <0xffe00000 0x00200000>;
+ };
+ };
};
};
diff --git a/arch/x86/dts/galileo.dts b/arch/x86/dts/galileo.dts
index 55165e1..9d82bb3 100644
--- a/arch/x86/dts/galileo.dts
+++ b/arch/x86/dts/galileo.dts
@@ -79,37 +79,59 @@
current-speed = <115200>;
};
- irq-router@1f,0 {
+ pch@1f,0 {
reg = <0x0000f800 0 0 0 0>;
- compatible = "intel,irq-router";
- intel,pirq-config = "pci";
- intel,pirq-link = <0x60 8>;
- intel,pirq-mask = <0xdef8>;
- intel,pirq-routing = <
- PCI_BDF(0, 20, 0) INTA PIRQE
- PCI_BDF(0, 20, 1) INTB PIRQF
- PCI_BDF(0, 20, 2) INTC PIRQG
- PCI_BDF(0, 20, 3) INTD PIRQH
- PCI_BDF(0, 20, 4) INTA PIRQE
- PCI_BDF(0, 20, 5) INTB PIRQF
- PCI_BDF(0, 20, 6) INTC PIRQG
- PCI_BDF(0, 20, 7) INTD PIRQH
- PCI_BDF(0, 21, 0) INTA PIRQE
- PCI_BDF(0, 21, 1) INTB PIRQF
- PCI_BDF(0, 21, 2) INTC PIRQG
- PCI_BDF(0, 23, 0) INTA PIRQA
- PCI_BDF(0, 23, 1) INTB PIRQB
+ compatible = "intel,pch7";
- /* PCIe root ports downstream interrupts */
- PCI_BDF(1, 0, 0) INTA PIRQA
- PCI_BDF(1, 0, 0) INTB PIRQB
- PCI_BDF(1, 0, 0) INTC PIRQC
- PCI_BDF(1, 0, 0) INTD PIRQD
- PCI_BDF(2, 0, 0) INTA PIRQB
- PCI_BDF(2, 0, 0) INTB PIRQC
- PCI_BDF(2, 0, 0) INTC PIRQD
- PCI_BDF(2, 0, 0) INTD PIRQA
- >;
+ irq-router {
+ compatible = "intel,irq-router";
+ intel,pirq-config = "pci";
+ intel,pirq-link = <0x60 8>;
+ intel,pirq-mask = <0xdef8>;
+ intel,pirq-routing = <
+ PCI_BDF(0, 20, 0) INTA PIRQE
+ PCI_BDF(0, 20, 1) INTB PIRQF
+ PCI_BDF(0, 20, 2) INTC PIRQG
+ PCI_BDF(0, 20, 3) INTD PIRQH
+ PCI_BDF(0, 20, 4) INTA PIRQE
+ PCI_BDF(0, 20, 5) INTB PIRQF
+ PCI_BDF(0, 20, 6) INTC PIRQG
+ PCI_BDF(0, 20, 7) INTD PIRQH
+ PCI_BDF(0, 21, 0) INTA PIRQE
+ PCI_BDF(0, 21, 1) INTB PIRQF
+ PCI_BDF(0, 21, 2) INTC PIRQG
+ PCI_BDF(0, 23, 0) INTA PIRQA
+ PCI_BDF(0, 23, 1) INTB PIRQB
+
+ /* PCIe root ports downstream interrupts */
+ PCI_BDF(1, 0, 0) INTA PIRQA
+ PCI_BDF(1, 0, 0) INTB PIRQB
+ PCI_BDF(1, 0, 0) INTC PIRQC
+ PCI_BDF(1, 0, 0) INTD PIRQD
+ PCI_BDF(2, 0, 0) INTA PIRQB
+ PCI_BDF(2, 0, 0) INTB PIRQC
+ PCI_BDF(2, 0, 0) INTC PIRQD
+ PCI_BDF(2, 0, 0) INTD PIRQA
+ >;
+ };
+
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "intel,ich-spi";
+ spi-flash@0 {
+ #size-cells = <1>;
+ #address-cells = <1>;
+ reg = <0>;
+ compatible = "winbond,w25q64",
+ "spi-flash";
+ memory-map = <0xff800000 0x00800000>;
+ rw-mrc-cache {
+ label = "rw-mrc-cache";
+ reg = <0x00010000 0x00010000>;
+ };
+ };
+ };
};
};
@@ -127,21 +149,4 @@
bank-name = "B";
};
- spi {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "intel,ich-spi";
- spi-flash@0 {
- #size-cells = <1>;
- #address-cells = <1>;
- reg = <0>;
- compatible = "winbond,w25q64", "spi-flash";
- memory-map = <0xff800000 0x00800000>;
- rw-mrc-cache {
- label = "rw-mrc-cache";
- reg = <0x00010000 0x00010000>;
- };
- };
- };
-
};
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index bbfd6d4..e7ef7c9 100644
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -150,66 +150,91 @@
0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
0x01000000 0x0 0x2000 0x2000 0 0xe000>;
- irq-router@1f,0 {
+ pch@1f,0 {
reg = <0x0000f800 0 0 0 0>;
- compatible = "intel,irq-router";
- intel,pirq-config = "ibase";
- intel,ibase-offset = <0x50>;
- intel,pirq-link = <8 8>;
- intel,pirq-mask = <0xdee0>;
- intel,pirq-routing = <
- /* BayTrail PCI devices */
- PCI_BDF(0, 2, 0) INTA PIRQA
- PCI_BDF(0, 3, 0) INTA PIRQA
- PCI_BDF(0, 16, 0) INTA PIRQA
- PCI_BDF(0, 17, 0) INTA PIRQA
- PCI_BDF(0, 18, 0) INTA PIRQA
- PCI_BDF(0, 19, 0) INTA PIRQA
- PCI_BDF(0, 20, 0) INTA PIRQA
- PCI_BDF(0, 21, 0) INTA PIRQA
- PCI_BDF(0, 22, 0) INTA PIRQA
- PCI_BDF(0, 23, 0) INTA PIRQA
- PCI_BDF(0, 24, 0) INTA PIRQA
- PCI_BDF(0, 24, 1) INTC PIRQC
- PCI_BDF(0, 24, 2) INTD PIRQD
- PCI_BDF(0, 24, 3) INTB PIRQB
- PCI_BDF(0, 24, 4) INTA PIRQA
- PCI_BDF(0, 24, 5) INTC PIRQC
- PCI_BDF(0, 24, 6) INTD PIRQD
- PCI_BDF(0, 24, 7) INTB PIRQB
- PCI_BDF(0, 26, 0) INTA PIRQA
- PCI_BDF(0, 27, 0) INTA PIRQA
- PCI_BDF(0, 28, 0) INTA PIRQA
- PCI_BDF(0, 28, 1) INTB PIRQB
- PCI_BDF(0, 28, 2) INTC PIRQC
- PCI_BDF(0, 28, 3) INTD PIRQD
- PCI_BDF(0, 29, 0) INTA PIRQA
- PCI_BDF(0, 30, 0) INTA PIRQA
- PCI_BDF(0, 30, 1) INTD PIRQD
- PCI_BDF(0, 30, 2) INTB PIRQB
- PCI_BDF(0, 30, 3) INTC PIRQC
- PCI_BDF(0, 30, 4) INTD PIRQD
- PCI_BDF(0, 30, 5) INTB PIRQB
- PCI_BDF(0, 31, 3) INTB PIRQB
+ compatible = "pci8086,0f1c", "intel,pch9";
- /* PCIe root ports downstream interrupts */
- PCI_BDF(1, 0, 0) INTA PIRQA
- PCI_BDF(1, 0, 0) INTB PIRQB
- PCI_BDF(1, 0, 0) INTC PIRQC
- PCI_BDF(1, 0, 0) INTD PIRQD
- PCI_BDF(2, 0, 0) INTA PIRQB
- PCI_BDF(2, 0, 0) INTB PIRQC
- PCI_BDF(2, 0, 0) INTC PIRQD
- PCI_BDF(2, 0, 0) INTD PIRQA
- PCI_BDF(3, 0, 0) INTA PIRQC
- PCI_BDF(3, 0, 0) INTB PIRQD
- PCI_BDF(3, 0, 0) INTC PIRQA
- PCI_BDF(3, 0, 0) INTD PIRQB
- PCI_BDF(4, 0, 0) INTA PIRQD
- PCI_BDF(4, 0, 0) INTB PIRQA
- PCI_BDF(4, 0, 0) INTC PIRQB
- PCI_BDF(4, 0, 0) INTD PIRQC
- >;
+ irq-router {
+ compatible = "intel,irq-router";
+ intel,pirq-config = "ibase";
+ intel,ibase-offset = <0x50>;
+ intel,pirq-link = <8 8>;
+ intel,pirq-mask = <0xdee0>;
+ intel,pirq-routing = <
+ /* BayTrail PCI devices */
+ PCI_BDF(0, 2, 0) INTA PIRQA
+ PCI_BDF(0, 3, 0) INTA PIRQA
+ PCI_BDF(0, 16, 0) INTA PIRQA
+ PCI_BDF(0, 17, 0) INTA PIRQA
+ PCI_BDF(0, 18, 0) INTA PIRQA
+ PCI_BDF(0, 19, 0) INTA PIRQA
+ PCI_BDF(0, 20, 0) INTA PIRQA
+ PCI_BDF(0, 21, 0) INTA PIRQA
+ PCI_BDF(0, 22, 0) INTA PIRQA
+ PCI_BDF(0, 23, 0) INTA PIRQA
+ PCI_BDF(0, 24, 0) INTA PIRQA
+ PCI_BDF(0, 24, 1) INTC PIRQC
+ PCI_BDF(0, 24, 2) INTD PIRQD
+ PCI_BDF(0, 24, 3) INTB PIRQB
+ PCI_BDF(0, 24, 4) INTA PIRQA
+ PCI_BDF(0, 24, 5) INTC PIRQC
+ PCI_BDF(0, 24, 6) INTD PIRQD
+ PCI_BDF(0, 24, 7) INTB PIRQB
+ PCI_BDF(0, 26, 0) INTA PIRQA
+ PCI_BDF(0, 27, 0) INTA PIRQA
+ PCI_BDF(0, 28, 0) INTA PIRQA
+ PCI_BDF(0, 28, 1) INTB PIRQB
+ PCI_BDF(0, 28, 2) INTC PIRQC
+ PCI_BDF(0, 28, 3) INTD PIRQD
+ PCI_BDF(0, 29, 0) INTA PIRQA
+ PCI_BDF(0, 30, 0) INTA PIRQA
+ PCI_BDF(0, 30, 1) INTD PIRQD
+ PCI_BDF(0, 30, 2) INTB PIRQB
+ PCI_BDF(0, 30, 3) INTC PIRQC
+ PCI_BDF(0, 30, 4) INTD PIRQD
+ PCI_BDF(0, 30, 5) INTB PIRQB
+ PCI_BDF(0, 31, 3) INTB PIRQB
+
+ /*
+ * PCIe root ports downstream
+ * interrupts
+ */
+ PCI_BDF(1, 0, 0) INTA PIRQA
+ PCI_BDF(1, 0, 0) INTB PIRQB
+ PCI_BDF(1, 0, 0) INTC PIRQC
+ PCI_BDF(1, 0, 0) INTD PIRQD
+ PCI_BDF(2, 0, 0) INTA PIRQB
+ PCI_BDF(2, 0, 0) INTB PIRQC
+ PCI_BDF(2, 0, 0) INTC PIRQD
+ PCI_BDF(2, 0, 0) INTD PIRQA
+ PCI_BDF(3, 0, 0) INTA PIRQC
+ PCI_BDF(3, 0, 0) INTB PIRQD
+ PCI_BDF(3, 0, 0) INTC PIRQA
+ PCI_BDF(3, 0, 0) INTD PIRQB
+ PCI_BDF(4, 0, 0) INTA PIRQD
+ PCI_BDF(4, 0, 0) INTB PIRQA
+ PCI_BDF(4, 0, 0) INTC PIRQB
+ PCI_BDF(4, 0, 0) INTD PIRQC
+ >;
+ };
+
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "intel,ich-spi";
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>;
+ compatible = "stmicro,n25q064a",
+ "spi-flash";
+ memory-map = <0xff800000 0x00800000>;
+ rw-mrc-cache {
+ label = "rw-mrc-cache";
+ reg = <0x006f0000 0x00010000>;
+ };
+ };
+ };
};
};
@@ -269,23 +294,6 @@
};
};
- spi {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "intel,ich-spi";
- spi-flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0>;
- compatible = "stmicro,n25q064a", "spi-flash";
- memory-map = <0xff800000 0x00800000>;
- rw-mrc-cache {
- label = "rw-mrc-cache";
- reg = <0x006f0000 0x00010000>;
- };
- };
- };
-
microcode {
update@0 {
#include "microcode/m0130673322.dtsi"
diff --git a/arch/x86/dts/qemu-x86_i440fx.dts b/arch/x86/dts/qemu-x86_i440fx.dts
index 9086b46..9c3f2a0 100644
--- a/arch/x86/dts/qemu-x86_i440fx.dts
+++ b/arch/x86/dts/qemu-x86_i440fx.dts
@@ -51,18 +51,22 @@
0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
0x01000000 0x0 0x2000 0x2000 0 0xe000>;
- irq-router@1,0 {
+ pch@1,0 {
reg = <0x00000800 0 0 0 0>;
- compatible = "intel,irq-router";
- intel,pirq-config = "pci";
- intel,pirq-link = <0x60 4>;
- intel,pirq-mask = <0x0e40>;
- intel,pirq-routing = <
- /* PIIX UHCI */
- PCI_BDF(0, 1, 2) INTD PIRQD
- /* e1000 NIC */
- PCI_BDF(0, 3, 0) INTA PIRQC
- >;
+ compatible = "intel,pch7";
+
+ irq-router {
+ compatible = "intel,irq-router";
+ intel,pirq-config = "pci";
+ intel,pirq-link = <0x60 4>;
+ intel,pirq-mask = <0x0e40>;
+ intel,pirq-routing = <
+ /* PIIX UHCI */
+ PCI_BDF(0, 1, 2) INTD PIRQD
+ /* e1000 NIC */
+ PCI_BDF(0, 3, 0) INTA PIRQC
+ >;
+ };
};
};
diff --git a/arch/x86/dts/qemu-x86_q35.dts b/arch/x86/dts/qemu-x86_q35.dts
index 145e811..5d601b3 100644
--- a/arch/x86/dts/qemu-x86_q35.dts
+++ b/arch/x86/dts/qemu-x86_q35.dts
@@ -62,24 +62,28 @@
0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
0x01000000 0x0 0x2000 0x2000 0 0xe000>;
- irq-router@1f,0 {
+ pch@1f,0 {
reg = <0x0000f800 0 0 0 0>;
- compatible = "intel,irq-router";
- intel,pirq-config = "pci";
- intel,pirq-link = <0x60 8>;
- intel,pirq-mask = <0x0e40>;
- intel,pirq-routing = <
- /* e1000 NIC */
- PCI_BDF(0, 2, 0) INTA PIRQG
- /* ICH9 UHCI */
- PCI_BDF(0, 29, 0) INTA PIRQA
- PCI_BDF(0, 29, 1) INTB PIRQB
- PCI_BDF(0, 29, 2) INTC PIRQC
- /* ICH9 EHCI */
- PCI_BDF(0, 29, 7) INTD PIRQD
- /* ICH9 SATA */
- PCI_BDF(0, 31, 2) INTA PIRQA
- >;
+ compatible = "intel,pch9";
+
+ irq-router {
+ compatible = "intel,irq-router";
+ intel,pirq-config = "pci";
+ intel,pirq-link = <0x60 8>;
+ intel,pirq-mask = <0x0e40>;
+ intel,pirq-routing = <
+ /* e1000 NIC */
+ PCI_BDF(0, 2, 0) INTA PIRQG
+ /* ICH9 UHCI */
+ PCI_BDF(0, 29, 0) INTA PIRQA
+ PCI_BDF(0, 29, 1) INTB PIRQB
+ PCI_BDF(0, 29, 2) INTC PIRQC
+ /* ICH9 EHCI */
+ PCI_BDF(0, 29, 7) INTD PIRQD
+ /* ICH9 SATA */
+ PCI_BDF(0, 31, 2) INTA PIRQA
+ >;
+ };
};
};