arm: dts: introduce dtsi for i.MX8QXP
Introduce dtsi for i.MX8QXP, since there is other variants i.MX8DX(P),
so add them there, because i.MX8QXP includes the dtsi of them.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
diff --git a/arch/arm/dts/fsl-imx8qxp.dtsi b/arch/arm/dts/fsl-imx8qxp.dtsi
new file mode 100644
index 0000000..1bffff1
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8qxp.dtsi
@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "fsl-imx8dxp.dtsi"
+
+/ {
+ model = "Freescale i.MX8QXP";
+ compatible = "fsl,imx8qxp";
+
+ cpus {
+ A35_2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a35";
+ reg = <0x0 0x2>;
+ enable-method = "psci";
+ next-level-cache = <&A35_L2>;
+ };
+
+ A35_3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a35";
+ reg = <0x0 0x3>;
+ enable-method = "psci";
+ next-level-cache = <&A35_L2>;
+ };
+ };
+
+ pmu {
+ interrupt-affinity = <&A35_0>, <&A35_1>, <&A35_2>, <&A35_3>;
+ };
+};
+
+&A35_2 {
+ device_type = "cpu";
+};
+
+&A35_3 {
+ device_type = "cpu";
+};