Merge branch 'u-boot/master' into 'u-boot-arm/master'
Conflicts:
arch/arm/cpu/armv7/rmobile/Makefile
doc/README.scrapyard
Needed manual fix:
arch/arm/cpu/armv7/omap-common/Makefile
board/compulab/cm_t335/u-boot.lds
diff --git a/CREDITS b/CREDITS
index 3b657e9..52f289e 100644
--- a/CREDITS
+++ b/CREDITS
@@ -143,7 +143,7 @@
N: Dr. Wolfgang Grandegger
E: wg@denx.de
-D: Support for Interphase 4539 T1/E1/J1 PMC, PN62, CCM, SCM boards
+D: Support for Interphase 4539 T1/E1/J1 PMC, CCM, SCM boards
W: www.denx.de
N: Peter Figuli
diff --git a/MAKEALL b/MAKEALL
index 80cd4f8..a74f0fc 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -18,6 +18,7 @@
-c CPU, --cpu CPU Build all boards with cpu CPU
-v VENDOR, --vendor VENDOR Build all boards with vendor VENDOR
-s SOC, --soc SOC Build all boards with soc SOC
+ -b BOARD, --board BOARD Build all boards with board name BOARD
-l, --list List all targets to be built
-m, --maintainers List all targets and maintainer email
-M, --mails List all targets and all affilated emails
@@ -59,8 +60,8 @@
exit ${ret}
}
-SHORT_OPTS="ha:c:v:s:lmMCnr"
-LONG_OPTS="help,arch:,cpu:,vendor:,soc:,list,maintainers,mails,check,continue,rebuild-errors"
+SHORT_OPTS="ha:c:v:s:b:lmMCnr"
+LONG_OPTS="help,arch:,cpu:,vendor:,soc:,board:,list,maintainers,mails,check,continue,rebuild-errors"
# Option processing based on util-linux-2.13/getopt-parse.bash
@@ -121,6 +122,17 @@
fi
SELECTED='y'
shift 2 ;;
+ -b|--board)
+ # echo "Option BOARD: argument \`$2'"
+ if [ "$opt_b" ] ; then
+ opt_b="${opt_b%)} || \$6 == \"$2\" || \$7 == \"$2\")"
+ else
+ # We need to check the 7th field too
+ # for boards whose 6th field is "-"
+ opt_b="(\$6 == \"$2\" || \$7 == \"$2\")"
+ fi
+ SELECTED='y'
+ shift 2 ;;
-C|--check)
CHECK='C=1'
shift ;;
@@ -158,6 +170,7 @@
[ "$opt_c" ] && FILTER="${FILTER} && $opt_c"
[ "$opt_s" ] && FILTER="${FILTER} && $opt_s"
[ "$opt_v" ] && FILTER="${FILTER} && $opt_v"
+[ "$opt_b" ] && FILTER="${FILTER} && $opt_b"
if [ "$SELECTED" ] ; then
SELECTED=$(awk '('"$FILTER"') { print $7 }' boards.cfg)
diff --git a/Makefile b/Makefile
index af0ad57..607d1dc 100644
--- a/Makefile
+++ b/Makefile
@@ -5,10 +5,10 @@
# SPDX-License-Identifier: GPL-2.0+
#
-VERSION = 2013
-PATCHLEVEL = 10
+VERSION = 2014
+PATCHLEVEL = 01
SUBLEVEL =
-EXTRAVERSION =
+EXTRAVERSION = -rc1
ifneq "$(SUBLEVEL)" ""
U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
else
@@ -65,11 +65,9 @@
# the object files are placed in the source directory.
#
-ifdef O
ifeq ("$(origin O)", "command line")
BUILD_DIR := $(O)
endif
-endif
# Call a source code checker (by default, "sparse") as part of the
# C compilation.
@@ -138,7 +136,6 @@
# The "examples" conditionally depend on U-Boot (say, when USE_PRIVATE_LIBGCC
# is "yes"), so compile examples after U-Boot is compiled.
SUBDIR_TOOLS = tools
-SUBDIR_EXAMPLES = examples/standalone examples/api
SUBDIRS = $(SUBDIR_TOOLS)
.PHONY : $(SUBDIRS) $(VERSION_FILE) $(TIMESTAMP_FILE)
@@ -152,8 +149,10 @@
sinclude $(obj)include/autoconf.mk.dep
sinclude $(obj)include/autoconf.mk
+SUBDIR_EXAMPLES-y := examples/standalone
+SUBDIR_EXAMPLES-$(CONFIG_API) += examples/api
ifndef CONFIG_SANDBOX
-SUBDIRS += $(SUBDIR_EXAMPLES)
+SUBDIRS += $(SUBDIR_EXAMPLES-y)
endif
# load ARCH, BOARD, and CPU configuration
@@ -231,87 +230,67 @@
HAVE_VENDOR_COMMON_LIB = $(if $(wildcard board/$(VENDOR)/common/Makefile),y,n)
-LIBS-y += lib/libgeneric.o
-LIBS-y += lib/rsa/librsa.o
-LIBS-y += lib/lzma/liblzma.o
-LIBS-y += lib/lzo/liblzo.o
-LIBS-y += lib/zlib/libz.o
-LIBS-$(CONFIG_TIZEN) += lib/tizen/libtizen.o
-LIBS-$(HAVE_VENDOR_COMMON_LIB) += board/$(VENDOR)/common/lib$(VENDOR).o
-LIBS-y += $(CPUDIR)/lib$(CPU).o
+LIBS-y += lib/
+LIBS-$(HAVE_VENDOR_COMMON_LIB) += board/$(VENDOR)/common/
+LIBS-y += $(CPUDIR)/
ifdef SOC
-LIBS-y += $(CPUDIR)/$(SOC)/lib$(SOC).o
+LIBS-y += $(CPUDIR)/$(SOC)/
endif
-ifeq ($(CPU),ixp)
-LIBS-y += drivers/net/npe/libnpe.o
-endif
-LIBS-$(CONFIG_OF_EMBED) += dts/libdts.o
-LIBS-y += arch/$(ARCH)/lib/lib$(ARCH).o
-LIBS-y += fs/libfs.o \
- fs/fat/libfat.o
-LIBS-y += net/libnet.o
-LIBS-y += disk/libdisk.o
-LIBS-y += drivers/libdrivers.o
-LIBS-y += drivers/dma/libdma.o
-LIBS-y += drivers/gpio/libgpio.o
-LIBS-y += drivers/i2c/libi2c.o
-LIBS-y += drivers/input/libinput.o
-LIBS-y += drivers/mmc/libmmc.o
-LIBS-y += drivers/mtd/libmtd.o
-LIBS-y += drivers/mtd/nand/libnand.o
-LIBS-y += drivers/mtd/onenand/libonenand.o
-LIBS-y += drivers/mtd/ubi/libubi.o
-LIBS-y += drivers/mtd/spi/libspi_flash.o
-LIBS-y += drivers/net/libnet.o
-LIBS-y += drivers/net/phy/libphy.o
-LIBS-y += drivers/pci/libpci.o
-LIBS-y += drivers/power/libpower.o \
- drivers/power/fuel_gauge/libfuel_gauge.o \
- drivers/power/mfd/libmfd.o \
- drivers/power/pmic/libpmic.o \
- drivers/power/battery/libbattery.o
-LIBS-y += drivers/spi/libspi.o
-ifeq ($(CPU),mpc83xx)
-LIBS-y += drivers/qe/libqe.o
-LIBS-y += arch/powerpc/cpu/mpc8xxx/ddr/libddr.o
-LIBS-y += arch/powerpc/cpu/mpc8xxx/lib8xxx.o
-endif
-ifeq ($(CPU),mpc85xx)
-LIBS-y += drivers/qe/libqe.o
-LIBS-y += drivers/net/fm/libfm.o
-LIBS-y += arch/powerpc/cpu/mpc8xxx/ddr/libddr.o
-LIBS-y += arch/powerpc/cpu/mpc8xxx/lib8xxx.o
-endif
-ifeq ($(CPU),mpc86xx)
-LIBS-y += arch/powerpc/cpu/mpc8xxx/ddr/libddr.o
-LIBS-y += arch/powerpc/cpu/mpc8xxx/lib8xxx.o
-endif
-LIBS-y += drivers/serial/libserial.o
-LIBS-y += drivers/usb/eth/libusb_eth.o
-LIBS-y += drivers/usb/gadget/libusb_gadget.o
-LIBS-y += drivers/usb/host/libusb_host.o
-LIBS-y += drivers/usb/musb/libusb_musb.o
-LIBS-y += drivers/usb/musb-new/libusb_musb-new.o
-LIBS-y += drivers/usb/phy/libusb_phy.o
-LIBS-y += drivers/usb/ulpi/libusb_ulpi.o
-LIBS-y += common/libcommon.o
-LIBS-y += lib/libfdt/libfdt.o
-LIBS-y += api/libapi.o
-LIBS-y += post/libpost.o
-LIBS-y += test/libtest.o
+LIBS-$(CONFIG_IXP4XX_NPE) += drivers/net/npe/
+LIBS-$(CONFIG_OF_EMBED) += dts/
+LIBS-y += arch/$(ARCH)/lib/
+LIBS-y += fs/
+LIBS-y += net/
+LIBS-y += disk/
+LIBS-y += drivers/
+LIBS-y += drivers/dma/
+LIBS-y += drivers/gpio/
+LIBS-y += drivers/i2c/
+LIBS-y += drivers/input/
+LIBS-y += drivers/mmc/
+LIBS-y += drivers/mtd/
+LIBS-y += drivers/mtd/nand/
+LIBS-y += drivers/mtd/onenand/
+LIBS-y += drivers/mtd/ubi/
+LIBS-y += drivers/mtd/spi/
+LIBS-y += drivers/net/
+LIBS-y += drivers/net/phy/
+LIBS-y += drivers/pci/
+LIBS-y += drivers/power/ \
+ drivers/power/fuel_gauge/ \
+ drivers/power/mfd/ \
+ drivers/power/pmic/ \
+ drivers/power/battery/
+LIBS-y += drivers/spi/
+LIBS-$(CONFIG_FMAN_ENET) += drivers/net/fm/
+LIBS-$(CONFIG_SYS_FSL_DDR) += drivers/ddr/fsl/
+LIBS-y += drivers/serial/
+LIBS-y += drivers/usb/eth/
+LIBS-y += drivers/usb/gadget/
+LIBS-y += drivers/usb/host/
+LIBS-y += drivers/usb/musb/
+LIBS-y += drivers/usb/musb-new/
+LIBS-y += drivers/usb/phy/
+LIBS-y += drivers/usb/ulpi/
+LIBS-y += common/
+LIBS-y += lib/libfdt/
+LIBS-$(CONFIG_API) += api/
+LIBS-y += post/
+LIBS-y += test/
ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35 mxs vf610))
-LIBS-y += arch/$(ARCH)/imx-common/libimx-common.o
+LIBS-y += arch/$(ARCH)/imx-common/
endif
-LIBS-$(CONFIG_ARM) += arch/arm/cpu/libcpu.o
+LIBS-$(CONFIG_ARM) += arch/arm/cpu/
+LIBS-$(CONFIG_PPC) += arch/powerpc/cpu/
+LIBS-y += board/$(BOARDDIR)/
+
+LIBS-y := $(patsubst %/, %/built-in.o, $(LIBS-y))
LIBS := $(addprefix $(obj),$(sort $(LIBS-y)))
.PHONY : $(LIBS)
-LIBBOARD = board/$(BOARDDIR)/lib$(BOARD).o
-LIBBOARD := $(addprefix $(obj),$(LIBBOARD))
-
# Add GCC lib
ifdef USE_PRIVATE_LIBGCC
ifeq ("$(USE_PRIVATE_LIBGCC)", "yes")
@@ -335,7 +314,7 @@
sed -ne 's/GNU ld version \([0-9][0-9]*\)\.\([0-9][0-9]*\).*/-DLD_MAJOR=\1 -DLD_MINOR=\2/p')
__OBJS := $(subst $(obj),,$(OBJS))
-__LIBS := $(subst $(obj),,$(LIBS)) $(subst $(obj),,$(LIBBOARD))
+__LIBS := $(subst $(obj),,$(LIBS))
#########################################################################
#########################################################################
@@ -380,7 +359,7 @@
build := -f $(TOPDIR)/scripts/Makefile.build -C
-all: $(ALL-y) $(SUBDIR_EXAMPLES)
+all: $(ALL-y) $(SUBDIR_EXAMPLES-y)
$(obj)u-boot.dtb: checkdtc $(obj)u-boot
$(MAKE) $(build) dts binary
@@ -549,7 +528,7 @@
endif
$(obj)u-boot: depend \
- $(SUBDIR_TOOLS) $(OBJS) $(LIBBOARD) $(LIBS) $(LDSCRIPT) $(obj)u-boot.lds
+ $(SUBDIR_TOOLS) $(OBJS) $(LIBS) $(LDSCRIPT) $(obj)u-boot.lds
$(GEN_UBOOT)
ifeq ($(CONFIG_KALLSYMS),y)
smap=`$(call SYSTEM_MAP,$(obj)u-boot) | \
@@ -564,16 +543,11 @@
$(LIBS): depend $(SUBDIR_TOOLS)
$(MAKE) $(build) $(dir $(subst $(obj),,$@))
- mv $(dir $@)built-in.o $@
-
-$(LIBBOARD): depend $(LIBS)
- $(MAKE) $(build) $(dir $(subst $(obj),,$@))
- mv $(dir $@)built-in.o $@
$(SUBDIRS): depend
$(MAKE) -C $@ all
-$(SUBDIR_EXAMPLES): $(obj)u-boot
+$(SUBDIR_EXAMPLES-y): $(obj)u-boot
$(LDSCRIPT): depend
$(MAKE) -C $(dir $@) $(notdir $@)
@@ -593,9 +567,6 @@
$(obj)tpl/u-boot-tpl.bin: $(SUBDIR_TOOLS) depend
$(MAKE) -C spl all CONFIG_TPL_BUILD=y
-updater:
- $(MAKE) -C tools/updater all
-
# Explicitly make _depend in subdirs containing multiple targets to prevent
# parallel sub-makes creating .depend files simultaneously.
depend dep: $(TIMESTAMP_FILE) $(VERSION_FILE) \
@@ -634,7 +605,7 @@
grep -v '\(compiled\)\|\(\.o$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \
LC_ALL=C sort
$(obj)System.map: $(obj)u-boot
- @$(call SYSTEM_MAP,$<) > $(obj)System.map
+ @$(call SYSTEM_MAP,$<) > $@
checkthumb:
@if test $(call cc-version) -lt 0404; then \
@@ -738,7 +709,7 @@
all $(obj)u-boot.hex $(obj)u-boot.srec $(obj)u-boot.bin \
$(obj)u-boot.img $(obj)u-boot.dis $(obj)u-boot \
$(filter-out tools,$(SUBDIRS)) \
-updater depend dep tags ctags etags cscope $(obj)System.map:
+depend dep tags ctags etags cscope $(obj)System.map:
@echo "System not configured - see README" >&2
@ exit 1
@@ -806,12 +777,6 @@
$(obj).boards.depend: boards.cfg
@awk '(NF && $$1 !~ /^#/) { print $$7 ": " $$7 "_config; $$(MAKE)" }' $< > $@
-#
-# Functions to generate common board directory names
-#
-lcname = $(shell echo $(1) | sed -e 's/\(.*\)_config/\L\1/')
-ucname = $(shell echo $(1) | sed -e 's/\(.*\)_config/\U\1/')
-
#########################################################################
#########################################################################
@@ -888,8 +853,6 @@
@rm -f $(obj)MLO MLO.byteswap
@rm -f $(obj)SPL
@rm -f $(obj)tools/xway-swap-bytes
- @rm -f $(obj)arch/powerpc/cpu/mpc824x/bedbug_603e.c
- @rm -f $(obj)arch/powerpc/cpu/mpc83xx/ddr-gen?.c
@rm -fr $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm
@rm -fr $(obj)include/generated
@[ ! -d $(obj)nand_spl ] || find $(obj)nand_spl -name "*" -type l -print | xargs rm -f
diff --git a/README b/README
index f0ffaf4..1130b4f 100644
--- a/README
+++ b/README
@@ -423,16 +423,50 @@
CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
This value denotes start offset of DSP CCSR space.
- CONFIG_SYS_FSL_DDR_EMU
- Specify emulator support for DDR. Some DDR features such as
- deskew training are not available.
-
- Generic CPU options:
CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
Defines the endianess of the CPU. Implementation of those
values is arch specific.
+ CONFIG_SYS_FSL_DDR
+ Freescale DDR driver in use. This type of DDR controller is
+ found in mpc83xx, mpc85xx, mpc86xx as well as some ARM core
+ SoCs.
+
+ CONFIG_SYS_FSL_DDR_ADDR
+ Freescale DDR memory-mapped register base.
+
+ CONFIG_SYS_FSL_DDR_EMU
+ Specify emulator support for DDR. Some DDR features such as
+ deskew training are not available.
+
+ CONFIG_SYS_FSL_DDRC_GEN1
+ Freescale DDR1 controller.
+
+ CONFIG_SYS_FSL_DDRC_GEN2
+ Freescale DDR2 controller.
+
+ CONFIG_SYS_FSL_DDRC_GEN3
+ Freescale DDR3 controller.
+
+ CONFIG_SYS_FSL_DDRC_ARM_GEN3
+ Freescale DDR3 controller for ARM-based SoCs.
+
+ CONFIG_SYS_FSL_DDR1
+ Board config to use DDR1. It can be enabled for SoCs with
+ Freescale DDR1 or DDR2 controllers, depending on the board
+ implemetation.
+
+ CONFIG_SYS_FSL_DDR2
+ Board config to use DDR2. It can be eanbeld for SoCs with
+ Freescale DDR2 or DDR3 controllers, depending on the board
+ implementation.
+
+ CONFIG_SYS_FSL_DDR3
+ Board config to use DDR3. It can be enabled for SoCs with
+ Freescale DDR3 controllers.
+
- Intel Monahans options:
CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO
@@ -1979,6 +2013,21 @@
kernel). Defining CONFIG_STATUS_LED enables this
feature in U-Boot.
+ Additional options:
+
+ CONFIG_GPIO_LED
+ The status LED can be connected to a GPIO pin.
+ In such cases, the gpio_led driver can be used as a
+ status LED backend implementation. Define CONFIG_GPIO_LED
+ to include the gpio_led driver in the U-Boot binary.
+
+ CONFIG_GPIO_LED_INVERTED_TABLE
+ Some GPIO connected LEDs may have inverted polarity in which
+ case the GPIO high value corresponds to LED off state and
+ GPIO low value corresponds to LED on state.
+ In such cases CONFIG_GPIO_LED_INVERTED_TABLE may be defined
+ with a list of GPIO LEDs that have inverted polarity.
+
- CAN Support: CONFIG_CAN_DRIVER
Defining CONFIG_CAN_DRIVER enables CAN driver support
@@ -2056,6 +2105,42 @@
- CONFIG_SYS_RCAR_I2C3_SPEED for for the speed channel 3
- CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS for number of i2c buses
+ - drivers/i2c/sh_i2c.c:
+ - activate this driver with CONFIG_SYS_I2C_SH
+ - This driver adds from 2 to 5 i2c buses
+
+ - CONFIG_SYS_I2C_SH_BASE0 for setting the register channel 0
+ - CONFIG_SYS_I2C_SH_SPEED0 for for the speed channel 0
+ - CONFIG_SYS_I2C_SH_BASE1 for setting the register channel 1
+ - CONFIG_SYS_I2C_SH_SPEED1 for for the speed channel 1
+ - CONFIG_SYS_I2C_SH_BASE2 for setting the register channel 2
+ - CONFIG_SYS_I2C_SH_SPEED2 for for the speed channel 2
+ - CONFIG_SYS_I2C_SH_BASE3 for setting the register channel 3
+ - CONFIG_SYS_I2C_SH_SPEED3 for for the speed channel 3
+ - CONFIG_SYS_I2C_SH_BASE4 for setting the register channel 4
+ - CONFIG_SYS_I2C_SH_SPEED4 for for the speed channel 4
+ - CONFIG_SYS_I2C_SH_BASE5 for setting the register channel 5
+ - CONFIG_SYS_I2C_SH_SPEED5 for for the speed channel 5
+ - CONFIF_SYS_I2C_SH_NUM_CONTROLLERS for nummber of i2c buses
+
+ - drivers/i2c/omap24xx_i2c.c
+ - activate this driver with CONFIG_SYS_I2C_OMAP24XX
+ - CONFIG_SYS_OMAP24_I2C_SPEED speed channel 0
+ - CONFIG_SYS_OMAP24_I2C_SLAVE slave addr channel 0
+ - CONFIG_SYS_OMAP24_I2C_SPEED1 speed channel 1
+ - CONFIG_SYS_OMAP24_I2C_SLAVE1 slave addr channel 1
+ - CONFIG_SYS_OMAP24_I2C_SPEED2 speed channel 2
+ - CONFIG_SYS_OMAP24_I2C_SLAVE2 slave addr channel 2
+ - CONFIG_SYS_OMAP24_I2C_SPEED3 speed channel 3
+ - CONFIG_SYS_OMAP24_I2C_SLAVE3 slave addr channel 3
+ - CONFIG_SYS_OMAP24_I2C_SPEED4 speed channel 4
+ - CONFIG_SYS_OMAP24_I2C_SLAVE4 slave addr channel 4
+
+ - drivers/i2c/zynq_i2c.c
+ - activate this driver with CONFIG_SYS_I2C_ZYNQ
+ - set CONFIG_SYS_I2C_ZYNQ_SPEED for speed setting
+ - set CONFIG_SYS_I2C_ZYNQ_SLAVE for slave addr
+
additional defines:
CONFIG_SYS_NUM_I2C_BUSES
@@ -3162,7 +3247,7 @@
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
Set for the SPL on PPC mpc8xxx targets, support for
- arch/powerpc/cpu/mpc8xxx/ddr/libddr.o in SPL binary.
+ drivers/ddr/fsl/libddr.o in SPL binary.
CONFIG_SPL_COMMON_INIT_DDR
Set for common ddr init with serial presence detect in
diff --git a/api/Makefile b/api/Makefile
index fb130ff..3c095ee 100644
--- a/api/Makefile
+++ b/api/Makefile
@@ -4,5 +4,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(CONFIG_API) += api.o api_display.o api_net.o api_storage.o \
- api_platform-$(ARCH).o
+obj-y += api.o api_display.o api_net.o api_storage.o
+obj-$(CONFIG_ARM) += api_platform-arm.o
+obj-$(CONFIG_PPC) += api_platform-powerpc.o
diff --git a/arch/arm/cpu/armv7/am33xx/Makefile b/arch/arm/cpu/armv7/am33xx/Makefile
index 966fcab..5566310 100644
--- a/arch/arm/cpu/armv7/am33xx/Makefile
+++ b/arch/arm/cpu/armv7/am33xx/Makefile
@@ -19,4 +19,3 @@
obj-y += emif4.o
obj-y += board.o
obj-y += mux.o
-obj-$(CONFIG_NAND_OMAP_GPMC) += elm.o
diff --git a/arch/arm/cpu/armv7/am33xx/mem.c b/arch/arm/cpu/armv7/am33xx/mem.c
index b6eb466..56c9e7d 100644
--- a/arch/arm/cpu/armv7/am33xx/mem.c
+++ b/arch/arm/cpu/armv7/am33xx/mem.c
@@ -22,17 +22,6 @@
struct gpmc *gpmc_cfg;
-#if defined(CONFIG_CMD_NAND)
-static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
- M_NAND_GPMC_CONFIG1,
- M_NAND_GPMC_CONFIG2,
- M_NAND_GPMC_CONFIG3,
- M_NAND_GPMC_CONFIG4,
- M_NAND_GPMC_CONFIG5,
- M_NAND_GPMC_CONFIG6, 0
-};
-#endif
-
void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
u32 size)
@@ -61,11 +50,34 @@
{
/* putting a blanket check on GPMC based on ZeBu for now */
gpmc_cfg = (struct gpmc *)GPMC_BASE;
-
-#ifdef CONFIG_CMD_NAND
- const u32 *gpmc_config = NULL;
- u32 base = 0;
+#if defined(CONFIG_NOR)
+/* configure GPMC for NOR */
+ const u32 gpmc_regs[GPMC_MAX_REG] = { STNOR_GPMC_CONFIG1,
+ STNOR_GPMC_CONFIG2,
+ STNOR_GPMC_CONFIG3,
+ STNOR_GPMC_CONFIG4,
+ STNOR_GPMC_CONFIG5,
+ STNOR_GPMC_CONFIG6,
+ STNOR_GPMC_CONFIG7
+ };
+ u32 size = GPMC_SIZE_16M;
+ u32 base = CONFIG_SYS_FLASH_BASE;
+#elif defined(CONFIG_NAND)
+/* configure GPMC for NAND */
+ const u32 gpmc_regs[GPMC_MAX_REG] = { M_NAND_GPMC_CONFIG1,
+ M_NAND_GPMC_CONFIG2,
+ M_NAND_GPMC_CONFIG3,
+ M_NAND_GPMC_CONFIG4,
+ M_NAND_GPMC_CONFIG5,
+ M_NAND_GPMC_CONFIG6,
+ 0
+ };
+ u32 size = GPMC_SIZE_256M;
+ u32 base = CONFIG_SYS_NAND_BASE;
+#else
+ const u32 gpmc_regs[GPMC_MAX_REG] = { 0, 0, 0, 0, 0, 0, 0 };
u32 size = 0;
+ u32 base = 0;
#endif
/* global settings */
writel(0x00000008, &gpmc_cfg->sysconfig);
@@ -81,12 +93,6 @@
*/
writel(0, &gpmc_cfg->cs[0].config7);
sdelay(1000);
-
-#ifdef CONFIG_CMD_NAND
- gpmc_config = gpmc_m_nand;
-
- base = PISMO1_NAND_BASE;
- size = PISMO1_NAND_SIZE;
- enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size);
-#endif
+ /* enable chip-select specific configurations */
+ enable_gpmc_cs_config(gpmc_regs, &gpmc_cfg->cs[0], base, size);
}
diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile
index 679c1a1..59f5352 100644
--- a/arch/arm/cpu/armv7/omap-common/Makefile
+++ b/arch/arm/cpu/armv7/omap-common/Makefile
@@ -18,7 +18,7 @@
endif
ifneq ($(CONFIG_OMAP54XX),)
-COBJS += pipe3-phy.o
+obj-y += pipe3-phy.o
obj-$(CONFIG_SCSI_AHCI_PLAT) += sata.o
endif
diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c
index bb77b5c..dfa3760 100644
--- a/arch/arm/cpu/armv7/omap-common/clocks-common.c
+++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c
@@ -779,7 +779,8 @@
static int gpi2c = 1;
if (gpi2c) {
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+ i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED,
+ CONFIG_SYS_OMAP24_I2C_SLAVE);
gpi2c = 0;
}
}
diff --git a/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds b/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
index 5e93b34..02aa129 100644
--- a/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
+++ b/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
@@ -33,6 +33,11 @@
.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
. = ALIGN(4);
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*_i2c_*)));
+ } >.sram
+
+ . = ALIGN(4);
__image_copy_end = .;
_end = .;
diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c
index 7d1f8d9..2922816 100644
--- a/arch/arm/cpu/armv7/omap3/board.c
+++ b/arch/arm/cpu/armv7/omap3/board.c
@@ -98,7 +98,7 @@
gpmc_init();
#endif
#ifdef CONFIG_SPL_I2C_SUPPORT
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+ i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
#endif
}
#endif /* CONFIG_SPL_BUILD */
diff --git a/arch/arm/cpu/armv7/omap3/clock.c b/arch/arm/cpu/armv7/omap3/clock.c
index ae9c4c3..1bc27bd 100644
--- a/arch/arm/cpu/armv7/omap3/clock.c
+++ b/arch/arm/cpu/armv7/omap3/clock.c
@@ -708,7 +708,7 @@
sr32(&prcm_base->iclken_per, 17, 1, 1);
#endif
-#ifdef CONFIG_DRIVER_OMAP34XX_I2C
+#ifdef CONFIG_SYS_I2C_OMAP34XX
/* Turn on all 3 I2C clocks */
sr32(&prcm_base->fclken1_core, 15, 3, 0x7);
sr32(&prcm_base->iclken1_core, 15, 3, 0x7); /* I2C1,2,3 = on */
diff --git a/arch/arm/cpu/armv7/rmobile/Makefile b/arch/arm/cpu/armv7/rmobile/Makefile
index 7b9d47e..2221999 100644
--- a/arch/arm/cpu/armv7/rmobile/Makefile
+++ b/arch/arm/cpu/armv7/rmobile/Makefile
@@ -14,10 +14,4 @@
obj-$(CONFIG_R8A7790) += lowlevel_init_ca15.o cpu_info-r8a7790.o pfc-r8a7790.o
obj-$(CONFIG_R8A7791) += lowlevel_init_ca15.o cpu_info-r8a7791.o pfc-r8a7791.o
obj-$(CONFIG_SH73A0) += lowlevel_init.o cpu_info-sh73a0.o pfc-sh73a0.o
-obj-$(CONFIG_TMU_TIMER) += sh_timer.o
-
-SRCS += $(obj)sh_timer.c
-# from arch/sh/lib/ directory
-$(obj)sh_timer.c:
- @rm -f $(obj)sh_timer.c
- ln -s $(SRCTREE)/arch/sh/lib/time.c $(obj)sh_timer.c
+obj-$(CONFIG_TMU_TIMER) += ../../../../sh/lib/time.o
diff --git a/arch/arm/include/asm/arch-am33xx/i2c.h b/arch/arm/include/asm/arch-am33xx/i2c.h
index 8bfa53f..8642c8f 100644
--- a/arch/arm/include/asm/arch-am33xx/i2c.h
+++ b/arch/arm/include/asm/arch-am33xx/i2c.h
@@ -4,8 +4,8 @@
*
* SPDX-License-Identifier: GPL-2.0+
*/
-#ifndef _I2C_H_
-#define _I2C_H_
+#ifndef _I2C_AM33XX_H_
+#define _I2C_AM33XX_H_
#define I2C_BASE1 0x44E0B000
#define I2C_BASE2 0x4802A000
@@ -62,4 +62,4 @@
#define I2C_IP_CLK 48000000
#define I2C_INTERNAL_SAMPLING_CLK 12000000
-#endif /* _I2C_H_ */
+#endif /* _I2C_AM33XX_H_ */
diff --git a/arch/arm/include/asm/arch-am33xx/mem.h b/arch/arm/include/asm/arch-am33xx/mem.h
index 983ea28..e7e8c58 100644
--- a/arch/arm/include/asm/arch-am33xx/mem.h
+++ b/arch/arm/include/asm/arch-am33xx/mem.h
@@ -68,9 +68,4 @@
#define PISMO2_NAND_CS0 7
#define PISMO2_NAND_CS1 8
-/* make it readable for the gpmc_init */
-#define PISMO1_NOR_BASE FLASH_BASE
-#define PISMO1_NAND_BASE CONFIG_SYS_NAND_BASE
-#define PISMO1_NAND_SIZE GPMC_SIZE_256M
-
#endif /* endif _MEM_H_ */
diff --git a/arch/arm/include/asm/arch-bcm2835/mbox.h b/arch/arm/include/asm/arch-bcm2835/mbox.h
index 24abe57..6b806ec 100644
--- a/arch/arm/include/asm/arch-bcm2835/mbox.h
+++ b/arch/arm/include/asm/arch-bcm2835/mbox.h
@@ -350,6 +350,7 @@
u32 top;
u32 bottom;
u32 left;
+ u32 right;
} resp;
} body;
};
diff --git a/arch/arm/include/asm/arch-omap3/dss.h b/arch/arm/include/asm/arch-omap3/dss.h
index ae0babf..8bf6b48 100644
--- a/arch/arm/include/asm/arch-omap3/dss.h
+++ b/arch/arm/include/asm/arch-omap3/dss.h
@@ -178,10 +178,11 @@
#define LCD_INTERFACE_24_BIT 3
/* Polarity */
-#define DSS_IVS (1 << 12)
-#define DSS_IHS (1 << 13)
-#define DSS_IPC (1 << 14)
-#define DSS_IEO (1 << 15)
+#define DSS_IVS (1 << 12)
+#define DSS_IHS (1 << 13)
+#define DSS_IPC (1 << 14)
+#define DSS_IEO (1 << 15)
+#define DSS_ONOFF (1 << 17)
/* GFX format */
#define GFXFORMAT_BITMAP1 (0x0 << 1)
diff --git a/arch/arm/include/asm/arch-am33xx/elm.h b/arch/arm/include/asm/omap_elm.h
similarity index 100%
rename from arch/arm/include/asm/arch-am33xx/elm.h
rename to arch/arm/include/asm/omap_elm.h
diff --git a/arch/arm/include/asm/omap_gpmc.h b/arch/arm/include/asm/omap_gpmc.h
index dd40cb6..d4143ec 100644
--- a/arch/arm/include/asm/omap_gpmc.h
+++ b/arch/arm/include/asm/omap_gpmc.h
@@ -68,4 +68,20 @@
}
#endif
+enum omap_ecc {
+ /* 1-bit ECC calculation by Software, Error detection by Software */
+ OMAP_ECC_HAM1_CODE_SW = 1, /* avoid un-initialized int can be 0x0 */
+ /* 1-bit ECC calculation by GPMC, Error detection by Software */
+ /* ECC layout compatible to legacy ROMCODE. */
+ OMAP_ECC_HAM1_CODE_HW,
+ /* 4-bit ECC calculation by GPMC, Error detection by Software */
+ OMAP_ECC_BCH4_CODE_HW_DETECTION_SW,
+ /* 4-bit ECC calculation by GPMC, Error detection by ELM */
+ OMAP_ECC_BCH4_CODE_HW,
+ /* 8-bit ECC calculation by GPMC, Error detection by Software */
+ OMAP_ECC_BCH8_CODE_HW_DETECTION_SW,
+ /* 8-bit ECC calculation by GPMC, Error detection by ELM */
+ OMAP_ECC_BCH8_CODE_HW,
+};
+
#endif /* __ASM_OMAP_GPMC_H */
diff --git a/arch/blackfin/cpu/bootrom-asm-offsets.awk b/arch/blackfin/cpu/bootrom-asm-offsets.awk
old mode 100755
new mode 100644
diff --git a/arch/blackfin/cpu/os_log.c b/arch/blackfin/cpu/os_log.c
index e1c8e29..2092d9e 100644
--- a/arch/blackfin/cpu/os_log.c
+++ b/arch/blackfin/cpu/os_log.c
@@ -12,12 +12,12 @@
#define OS_LOG_MAGIC_ADDR ((unsigned long *)0x4f0)
#define OS_LOG_PTR_ADDR ((char **)0x4f4)
-bool bfin_os_log_check(void)
+int bfin_os_log_check(void)
{
if (*OS_LOG_MAGIC_ADDR != OS_LOG_MAGIC)
- return false;
+ return 0;
*OS_LOG_MAGIC_ADDR = 0;
- return true;
+ return 1;
}
void bfin_os_log_dump(void)
diff --git a/arch/blackfin/include/asm/blackfin_local.h b/arch/blackfin/include/asm/blackfin_local.h
index ab31dcb..8ea8cde 100644
--- a/arch/blackfin/include/asm/blackfin_local.h
+++ b/arch/blackfin/include/asm/blackfin_local.h
@@ -51,7 +51,7 @@
# define bfin_revid() (bfin_read_CHIPID() >> 28)
-extern bool bfin_os_log_check(void);
+extern int bfin_os_log_check(void);
extern void bfin_os_log_dump(void);
extern void blackfin_icache_flush_range(const void *, const void *);
diff --git a/arch/microblaze/cpu/u-boot.lds b/arch/microblaze/cpu/u-boot.lds
index 3e6204d..fdad207 100644
--- a/arch/microblaze/cpu/u-boot.lds
+++ b/arch/microblaze/cpu/u-boot.lds
@@ -30,7 +30,7 @@
{
__data_start = .;
#ifdef CONFIG_OF_EMBED
- dts/libdts.o (.data)
+ dts/built-in.o (.data)
#endif
*(.data)
__data_end = .;
diff --git a/arch/mips/cpu/mips32/cache.S b/arch/mips/cpu/mips32/cache.S
index 12f656c..22bd844 100644
--- a/arch/mips/cpu/mips32/cache.S
+++ b/arch/mips/cpu/mips32/cache.S
@@ -20,15 +20,6 @@
#define RA t9
-/*
- * 16kB is the maximum size of instruction and data caches on MIPS 4K,
- * 64kB is on 4KE, 24K, 5K, etc. Set bigger size for convenience.
- *
- * Note that the above size is the maximum size of primary cache. U-Boot
- * doesn't have L2 cache support for now.
- */
-#define MIPS_MAX_CACHE_SIZE 0x10000
-
#define INDEX_BASE CKSEG0
.macro cache_op op addr
@@ -126,12 +117,85 @@
*/
NESTED(mips_cache_reset, 0, ra)
move RA, ra
- li t2, CONFIG_SYS_ICACHE_SIZE
- li t3, CONFIG_SYS_DCACHE_SIZE
+
+#if !defined(CONFIG_SYS_ICACHE_SIZE) || !defined(CONFIG_SYS_DCACHE_SIZE) || \
+ !defined(CONFIG_SYS_CACHELINE_SIZE)
+ /* read Config1 for use below */
+ mfc0 t5, CP0_CONFIG, 1
+#endif
+
+#ifdef CONFIG_SYS_CACHELINE_SIZE
+ li t7, CONFIG_SYS_CACHELINE_SIZE
li t8, CONFIG_SYS_CACHELINE_SIZE
+#else
+ /* Detect I-cache line size. */
+ srl t8, t5, MIPS_CONF1_IL_SHIFT
+ andi t8, t8, (MIPS_CONF1_IL >> MIPS_CONF1_IL_SHIFT)
+ beqz t8, 1f
+ li t6, 2
+ sllv t8, t6, t8
- li v0, MIPS_MAX_CACHE_SIZE
+1: /* Detect D-cache line size. */
+ srl t7, t5, MIPS_CONF1_DL_SHIFT
+ andi t7, t7, (MIPS_CONF1_DL >> MIPS_CONF1_DL_SHIFT)
+ beqz t7, 1f
+ li t6, 2
+ sllv t7, t6, t7
+1:
+#endif
+#ifdef CONFIG_SYS_ICACHE_SIZE
+ li t2, CONFIG_SYS_ICACHE_SIZE
+#else
+ /* Detect I-cache size. */
+ srl t6, t5, MIPS_CONF1_IS_SHIFT
+ andi t6, t6, (MIPS_CONF1_IS >> MIPS_CONF1_IS_SHIFT)
+ li t4, 32
+ xori t2, t6, 0x7
+ beqz t2, 1f
+ addi t6, t6, 1
+ sllv t4, t4, t6
+1: /* At this point t4 == I-cache sets. */
+ mul t2, t4, t8
+ srl t6, t5, MIPS_CONF1_IA_SHIFT
+ andi t6, t6, (MIPS_CONF1_IA >> MIPS_CONF1_IA_SHIFT)
+ addi t6, t6, 1
+ /* At this point t6 == I-cache ways. */
+ mul t2, t2, t6
+#endif
+
+#ifdef CONFIG_SYS_DCACHE_SIZE
+ li t3, CONFIG_SYS_DCACHE_SIZE
+#else
+ /* Detect D-cache size. */
+ srl t6, t5, MIPS_CONF1_DS_SHIFT
+ andi t6, t6, (MIPS_CONF1_DS >> MIPS_CONF1_DS_SHIFT)
+ li t4, 32
+ xori t3, t6, 0x7
+ beqz t3, 1f
+ addi t6, t6, 1
+ sllv t4, t4, t6
+1: /* At this point t4 == I-cache sets. */
+ mul t3, t4, t7
+ srl t6, t5, MIPS_CONF1_DA_SHIFT
+ andi t6, t6, (MIPS_CONF1_DA >> MIPS_CONF1_DA_SHIFT)
+ addi t6, t6, 1
+ /* At this point t6 == I-cache ways. */
+ mul t3, t3, t6
+#endif
+
+ /* Determine the largest L1 cache size */
+#if defined(CONFIG_SYS_ICACHE_SIZE) && defined(CONFIG_SYS_DCACHE_SIZE)
+#if CONFIG_SYS_ICACHE_SIZE > CONFIG_SYS_DCACHE_SIZE
+ li v0, CONFIG_SYS_ICACHE_SIZE
+#else
+ li v0, CONFIG_SYS_DCACHE_SIZE
+#endif
+#else
+ move v0, t2
+ sltu t1, t2, t3
+ movn v0, t3, t1
+#endif
/*
* Now clear that much memory starting from zero.
*/
@@ -163,7 +227,7 @@
* then initialize D-cache.
*/
move a1, t3
- move a2, t8
+ move a2, t7
PTR_LA v1, mips_init_dcache
jalr v1
diff --git a/arch/mips/cpu/mips32/cpu.c b/arch/mips/cpu/mips32/cpu.c
index 28d5c45..278865b 100644
--- a/arch/mips/cpu/mips32/cpu.c
+++ b/arch/mips/cpu/mips32/cpu.c
@@ -34,28 +34,89 @@
return 0;
}
+#ifdef CONFIG_SYS_CACHELINE_SIZE
+
+static inline unsigned long icache_line_size(void)
+{
+ return CONFIG_SYS_CACHELINE_SIZE;
+}
+
+static inline unsigned long dcache_line_size(void)
+{
+ return CONFIG_SYS_CACHELINE_SIZE;
+}
+
+#else /* !CONFIG_SYS_CACHELINE_SIZE */
+
+static inline unsigned long icache_line_size(void)
+{
+ unsigned long conf1, il;
+ conf1 = read_c0_config1();
+ il = (conf1 & MIPS_CONF1_IL) >> MIPS_CONF1_IL_SHIFT;
+ if (!il)
+ return 0;
+ return 2 << il;
+}
+
+static inline unsigned long dcache_line_size(void)
+{
+ unsigned long conf1, dl;
+ conf1 = read_c0_config1();
+ dl = (conf1 & MIPS_CONF1_DL) >> MIPS_CONF1_DL_SHIFT;
+ if (!dl)
+ return 0;
+ return 2 << dl;
+}
+
+#endif /* !CONFIG_SYS_CACHELINE_SIZE */
+
void flush_cache(ulong start_addr, ulong size)
{
- unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
- unsigned long addr = start_addr & ~(lsize - 1);
- unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
+ unsigned long ilsize = icache_line_size();
+ unsigned long dlsize = dcache_line_size();
+ unsigned long addr, aend;
/* aend will be miscalculated when size is zero, so we return here */
if (size == 0)
return;
+ addr = start_addr & ~(dlsize - 1);
+ aend = (start_addr + size - 1) & ~(dlsize - 1);
+
+ if (ilsize == dlsize) {
+ /* flush I-cache & D-cache simultaneously */
+ while (1) {
+ cache_op(HIT_WRITEBACK_INV_D, addr);
+ cache_op(HIT_INVALIDATE_I, addr);
+ if (addr == aend)
+ break;
+ addr += dlsize;
+ }
+ return;
+ }
+
+ /* flush D-cache */
while (1) {
cache_op(HIT_WRITEBACK_INV_D, addr);
+ if (addr == aend)
+ break;
+ addr += dlsize;
+ }
+
+ /* flush I-cache */
+ addr = start_addr & ~(ilsize - 1);
+ aend = (start_addr + size - 1) & ~(ilsize - 1);
+ while (1) {
cache_op(HIT_INVALIDATE_I, addr);
if (addr == aend)
break;
- addr += lsize;
+ addr += ilsize;
}
}
void flush_dcache_range(ulong start_addr, ulong stop)
{
- unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
+ unsigned long lsize = dcache_line_size();
unsigned long addr = start_addr & ~(lsize - 1);
unsigned long aend = (stop - 1) & ~(lsize - 1);
@@ -69,7 +130,7 @@
void invalidate_dcache_range(ulong start_addr, ulong stop)
{
- unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
+ unsigned long lsize = dcache_line_size();
unsigned long addr = start_addr & ~(lsize - 1);
unsigned long aend = (stop - 1) & ~(lsize - 1);
diff --git a/arch/mips/cpu/mips32/start.S b/arch/mips/cpu/mips32/start.S
index 70ad198..68e59b5 100644
--- a/arch/mips/cpu/mips32/start.S
+++ b/arch/mips/cpu/mips32/start.S
@@ -51,7 +51,7 @@
*/
.word CONFIG_SYS_XWAY_EBU_BOOTCFG
.word 0x0
-#elif defined(CONFIG_QEMU_MALTA)
+#elif defined(CONFIG_MALTA)
/*
* Linux expects the Board ID here.
*/
diff --git a/arch/mips/include/asm/malta.h b/arch/mips/include/asm/malta.h
index d4d44a2..9e7c045 100644
--- a/arch/mips/include/asm/malta.h
+++ b/arch/mips/include/asm/malta.h
@@ -1,23 +1,67 @@
/*
* Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2013 Imagination Technologies
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _MIPS_ASM_MALTA_H
#define _MIPS_ASM_MALTA_H
-#define MALTA_IO_PORT_BASE 0x18000000
+#define MALTA_GT_BASE 0x1be00000
+#define MALTA_GT_PCIIO_BASE 0x18000000
+#define MALTA_GT_UART0_BASE (MALTA_GT_PCIIO_BASE + 0x3f8)
-#define MALTA_UART_BASE (MALTA_IO_PORT_BASE + 0x3f8)
+#define MALTA_MSC01_BIU_BASE 0x1bc80000
+#define MALTA_MSC01_PCI_BASE 0x1bd00000
+#define MALTA_MSC01_PBC_BASE 0x1bd40000
+#define MALTA_MSC01_IP1_BASE 0x1bc00000
+#define MALTA_MSC01_IP1_SIZE 0x00400000
+#define MALTA_MSC01_IP2_BASE1 0x10000000
+#define MALTA_MSC01_IP2_SIZE1 0x08000000
+#define MALTA_MSC01_IP2_BASE2 0x18000000
+#define MALTA_MSC01_IP2_SIZE2 0x04000000
+#define MALTA_MSC01_IP3_BASE 0x1c000000
+#define MALTA_MSC01_IP3_SIZE 0x04000000
+#define MALTA_MSC01_PCIMEM_BASE 0x10000000
+#define MALTA_MSC01_PCIMEM_SIZE 0x10000000
+#define MALTA_MSC01_PCIMEM_MAP 0x10000000
+#define MALTA_MSC01_PCIIO_BASE 0x1b000000
+#define MALTA_MSC01_PCIIO_SIZE 0x00800000
+#define MALTA_MSC01_PCIIO_MAP 0x00000000
+#define MALTA_MSC01_UART0_BASE (MALTA_MSC01_PCIIO_BASE + 0x3f8)
-#define MALTA_GT_BASE 0x1be00000
+#define MALTA_ASCIIWORD 0x1f000410
+#define MALTA_ASCIIPOS0 0x1f000418
+#define MALTA_ASCIIPOS1 0x1f000420
+#define MALTA_ASCIIPOS2 0x1f000428
+#define MALTA_ASCIIPOS3 0x1f000430
+#define MALTA_ASCIIPOS4 0x1f000438
+#define MALTA_ASCIIPOS5 0x1f000440
+#define MALTA_ASCIIPOS6 0x1f000448
+#define MALTA_ASCIIPOS7 0x1f000450
-#define MALTA_RESET_BASE 0x1f000500
-#define GORESET 0x42
+#define MALTA_RESET_BASE 0x1f000500
+#define GORESET 0x42
-#define MALTA_FLASH_BASE 0x1fc00000
+#define MALTA_FLASH_BASE 0x1e000000
+
+#define MALTA_REVISION 0x1fc00010
+#define MALTA_REVISION_CORID_SHF 10
+#define MALTA_REVISION_CORID_MSK (0x3f << MALTA_REVISION_CORID_SHF)
+#define MALTA_REVISION_CORID_CORE_LV 1
+#define MALTA_REVISION_CORID_CORE_FPGA6 14
+
+#define PCI_CFG_PIIX4_PIRQRCA 0x60
+#define PCI_CFG_PIIX4_PIRQRCB 0x61
+#define PCI_CFG_PIIX4_PIRQRCC 0x62
+#define PCI_CFG_PIIX4_PIRQRCD 0x63
+#define PCI_CFG_PIIX4_SERIRQC 0x64
+#define PCI_CFG_PIIX4_GENCFG 0xb0
+
+#define PCI_CFG_PIIX4_SERIRQC_EN (1 << 7)
+#define PCI_CFG_PIIX4_SERIRQC_CONT (1 << 6)
+
+#define PCI_CFG_PIIX4_GENCFG_SERIRQ (1 << 16)
#endif /* _MIPS_ASM_MALTA_H */
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index be7e5c6..3571e4f 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -494,11 +494,17 @@
#define MIPS_CONF1_PC (_ULCAST_(1) << 4)
#define MIPS_CONF1_MD (_ULCAST_(1) << 5)
#define MIPS_CONF1_C2 (_ULCAST_(1) << 6)
+#define MIPS_CONF1_DA_SHIFT 7
#define MIPS_CONF1_DA (_ULCAST_(7) << 7)
+#define MIPS_CONF1_DL_SHIFT 10
#define MIPS_CONF1_DL (_ULCAST_(7) << 10)
+#define MIPS_CONF1_DS_SHIFT 13
#define MIPS_CONF1_DS (_ULCAST_(7) << 13)
+#define MIPS_CONF1_IA_SHIFT 16
#define MIPS_CONF1_IA (_ULCAST_(7) << 16)
+#define MIPS_CONF1_IL_SHIFT 19
#define MIPS_CONF1_IL (_ULCAST_(7) << 19)
+#define MIPS_CONF1_IS_SHIFT 22
#define MIPS_CONF1_IS (_ULCAST_(7) << 22)
#define MIPS_CONF1_TLBS (_ULCAST_(63)<< 25)
diff --git a/arch/mips/lib/bootm.c b/arch/mips/lib/bootm.c
index 66340ea..71bb0d2 100644
--- a/arch/mips/lib/bootm.c
+++ b/arch/mips/lib/bootm.c
@@ -17,10 +17,10 @@
#define LINUX_MAX_ENVS 256
#define LINUX_MAX_ARGS 256
-#if defined(CONFIG_QEMU_MALTA)
-#define mips_boot_qemu_malta 1
+#if defined(CONFIG_MALTA)
+#define mips_boot_malta 1
#else
-#define mips_boot_qemu_malta 0
+#define mips_boot_malta 0
#endif
static int linux_argc;
@@ -139,7 +139,7 @@
strcpy(linux_env_p, env_name);
linux_env_p += strlen(env_name);
- if (mips_boot_qemu_malta) {
+ if (mips_boot_malta) {
linux_env_p++;
linux_env[++linux_env_idx] = linux_env_p;
} else {
@@ -196,8 +196,10 @@
if (cp)
linux_env_set("eth1addr", cp);
- if (mips_boot_qemu_malta)
- linux_env_set("modetty0", "38400n8r");
+ if (mips_boot_malta) {
+ sprintf(env_buf, "%un8r", gd->baudrate);
+ linux_env_set("modetty0", env_buf);
+ }
}
static void boot_jump_linux(bootm_headers_t *images)
@@ -210,7 +212,7 @@
bootstage_mark(BOOTSTAGE_ID_RUN_OS);
- if (mips_boot_qemu_malta)
+ if (mips_boot_malta)
linux_extra = gd->ram_size;
/* we assume that the kernel is in place */
diff --git a/arch/powerpc/cpu/Makefile b/arch/powerpc/cpu/Makefile
new file mode 100644
index 0000000..d630abe
--- /dev/null
+++ b/arch/powerpc/cpu/Makefile
@@ -0,0 +1,3 @@
+ifneq ($(filter mpc83xx mpc85xx mpc86xx,$(CPU)),)
+obj-y += mpc8xxx/
+endif
diff --git a/arch/powerpc/cpu/mpc512x/Makefile b/arch/powerpc/cpu/mpc512x/Makefile
index f770350..a4934ef 100644
--- a/arch/powerpc/cpu/mpc512x/Makefile
+++ b/arch/powerpc/cpu/mpc512x/Makefile
@@ -4,8 +4,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-$(shell mkdir -p $(OBJTREE)/board/freescale/common)
-
extra-y = start.o
obj-y := cpu.o
obj-y += traps.o
diff --git a/arch/powerpc/cpu/mpc824x/.gitignore b/arch/powerpc/cpu/mpc824x/.gitignore
deleted file mode 100644
index 2d79931..0000000
--- a/arch/powerpc/cpu/mpc824x/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-/bedbug_603e.c
diff --git a/arch/powerpc/cpu/mpc824x/Makefile b/arch/powerpc/cpu/mpc824x/Makefile
index 67b0d17..2c8be92 100644
--- a/arch/powerpc/cpu/mpc824x/Makefile
+++ b/arch/powerpc/cpu/mpc824x/Makefile
@@ -5,15 +5,7 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)drivers/epic $(obj)drivers/i2c)
-endif
-
extra-y = start.o
obj-y = traps.o cpu.o cpu_init.o interrupts.o speed.o \
drivers/epic/epic1.o drivers/i2c/i2c.o pci.o
-obj-y += bedbug_603e.o
-
-SRCS += $(obj)bedbug_603e.c
-$(obj)bedbug_603e.c:
- ln -sf $(src)../mpc8260/bedbug_603e.c $(obj)bedbug_603e.c
+obj-y += ../mpc8260/bedbug_603e.o
diff --git a/arch/powerpc/cpu/mpc824x/cpu_init.c b/arch/powerpc/cpu/mpc824x/cpu_init.c
index 37d796e..47ac18e 100644
--- a/arch/powerpc/cpu/mpc824x/cpu_init.c
+++ b/arch/powerpc/cpu/mpc824x/cpu_init.c
@@ -52,7 +52,7 @@
CONFIG_WRITE_HALFWORD(PCICR, 0x06); /* Bus Master, respond to PCI memory space acesses*/
/* CONFIG_WRITE_HALFWORD(PCISR, 0xffff); */ /*reset PCISR*/
-#if defined(CONFIG_MUSENKI) || defined(CONFIG_PN62)
+#if defined(CONFIG_MUSENKI)
/* Why is this here, you ask? Try, just try setting 0x8000
* in PCIACR with CONFIG_WRITE_HALFWORD()
* this one was a stumper, and we are annoyed
@@ -142,9 +142,7 @@
CONFIG_READ_WORD(PICR2, val);
val= val & ~ (PICR2_CF_SNOOP_WS_MASK | PICR2_CF_APHASE_WS_MASK); /*mask off waitstate bits*/
-#ifndef CONFIG_PN62
val |= PICR2_CF_SNOOP_WS_1WS | PICR2_CF_APHASE_WS_1WS; /*1 wait state*/
-#endif
CONFIG_WRITE_WORD(PICR2, val);
CONFIG_WRITE_WORD(EUMBBAR, CONFIG_SYS_EUMB_ADDR);
@@ -186,7 +184,7 @@
* should define CONFIG_SYS_ACTORW to 0 if they don't want to set it, or even, if
* its not set, we define it to zero in this file
*/
-#if defined(CONFIG_CU824) || defined(CONFIG_PN62)
+#if defined(CONFIG_CU824)
CONFIG_WRITE_WORD(MCCR4,
(CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) |
(CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) |
diff --git a/arch/powerpc/cpu/mpc83xx/Makefile b/arch/powerpc/cpu/mpc83xx/Makefile
index b7142f0..c345dd6 100644
--- a/arch/powerpc/cpu/mpc83xx/Makefile
+++ b/arch/powerpc/cpu/mpc83xx/Makefile
@@ -38,21 +38,11 @@
# Stub implementations of cache management functions for USB
obj-y += cache.o
-ifdef CONFIG_FSL_DDR2
-obj-$(CONFIG_MPC8349) += ddr-gen2.o
-SRCS += $(obj)ddr-gen2.c
+ifdef CONFIG_SYS_FSL_DDR2
+obj-$(CONFIG_MPC8349) += $(SRCTREE)/drivers/ddr/fsl/mpc85xx_ddr_gen2.o
else
obj-y += spd_sdram.o
endif
-obj-$(CONFIG_FSL_DDR2) += law.o
+obj-$(CONFIG_SYS_FSL_DDR2) += law.o
endif # not minimal
-
-$(obj)ddr-gen1.c:
- ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/ddr-gen1.c $(obj)ddr-gen1.c
-
-$(obj)ddr-gen2.c:
- ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/ddr-gen2.c $(obj)ddr-gen2.c
-
-$(obj)ddr-gen3.c:
- ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/ddr-gen3.c $(obj)ddr-gen3.c
diff --git a/arch/powerpc/cpu/mpc83xx/ecc.c b/arch/powerpc/cpu/mpc83xx/ecc.c
index 120b37b..985a024 100644
--- a/arch/powerpc/cpu/mpc83xx/ecc.c
+++ b/arch/powerpc/cpu/mpc83xx/ecc.c
@@ -15,8 +15,8 @@
void ecc_print_status(void)
{
immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-#ifdef CONFIG_FSL_DDR2
- ccsr_ddr_t *ddr = &immap->ddr;
+#ifdef CONFIG_SYS_FSL_DDR2
+ struct ccsr_ddr __iomem *ddr = &immap->ddr;
#else
ddr83xx_t *ddr = &immap->ddr;
#endif
@@ -99,8 +99,8 @@
int do_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-#ifdef CONFIG_FSL_DDR2
- ccsr_ddr_t *ddr = &immap->ddr;
+#ifdef CONFIG_SYS_FSL_DDR2
+ struct ccsr_ddr __iomem *ddr = &immap->ddr;
#else
ddr83xx_t *ddr = &immap->ddr;
#endif
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index 50ddb50..ef7637a 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -29,48 +29,6 @@
obj-$(CONFIG_CMD_ERRATA) += cmd_errata.o
obj-$(CONFIG_CPM2) += commproc.o
-# supports ddr1
-obj-$(CONFIG_MPC8540) += ddr-gen1.o
-obj-$(CONFIG_MPC8560) += ddr-gen1.o
-obj-$(CONFIG_MPC8541) += ddr-gen1.o
-obj-$(CONFIG_MPC8555) += ddr-gen1.o
-
-# supports ddr1/2
-obj-$(CONFIG_MPC8548) += ddr-gen2.o
-obj-$(CONFIG_MPC8568) += ddr-gen2.o
-obj-$(CONFIG_MPC8544) += ddr-gen2.o
-
-# supports ddr1/2/3
-obj-$(CONFIG_PPC_C29X) += ddr-gen3.o
-obj-$(CONFIG_MPC8572) += ddr-gen3.o
-obj-$(CONFIG_MPC8536) += ddr-gen3.o
-obj-$(CONFIG_MPC8569) += ddr-gen3.o
-obj-$(CONFIG_P1010) += ddr-gen3.o
-obj-$(CONFIG_P1011) += ddr-gen3.o
-obj-$(CONFIG_P1012) += ddr-gen3.o
-obj-$(CONFIG_P1013) += ddr-gen3.o
-obj-$(CONFIG_P1014) += ddr-gen3.o
-obj-$(CONFIG_P1020) += ddr-gen3.o
-obj-$(CONFIG_P1021) += ddr-gen3.o
-obj-$(CONFIG_P1022) += ddr-gen3.o
-obj-$(CONFIG_P1023) += ddr-gen3.o
-obj-$(CONFIG_P1024) += ddr-gen3.o
-obj-$(CONFIG_P1025) += ddr-gen3.o
-obj-$(CONFIG_P2010) += ddr-gen3.o
-obj-$(CONFIG_P2020) += ddr-gen3.o
-obj-$(CONFIG_PPC_P2041) += ddr-gen3.o
-obj-$(CONFIG_PPC_P3041) += ddr-gen3.o
-obj-$(CONFIG_PPC_P4080) += ddr-gen3.o
-obj-$(CONFIG_PPC_P5020) += ddr-gen3.o
-obj-$(CONFIG_PPC_P5040) += ddr-gen3.o
-obj-$(CONFIG_PPC_T4240) += ddr-gen3.o
-obj-$(CONFIG_PPC_T4160) += ddr-gen3.o
-obj-$(CONFIG_PPC_B4420) += ddr-gen3.o
-obj-$(CONFIG_PPC_B4860) += ddr-gen3.o
-obj-$(CONFIG_BSC9131) += ddr-gen3.o
-obj-$(CONFIG_BSC9132) += ddr-gen3.o
-obj-$(CONFIG_PPC_T1040) += ddr-gen3.o
-
obj-$(CONFIG_CPM2) += ether_fcc.o
obj-$(CONFIG_OF_LIBFDT) += fdt.o
obj-$(CONFIG_FSL_CORENET) += liodn.o
@@ -89,6 +47,12 @@
obj-$(CONFIG_PPC_B4420) += b4860_ids.o
obj-$(CONFIG_PPC_B4860) += b4860_ids.o
obj-$(CONFIG_PPC_T1040) += t1040_ids.o
+obj-$(CONFIG_PPC_T1042) += t1040_ids.o
+obj-$(CONFIG_PPC_T1020) += t1040_ids.o
+obj-$(CONFIG_PPC_T1022) += t1040_ids.o
+obj-$(CONFIG_PPC_T2080) += t2080_ids.o
+obj-$(CONFIG_PPC_T2081) += t2080_ids.o
+
obj-$(CONFIG_QE) += qe_io.o
obj-$(CONFIG_CPM2) += serial_scc.o
@@ -128,6 +92,11 @@
obj-$(CONFIG_PPC_B4860) += b4860_serdes.o
obj-$(CONFIG_BSC9132) += bsc9132_serdes.o
obj-$(CONFIG_PPC_T1040) += t1040_serdes.o
+obj-$(CONFIG_PPC_T1042) += t1040_serdes.o
+obj-$(CONFIG_PPC_T1020) += t1040_serdes.o
+obj-$(CONFIG_PPC_T1022) += t1040_serdes.o
+obj-$(CONFIG_PPC_T2080) += t2080_serdes.o
+obj-$(CONFIG_PPC_T2081) += t2080_serdes.o
obj-y += cpu.o
obj-y += cpu_init.o
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 1a0196c..3e99b07 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -17,12 +17,12 @@
#include <asm/cache.h>
#include <asm/io.h>
#include <asm/mmu.h>
-#include <asm/fsl_ifc.h>
+#include <fsl_ifc.h>
#include <asm/fsl_law.h>
#include <asm/fsl_lbc.h>
#include <post.h>
#include <asm/processor.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -416,7 +416,7 @@
int i, j, k, m;
u8 *p_8;
u32 *p_32;
- ccsr_ddr_t *ddr[CONFIG_NUM_DDR_CONTROLLERS];
+ struct ccsr_ddr __iomem *ddr[CONFIG_NUM_DDR_CONTROLLERS];
generic_spd_eeprom_t
spd[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR];
@@ -453,21 +453,21 @@
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
switch (i) {
case 0:
- ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
+ ddr[i] = (void *)CONFIG_SYS_FSL_DDR_ADDR;
break;
-#if defined(CONFIG_SYS_MPC8xxx_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
+#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
case 1:
- ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR2_ADDR;
+ ddr[i] = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
break;
#endif
-#if defined(CONFIG_SYS_MPC8xxx_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
+#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
case 2:
- ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR3_ADDR;
+ ddr[i] = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
break;
#endif
-#if defined(CONFIG_SYS_MPC8xxx_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
+#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
case 3:
- ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR4_ADDR;
+ ddr[i] = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
break;
#endif
default:
@@ -482,7 +482,7 @@
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF);
puts("\n");
- for (k = 0; k < sizeof(ccsr_ddr_t)/4; k++) {
+ for (k = 0; k < sizeof(struct ccsr_ddr)/4; k++) {
m = 0;
printf("%6d (0x%04x)", k * 4, k * 4);
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 2ccd9c7..33bc900 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -586,6 +586,7 @@
{
int off;
int val;
+ int len;
sys_info_t sysinfo;
/* delete crypto node if not on an E-processor */
@@ -615,8 +616,8 @@
get_sys_info(&sysinfo);
off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
while (off != -FDT_ERR_NOTFOUND) {
- u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
- val = cpu_to_fdt32(sysinfo.freq_processor[*reg]);
+ u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", &len);
+ val = cpu_to_fdt32(sysinfo.freq_processor[(*reg) / (len / 4)]);
fdt_setprop(blob, off, "clock-frequency", &val, 4);
off = fdt_node_offset_by_prop_value(blob, off, "device_type",
"cpu", 4);
diff --git a/arch/powerpc/cpu/mpc85xx/liodn.c b/arch/powerpc/cpu/mpc85xx/liodn.c
index 4b00da9..19e130e 100644
--- a/arch/powerpc/cpu/mpc85xx/liodn.c
+++ b/arch/powerpc/cpu/mpc85xx/liodn.c
@@ -239,9 +239,9 @@
#endif
#define CONFIG_SYS_MAX_PCI_EPS 8
-#define CONFIG_SYS_PCI_EP_LIODN_START 256
-static void fdt_fixup_pci_liodn_offsets(void *fdt, const char *compat)
+static void fdt_fixup_pci_liodn_offsets(void *fdt, const char *compat,
+ int ep_liodn_start)
{
int off, pci_idx = 0, pci_cnt = 0, i, rc;
const uint32_t *base_liodn;
@@ -271,7 +271,7 @@
continue;
}
for (i = 0; i < CONFIG_SYS_MAX_PCI_EPS; i++)
- liodn_offs[i + 1] = CONFIG_SYS_PCI_EP_LIODN_START +
+ liodn_offs[i + 1] = ep_liodn_start +
i * pci_cnt + pci_idx - *base_liodn;
rc = fdt_setprop(fdt, off, "fsl,liodn-offset-list",
liodn_offs, sizeof(liodn_offs));
@@ -338,5 +338,22 @@
fdt_fixup_liodn_tbl(blob, rman_liodn_tbl, rman_liodn_tbl_sz);
#endif
- fdt_fixup_pci_liodn_offsets(blob, "fsl,qoriq-pcie-v2.4");
+ ccsr_pcix_t *pcix = (ccsr_pcix_t *)CONFIG_SYS_PCIE1_ADDR;
+ int pci_ver = pcix->ipver1 & 0xffff, liodn_base = 0;
+
+ if (pci_ver >= 0x0204) {
+ if (pci_ver >= 0x0300)
+ liodn_base = 1024;
+ else
+ liodn_base = 256;
+ }
+
+ if (liodn_base) {
+ char compat[32];
+
+ sprintf(compat, "fsl,qoriq-pcie-v%d.%d",
+ (pci_ver & 0xff00) >> 8, pci_ver & 0xff);
+ fdt_fixup_pci_liodn_offsets(blob, compat, liodn_base);
+ fdt_fixup_pci_liodn_offsets(blob, "fsl,qoriq-pcie", liodn_base);
+ }
}
diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c
index 5f198eb..88c8e65 100644
--- a/arch/powerpc/cpu/mpc85xx/mp.c
+++ b/arch/powerpc/cpu/mpc85xx/mp.c
@@ -11,7 +11,7 @@
#include <asm/io.h>
#include <asm/mmu.h>
#include <asm/fsl_law.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include "mp.h"
DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index d08a8d2..1a58a19 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -122,7 +122,7 @@
sys_info->freq_processor[cpu] =
freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
}
-#ifdef CONFIG_PPC_B4860
+#if defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_T2080)
#define FM1_CLK_SEL 0xe0000000
#define FM1_CLK_SHIFT 29
#else
diff --git a/arch/powerpc/cpu/mpc85xx/spl_minimal.c b/arch/powerpc/cpu/mpc85xx/spl_minimal.c
index 199b33e..9e4c6c9 100644
--- a/arch/powerpc/cpu/mpc85xx/spl_minimal.c
+++ b/arch/powerpc/cpu/mpc85xx/spl_minimal.c
@@ -7,7 +7,7 @@
#include <common.h>
#include <asm/processor.h>
#include <asm/global_data.h>
-#include <asm/fsl_ifc.h>
+#include <fsl_ifc.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/powerpc/cpu/mpc85xx/t2080_ids.c b/arch/powerpc/cpu/mpc85xx/t2080_ids.c
new file mode 100644
index 0000000..068e1f2
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/t2080_ids.c
@@ -0,0 +1,142 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+
+#ifdef CONFIG_SYS_DPAA_QBMAN
+struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
+ /* dqrr liodn, frame data liodn, liodn off, sdest */
+ SET_QP_INFO(1, 27, 1, 0),
+ SET_QP_INFO(2, 28, 1, 0),
+ SET_QP_INFO(3, 29, 1, 1),
+ SET_QP_INFO(4, 30, 1, 1),
+ SET_QP_INFO(5, 31, 1, 2),
+ SET_QP_INFO(6, 32, 1, 2),
+ SET_QP_INFO(7, 33, 1, 3),
+ SET_QP_INFO(8, 34, 1, 3),
+ SET_QP_INFO(9, 35, 1, 0),
+ SET_QP_INFO(10, 36, 1, 0),
+ SET_QP_INFO(11, 37, 1, 1),
+ SET_QP_INFO(12, 38, 1, 1),
+ SET_QP_INFO(13, 39, 1, 2),
+ SET_QP_INFO(14, 40, 1, 2),
+ SET_QP_INFO(15, 41, 1, 3),
+ SET_QP_INFO(16, 42, 1, 3),
+ SET_QP_INFO(17, 43, 1, 0),
+ SET_QP_INFO(18, 44, 1, 0),
+};
+#endif
+
+#ifdef CONFIG_SYS_SRIO
+struct srio_liodn_id_table srio_liodn_tbl[] = {
+ SET_SRIO_LIODN_BASE(1, 307),
+ SET_SRIO_LIODN_BASE(2, 387),
+};
+int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl);
+#endif
+
+struct liodn_id_table liodn_tbl[] = {
+#ifdef CONFIG_SYS_DPAA_QBMAN
+ SET_QMAN_LIODN(62),
+ SET_BMAN_LIODN(63),
+#endif
+
+ SET_SDHC_LIODN(1, 552),
+
+ SET_PME_LIODN(117),
+
+ SET_USB_LIODN(1, "fsl-usb2-mph", 553),
+ SET_USB_LIODN(2, "fsl-usb2-dr", 554),
+
+ SET_SATA_LIODN(1, 555),
+ SET_SATA_LIODN(2, 556),
+
+ SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148),
+ SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 228),
+ SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 308),
+ SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 388),
+
+ SET_DMA_LIODN(1, 147),
+ SET_DMA_LIODN(2, 227),
+ SET_DMA_LIODN(3, 226),
+
+ SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0),
+ SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0),
+ SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0),
+ SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0),
+
+#ifdef CONFIG_SYS_PMAN
+ SET_PMAN_LIODN(1, 513),
+ SET_PMAN_LIODN(2, 514),
+ SET_PMAN_LIODN(3, 515),
+#endif
+
+ /* SET_NEXUS_LIODN(557), -- not yet implemented */
+};
+int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+struct liodn_id_table fman1_liodn_tbl[] = {
+ SET_FMAN_RX_1G_LIODN(1, 0, 88),
+ SET_FMAN_RX_1G_LIODN(1, 1, 89),
+ SET_FMAN_RX_1G_LIODN(1, 2, 90),
+ SET_FMAN_RX_1G_LIODN(1, 3, 91),
+ SET_FMAN_RX_1G_LIODN(1, 4, 92),
+ SET_FMAN_RX_1G_LIODN(1, 5, 93),
+ SET_FMAN_RX_10G_LIODN(1, 0, 94),
+ SET_FMAN_RX_10G_LIODN(1, 1, 95),
+};
+int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl);
+#endif
+
+struct liodn_id_table sec_liodn_tbl[] = {
+ SET_SEC_JR_LIODN_ENTRY(0, 454, 458),
+ SET_SEC_JR_LIODN_ENTRY(1, 455, 459),
+ SET_SEC_JR_LIODN_ENTRY(2, 456, 460),
+ SET_SEC_JR_LIODN_ENTRY(3, 457, 461),
+ SET_SEC_RTIC_LIODN_ENTRY(a, 453),
+ SET_SEC_RTIC_LIODN_ENTRY(b, 549),
+ SET_SEC_RTIC_LIODN_ENTRY(c, 550),
+ SET_SEC_RTIC_LIODN_ENTRY(d, 551),
+ SET_SEC_DECO_LIODN_ENTRY(0, 541, 610),
+ SET_SEC_DECO_LIODN_ENTRY(1, 542, 611),
+ SET_SEC_DECO_LIODN_ENTRY(2, 543, 612),
+ SET_SEC_DECO_LIODN_ENTRY(3, 544, 613),
+ SET_SEC_DECO_LIODN_ENTRY(4, 545, 614),
+ SET_SEC_DECO_LIODN_ENTRY(5, 546, 615),
+ SET_SEC_DECO_LIODN_ENTRY(6, 547, 616),
+ SET_SEC_DECO_LIODN_ENTRY(7, 548, 617),
+};
+int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl);
+
+#ifdef CONFIG_SYS_DPAA_RMAN
+struct liodn_id_table rman_liodn_tbl[] = {
+ /* Set RMan block 0-3 liodn offset */
+ SET_RMAN_LIODN(0, 6),
+ SET_RMAN_LIODN(1, 7),
+ SET_RMAN_LIODN(2, 8),
+ SET_RMAN_LIODN(3, 9),
+};
+int rman_liodn_tbl_sz = ARRAY_SIZE(rman_liodn_tbl);
+#endif
+
+struct liodn_id_table liodn_bases[] = {
+#ifdef CONFIG_SYS_DPAA_DCE
+ [FSL_HW_PORTAL_DCE] = SET_LIODN_BASE_2(618, 694),
+#endif
+ [FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(462, 558),
+#ifdef CONFIG_SYS_DPAA_FMAN
+ [FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(973),
+#endif
+#ifdef CONFIG_SYS_DPAA_PME
+ [FSL_HW_PORTAL_PME] = SET_LIODN_BASE_2(770, 846),
+#endif
+#ifdef CONFIG_SYS_DPAA_RMAN
+ [FSL_HW_PORTAL_RMAN] = SET_LIODN_BASE_1(922),
+#endif
+};
diff --git a/arch/powerpc/cpu/mpc85xx/t2080_serdes.c b/arch/powerpc/cpu/mpc85xx/t2080_serdes.c
new file mode 100644
index 0000000..f2fbdeb
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/t2080_serdes.c
@@ -0,0 +1,208 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * Shengzhou Liu <Shengzhou.Liu@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_serdes.h>
+#include <asm/processor.h>
+#include "fsl_corenet2_serdes.h"
+
+struct serdes_config {
+ u32 protocol;
+ u8 lanes[SRDS_MAX_LANES];
+};
+
+static const struct serdes_config serdes1_cfg_tbl[] = {
+ /* SerDes 1 */
+ {0x6E, {XFI_FM1_MAC9, XFI_FM1_MAC10,
+ SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ PCIE4, PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+ {0xBC, {PCIE3, PCIE3, SGMII_FM1_DTSEC1,
+ SGMII_FM1_DTSEC2, PCIE4, PCIE4, PCIE4, PCIE4} },
+ {0xC8, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
+ SGMII_FM1_DTSEC2, PCIE4, PCIE4,
+ SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+ {0xD6, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
+ SGMII_FM1_DTSEC2, PCIE4, PCIE4,
+ SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+ {0xDE, {PCIE3, PCIE3, PCIE3, PCIE3,
+ PCIE4, PCIE1, PCIE2, SGMII_FM1_DTSEC6} },
+ {0xE0, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4,
+ PCIE1, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+ {0xF2, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
+ SGMII_FM1_DTSEC2, PCIE4, PCIE1, PCIE2, SGMII_FM1_DTSEC6} },
+ {0xF8, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
+ SGMII_FM1_DTSEC2, PCIE4, PCIE1, PCIE2, SGMII_FM1_DTSEC6} },
+ {0xFA, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
+ SGMII_FM1_DTSEC2, PCIE4, PCIE1,
+ SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+ {0x6C, {XFI_FM1_MAC9, XFI_FM1_MAC10,
+ SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ PCIE4, PCIE4, PCIE4, PCIE4} },
+#if defined(CONFIG_PPC_T2080)
+ {0x1C, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
+ SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+ SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+ {0x95, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
+ SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+ SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+ {0xA2, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
+ SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+ SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+ {0x94, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
+ SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+ SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+ {0x51, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
+ XAUI_FM1_MAC9, XAUI_FM1_MAC9,
+ PCIE4, SGMII_FM1_DTSEC4,
+ SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+ {0x5F, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+ HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+ PCIE4, SGMII_FM1_DTSEC4,
+ SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+ {0x65, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+ HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+ PCIE4, SGMII_FM1_DTSEC4,
+ SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+ {0x6B, {XFI_FM1_MAC9, XFI_FM1_MAC10,
+ XFI_FM1_MAC1, XFI_FM1_MAC2,
+ PCIE4, SGMII_FM1_DTSEC4,
+ SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+ {0x6D, {XFI_FM1_MAC9, XFI_FM1_MAC10,
+ SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ PCIE4, PCIE4, PCIE4, PCIE4} },
+ {0x71, {XFI_FM1_MAC9, XFI_FM1_MAC10,
+ SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4,
+ SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+ {0xA6, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
+ SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4,
+ PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+ {0x8E, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
+ SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4,
+ PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+ {0x8F, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
+ SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4,
+ PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+ {0x82, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
+ SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ PCIE4, PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+ {0x83, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
+ SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ PCIE4, PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+ {0xA4, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
+ SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ PCIE4, PCIE4, PCIE4, PCIE4} },
+ {0x96, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
+ SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ PCIE4, PCIE4, PCIE4, PCIE4} },
+ {0x8A, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
+ SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ PCIE4, PCIE4, PCIE4, PCIE4} },
+ {0x67, {XFI_FM1_MAC9, XFI_FM1_MAC10,
+ XFI_FM1_MAC1, XFI_FM1_MAC2,
+ PCIE4, PCIE4, PCIE4, PCIE4} },
+ {0xAB, {PCIE3, PCIE3, PCIE3, PCIE3,
+ PCIE4, PCIE4, PCIE4, PCIE4} },
+ {0xDA, {PCIE3, PCIE3, PCIE3, PCIE3,
+ PCIE3, PCIE3, PCIE3, PCIE3} },
+ {0xD9, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
+ SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
+ SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+ {0xD3, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
+ SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
+ SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+ {0xCB, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
+ SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
+ SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+ {0xD8, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
+ SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
+ SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+ {0x66, {XFI_FM1_MAC9, XFI_FM1_MAC10,
+ XFI_FM1_MAC1, XFI_FM1_MAC2,
+ PCIE4, PCIE4, PCIE4, PCIE4} },
+
+#elif defined(CONFIG_PPC_T2081)
+ {0xAA, {PCIE3, PCIE3, PCIE3, PCIE3,
+ PCIE4, PCIE4, PCIE4, PCIE4} },
+ {0xCA, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
+ SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
+ SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+ {0x70, {XFI_FM1_MAC9, XFI_FM1_MAC10, SGMII_FM1_DTSEC1,
+ SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
+ SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+#endif
+ {}
+};
+
+#ifndef CONFIG_PPC_T2081
+static const struct serdes_config serdes2_cfg_tbl[] = {
+ /* SerDes 2 */
+ {0x1F, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
+ {0x16, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SATA1, SATA2} },
+ {0x01, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
+ {0x29, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1} },
+ {0x2D, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1} },
+ {0x15, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SATA1, SATA2} },
+ {0x18, {PCIE1, PCIE1, PCIE1, PCIE1, AURORA, AURORA, SATA1, SATA2} },
+ {0x02, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
+ {0x36, {SRIO2, SRIO2, SRIO2, SRIO2, AURORA, AURORA, SATA1, SATA2} },
+ {}
+};
+#endif
+
+static const struct serdes_config *serdes_cfg_tbl[] = {
+ serdes1_cfg_tbl,
+#ifndef CONFIG_PPC_T2081
+ serdes2_cfg_tbl,
+#endif
+};
+
+enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
+{
+ const struct serdes_config *ptr;
+
+ if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
+ return 0;
+
+ ptr = serdes_cfg_tbl[serdes];
+ while (ptr->protocol) {
+ if (ptr->protocol == cfg)
+ return ptr->lanes[lane];
+ ptr++;
+ }
+ return 0;
+}
+
+int is_serdes_prtcl_valid(int serdes, u32 prtcl)
+{
+ int i;
+ const struct serdes_config *ptr;
+
+ if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
+ return 0;
+
+ ptr = serdes_cfg_tbl[serdes];
+ while (ptr->protocol) {
+ if (ptr->protocol == prtcl)
+ break;
+ ptr++;
+ }
+
+ if (!ptr->protocol)
+ return 0;
+
+ for (i = 0; i < SRDS_MAX_LANES; i++) {
+ if (ptr->lanes[i] != NONE)
+ return 1;
+ }
+
+ return 0;
+}
diff --git a/arch/powerpc/cpu/mpc85xx/t4240_ids.c b/arch/powerpc/cpu/mpc85xx/t4240_ids.c
index 54c1cfd..f181315 100644
--- a/arch/powerpc/cpu/mpc85xx/t4240_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/t4240_ids.c
@@ -86,10 +86,10 @@
SET_SATA_LIODN(1, 555),
SET_SATA_LIODN(2, 556),
- SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148),
- SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 228),
- SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 308),
- SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 388),
+ SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148),
+ SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 228),
+ SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 308),
+ SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 388),
SET_DMA_LIODN(1, 147),
SET_DMA_LIODN(2, 227),
diff --git a/arch/powerpc/cpu/mpc86xx/Makefile b/arch/powerpc/cpu/mpc86xx/Makefile
index bcb786d..0f790b0 100644
--- a/arch/powerpc/cpu/mpc86xx/Makefile
+++ b/arch/powerpc/cpu/mpc86xx/Makefile
@@ -16,9 +16,6 @@
obj-y += cpu.o
obj-y += cpu_init.o
-# 8610 & 8641 are identical w/regards to DDR
-obj-$(CONFIG_MPC8610) += ddr-8641.o
-obj-$(CONFIG_MPC8641) += ddr-8641.o
obj-$(CONFIG_OF_LIBFDT) += fdt.o
obj-y += interrupts.o
obj-$(CONFIG_MP) += mp.o
diff --git a/arch/powerpc/cpu/mpc8xxx/Makefile b/arch/powerpc/cpu/mpc8xxx/Makefile
index 395fed1..f66ee2e 100644
--- a/arch/powerpc/cpu/mpc8xxx/Makefile
+++ b/arch/powerpc/cpu/mpc8xxx/Makefile
@@ -25,7 +25,6 @@
endif
obj-$(CONFIG_OF_LIBFDT) += fdt.o
-obj-$(CONFIG_FSL_IFC) += fsl_ifc.o
obj-$(CONFIG_FSL_LBC) += fsl_lbc.o
obj-$(CONFIG_SYS_SRIO) += srio.o
obj-$(CONFIG_FSL_LAW) += law.o
diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c
index c67be4e..35795c4 100644
--- a/arch/powerpc/cpu/mpc8xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xxx/cpu.c
@@ -75,6 +75,8 @@
CPU_TYPE_ENTRY(T1020, T1020, 0),
CPU_TYPE_ENTRY(T1021, T1021, 0),
CPU_TYPE_ENTRY(T1022, T1022, 0),
+ CPU_TYPE_ENTRY(T2080, T2080, 0),
+ CPU_TYPE_ENTRY(T2081, T2081, 0),
CPU_TYPE_ENTRY(BSC9130, 9130, 1),
CPU_TYPE_ENTRY(BSC9131, 9131, 1),
CPU_TYPE_ENTRY(BSC9132, 9132, 2),
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/Makefile b/arch/powerpc/cpu/mpc8xxx/ddr/Makefile
deleted file mode 100644
index 8cbc06c..0000000
--- a/arch/powerpc/cpu/mpc8xxx/ddr/Makefile
+++ /dev/null
@@ -1,29 +0,0 @@
-#
-# Copyright 2008-2011 Freescale Semiconductor, Inc.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License
-# Version 2 as published by the Free Software Foundation.
-#
-
-obj-$(CONFIG_FSL_DDR1) += main.o util.o ctrl_regs.o options.o \
- lc_common_dimm_params.o
-
-obj-$(CONFIG_FSL_DDR2) += main.o util.o ctrl_regs.o options.o \
- lc_common_dimm_params.o
-
-obj-$(CONFIG_FSL_DDR3) += main.o util.o ctrl_regs.o options.o \
- lc_common_dimm_params.o
-ifdef CONFIG_DDR_SPD
-SPD := y
-endif
-ifdef CONFIG_SPD_EEPROM
-SPD := y
-endif
-ifdef SPD
-obj-$(CONFIG_FSL_DDR1) += ddr1_dimm_params.o
-obj-$(CONFIG_FSL_DDR2) += ddr2_dimm_params.o
-obj-$(CONFIG_FSL_DDR3) += ddr3_dimm_params.o
-endif
-
-obj-$(CONFIG_FSL_DDR_INTERACTIVE) += interactive.o
diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h
index 3c17c99..423a6fb 100644
--- a/arch/powerpc/include/asm/config.h
+++ b/arch/powerpc/include/asm/config.h
@@ -9,10 +9,16 @@
#ifdef CONFIG_MPC85xx
#include <asm/config_mpc85xx.h>
+#define CONFIG_SYS_FSL_DDR
#endif
#ifdef CONFIG_MPC86xx
#include <asm/config_mpc86xx.h>
+#define CONFIG_SYS_FSL_DDR
+#endif
+
+#ifdef CONFIG_MPC83xx
+#define CONFIG_SYS_FSL_DDR
#endif
#ifndef HWCONFIG_BUFFER_SIZE
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 4cc12ee..99e16bd 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -40,17 +40,20 @@
#elif defined(CONFIG_MPC8540)
#define CONFIG_MAX_CPUS 1
#define CONFIG_SYS_FSL_NUM_LAWS 8
+#define CONFIG_SYS_FSL_DDRC_GEN1
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#elif defined(CONFIG_MPC8541)
#define CONFIG_MAX_CPUS 1
#define CONFIG_SYS_FSL_NUM_LAWS 8
+#define CONFIG_SYS_FSL_DDRC_GEN1
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#elif defined(CONFIG_MPC8544)
#define CONFIG_MAX_CPUS 1
#define CONFIG_SYS_FSL_NUM_LAWS 10
+#define CONFIG_SYS_FSL_DDRC_GEN2
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
@@ -59,6 +62,7 @@
#elif defined(CONFIG_MPC8548)
#define CONFIG_MAX_CPUS 1
#define CONFIG_SYS_FSL_NUM_LAWS 10
+#define CONFIG_SYS_FSL_DDRC_GEN2
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
@@ -77,17 +81,20 @@
#elif defined(CONFIG_MPC8555)
#define CONFIG_MAX_CPUS 1
#define CONFIG_SYS_FSL_NUM_LAWS 8
+#define CONFIG_SYS_FSL_DDRC_GEN1
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#elif defined(CONFIG_MPC8560)
#define CONFIG_MAX_CPUS 1
#define CONFIG_SYS_FSL_NUM_LAWS 8
+#define CONFIG_SYS_FSL_DDRC_GEN1
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#elif defined(CONFIG_MPC8568)
#define CONFIG_MAX_CPUS 1
#define CONFIG_SYS_FSL_NUM_LAWS 10
+#define CONFIG_SYS_FSL_DDRC_GEN2
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define QE_MURAM_SIZE 0x10000UL
#define MAX_QE_RISC 2
@@ -674,7 +681,8 @@
#define CONFIG_NUM_DDR_CONTROLLERS 1
#endif
-#elif defined(CONFIG_PPC_T1040)
+#elif defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\
+defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
#define CONFIG_E5500
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
@@ -710,6 +718,50 @@
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
+#elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
+#define CONFIG_E6500
+#define CONFIG_SYS_PPC64 /* 64-bit core */
+#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
+#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
+#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
+#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
+#define CONFIG_SYS_FSL_QMAN_V3
+#define CONFIG_MAX_CPUS 4
+#define CONFIG_SYS_FSL_NUM_LAWS 32
+#define CONFIG_SYS_FSL_SEC_COMPAT 4
+#define CONFIG_SYS_NUM_FMAN 1
+#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
+#define CONFIG_SYS_FSL_SRDS_1
+#define CONFIG_SYS_FSL_PCI_VER_3_X
+#if defined(CONFIG_PPC_T2080)
+#define CONFIG_SYS_NUM_FM1_DTSEC 8
+#define CONFIG_SYS_NUM_FM1_10GEC 4
+#define CONFIG_SYS_FSL_SRDS_2
+#define CONFIG_SYS_FSL_SRIO_LIODN
+#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
+#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
+#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
+#elif defined(CONFIG_PPC_T2081)
+#define CONFIG_SYS_NUM_FM1_DTSEC 6
+#define CONFIG_SYS_NUM_FM1_10GEC 2
+#endif
+#define CONFIG_SYS_FSL_NUM_USB_CTRLS 2
+#define CONFIG_NUM_DDR_CONTROLLERS 1
+#define CONFIG_PME_PLAT_CLK_DIV 1
+#define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
+#define CONFIG_SYS_FM1_CLK 0
+#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
+#define CONFIG_SYS_FMAN_V3
+#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
+#define CONFIG_SYS_FSL_TBCLK_DIV 16
+#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
+#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
+#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
+#define CONFIG_SYS_FSL_SFP_VER_3_0
+#define CONFIG_SYS_FSL_ISBC_VER 2
+
#elif defined(CONFIG_PPC_C29X)
#define CONFIG_MAX_CPUS 1
#define CONFIG_FSL_SDHC_V2_3
@@ -737,4 +789,10 @@
#define CONFIG_SYS_FSL_THREADS_PER_CORE 1
#endif
+#if !defined(CONFIG_SYS_FSL_DDRC_GEN1) && \
+ !defined(CONFIG_SYS_FSL_DDRC_GEN2) && \
+ !defined(CONFIG_SYS_FSL_DDRC_GEN3)
+#define CONFIG_SYS_FSL_DDRC_GEN3
+#endif
+
#endif /* _ASM_MPC85xx_CONFIG_H_ */
diff --git a/arch/powerpc/include/asm/config_mpc86xx.h b/arch/powerpc/include/asm/config_mpc86xx.h
index 694b110..4f9b225 100644
--- a/arch/powerpc/include/asm/config_mpc86xx.h
+++ b/arch/powerpc/include/asm/config_mpc86xx.h
@@ -7,6 +7,8 @@
#ifndef _ASM_MPC86xx_CONFIG_H_
#define _ASM_MPC86xx_CONFIG_H_
+#define CONFIG_SYS_FSL_DDR_86XX
+
/* SoC specific defines for Freescale MPC86xx processors */
#if defined(CONFIG_MPC8610)
diff --git a/arch/powerpc/include/asm/fsl_serdes.h b/arch/powerpc/include/asm/fsl_serdes.h
index cce892c..404ded4 100644
--- a/arch/powerpc/include/asm/fsl_serdes.h
+++ b/arch/powerpc/include/asm/fsl_serdes.h
@@ -62,6 +62,8 @@
QSGMII_FM1_B, /* B indicates MACs 5,6,9,10 */
QSGMII_FM2_A,
QSGMII_FM2_B,
+ XFI_FM1_MAC1,
+ XFI_FM1_MAC2,
XFI_FM1_MAC9,
XFI_FM1_MAC10,
XFI_FM2_MAC9,
diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h
index 3c86ff6..2518402 100644
--- a/arch/powerpc/include/asm/immap_83xx.h
+++ b/arch/powerpc/include/asm/immap_83xx.h
@@ -14,6 +14,7 @@
#ifndef __IMMAP_83xx__
#define __IMMAP_83xx__
+#include <fsl_immap.h>
#include <asm/types.h>
#include <asm/fsl_i2c.h>
#include <asm/mpc8xxx_spi.h>
@@ -277,107 +278,10 @@
} qesba83xx_t;
/*
- * DDR Memory Controller Memory Map
+ * DDR Memory Controller Memory Map for DDR1
+ * The structure of DDR2, or DDR3 is defined in fsl_immap.h
*/
-#if defined(CONFIG_FSL_DDR2) || defined(CONFIG_FSL_DDR3)
-typedef struct ccsr_ddr {
- u32 cs0_bnds; /* Chip Select 0 Memory Bounds */
- u8 res1[4];
- u32 cs1_bnds; /* Chip Select 1 Memory Bounds */
- u8 res2[4];
- u32 cs2_bnds; /* Chip Select 2 Memory Bounds */
- u8 res3[4];
- u32 cs3_bnds; /* Chip Select 3 Memory Bounds */
- u8 res4[100];
- u32 cs0_config; /* Chip Select Configuration */
- u32 cs1_config; /* Chip Select Configuration */
- u32 cs2_config; /* Chip Select Configuration */
- u32 cs3_config; /* Chip Select Configuration */
- u8 res4a[48];
- u32 cs0_config_2; /* Chip Select Configuration 2 */
- u32 cs1_config_2; /* Chip Select Configuration 2 */
- u32 cs2_config_2; /* Chip Select Configuration 2 */
- u32 cs3_config_2; /* Chip Select Configuration 2 */
- u8 res5[48];
- u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */
- u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */
- u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */
- u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */
- u32 sdram_cfg; /* SDRAM Control Configuration */
- u32 sdram_cfg_2; /* SDRAM Control Configuration 2 */
- u32 sdram_mode; /* SDRAM Mode Configuration */
- u32 sdram_mode_2; /* SDRAM Mode Configuration 2 */
- u32 sdram_md_cntl; /* SDRAM Mode Control */
- u32 sdram_interval; /* SDRAM Interval Configuration */
- u32 sdram_data_init; /* SDRAM Data initialization */
- u8 res6[4];
- u32 sdram_clk_cntl; /* SDRAM Clock Control */
- u8 res7[20];
- u32 init_addr; /* training init addr */
- u32 init_ext_addr; /* training init extended addr */
- u8 res8_1[16];
- u32 timing_cfg_4; /* SDRAM Timing Configuration 4 */
- u32 timing_cfg_5; /* SDRAM Timing Configuration 5 */
- u8 reg8_1a[8];
- u32 ddr_zq_cntl; /* ZQ calibration control*/
- u32 ddr_wrlvl_cntl; /* write leveling control*/
- u8 reg8_1aa[4];
- u32 ddr_sr_cntr; /* self refresh counter */
- u32 ddr_sdram_rcw_1; /* Control Words 1 */
- u32 ddr_sdram_rcw_2; /* Control Words 2 */
- u8 reg_1ab[8];
- u32 ddr_wrlvl_cntl_2; /* write leveling control 2 */
- u32 ddr_wrlvl_cntl_3; /* write leveling control 3 */
- u8 res8_1b[104];
- u32 sdram_mode_3; /* SDRAM Mode Configuration 3 */
- u32 sdram_mode_4; /* SDRAM Mode Configuration 4 */
- u32 sdram_mode_5; /* SDRAM Mode Configuration 5 */
- u32 sdram_mode_6; /* SDRAM Mode Configuration 6 */
- u32 sdram_mode_7; /* SDRAM Mode Configuration 7 */
- u32 sdram_mode_8; /* SDRAM Mode Configuration 8 */
- u8 res8_1ba[0x908];
- u32 ddr_dsr1; /* Debug Status 1 */
- u32 ddr_dsr2; /* Debug Status 2 */
- u32 ddr_cdr1; /* Control Driver 1 */
- u32 ddr_cdr2; /* Control Driver 2 */
- u8 res8_1c[200];
- u32 ip_rev1; /* IP Block Revision 1 */
- u32 ip_rev2; /* IP Block Revision 2 */
- u32 eor; /* Enhanced Optimization Register */
- u8 res8_2[252];
- u32 mtcr; /* Memory Test Control Register */
- u8 res8_3[28];
- u32 mtp1; /* Memory Test Pattern 1 */
- u32 mtp2; /* Memory Test Pattern 2 */
- u32 mtp3; /* Memory Test Pattern 3 */
- u32 mtp4; /* Memory Test Pattern 4 */
- u32 mtp5; /* Memory Test Pattern 5 */
- u32 mtp6; /* Memory Test Pattern 6 */
- u32 mtp7; /* Memory Test Pattern 7 */
- u32 mtp8; /* Memory Test Pattern 8 */
- u32 mtp9; /* Memory Test Pattern 9 */
- u32 mtp10; /* Memory Test Pattern 10 */
- u8 res8_4[184];
- u32 data_err_inject_hi; /* Data Path Err Injection Mask High */
- u32 data_err_inject_lo; /* Data Path Err Injection Mask Low */
- u32 ecc_err_inject; /* Data Path Err Injection Mask ECC */
- u8 res9[20];
- u32 capture_data_hi; /* Data Path Read Capture High */
- u32 capture_data_lo; /* Data Path Read Capture Low */
- u32 capture_ecc; /* Data Path Read Capture ECC */
- u8 res10[20];
- u32 err_detect; /* Error Detect */
- u32 err_disable; /* Error Disable */
- u32 err_int_en;
- u32 capture_attributes; /* Error Attrs Capture */
- u32 capture_address; /* Error Addr Capture */
- u32 capture_ext_address; /* Error Extended Addr Capture */
- u32 err_sbe; /* Single-Bit ECC Error Management */
- u8 res11[164];
- u32 debug[32]; /* debug_1 to debug_32 */
- u8 res12[128];
-} ccsr_ddr_t;
-#else
+#if !defined(CONFIG_SYS_FSL_DDR2) && !defined(CONFIG_SYS_FSL_DDR3)
typedef struct ddr_cs_bnds {
u32 csbnds;
u8 res0[4];
@@ -739,8 +643,8 @@
u8 dll_ddr[0x100];
u8 dll_lbc[0x100];
u8 res1[0xE00];
-#if defined(CONFIG_FSL_DDR2) || defined(CONFIG_FSL_DDR3)
- ccsr_ddr_t ddr; /* DDR Memory Controller Memory */
+#if defined(CONFIG_SYS_FSL_DDR2) || defined(CONFIG_SYS_FSL_DDR3)
+ struct ccsr_ddr ddr; /* DDR Memory Controller Memory */
#else
ddr83xx_t ddr; /* DDR Memory Controller Memory */
#endif
@@ -763,6 +667,7 @@
u8 res7[0xC0000];
} immap_t;
+#ifndef CONFIG_MPC834x
#ifdef CONFIG_HAS_FSL_MPH_USB
#define CONFIG_SYS_MPC83xx_USB1_OFFSET 0x22000 /* use the MPH controller */
#define CONFIG_SYS_MPC83xx_USB2_OFFSET 0
@@ -770,6 +675,10 @@
#define CONFIG_SYS_MPC83xx_USB1_OFFSET 0
#define CONFIG_SYS_MPC83xx_USB2_OFFSET 0x23000 /* use the DR controller */
#endif
+#else
+#define CONFIG_SYS_MPC83xx_USB1_OFFSET 0x22000
+#define CONFIG_SYS_MPC83xx_USB2_OFFSET 0x23000
+#endif
#elif defined(CONFIG_MPC8313)
typedef struct immap {
@@ -1024,7 +933,7 @@
#endif
#define CONFIG_SYS_MPC8xxx_DDR_OFFSET (0x2000)
-#define CONFIG_SYS_MPC8xxx_DDR_ADDR \
+#define CONFIG_SYS_FSL_DDR_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
#define CONFIG_SYS_MPC83xx_DMA_OFFSET (0x8000)
#define CONFIG_SYS_MPC83xx_DMA_ADDR \
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 060e0d7..672e8c6 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -15,9 +15,10 @@
#include <asm/types.h>
#include <asm/fsl_dma.h>
#include <asm/fsl_i2c.h>
-#include <asm/fsl_ifc.h>
+#include <fsl_ifc.h>
#include <asm/fsl_lbc.h>
#include <asm/fsl_fman.h>
+#include <fsl_immap.h>
typedef struct ccsr_local {
u32 ccsrbarh; /* CCSR Base Addr High */
@@ -112,105 +113,6 @@
u8 res24[492];
} ccsr_local_ecm_t;
-/* DDR memory controller registers */
-typedef struct ccsr_ddr {
- u32 cs0_bnds; /* Chip Select 0 Memory Bounds */
- u8 res1[4];
- u32 cs1_bnds; /* Chip Select 1 Memory Bounds */
- u8 res2[4];
- u32 cs2_bnds; /* Chip Select 2 Memory Bounds */
- u8 res3[4];
- u32 cs3_bnds; /* Chip Select 3 Memory Bounds */
- u8 res4[100];
- u32 cs0_config; /* Chip Select Configuration */
- u32 cs1_config; /* Chip Select Configuration */
- u32 cs2_config; /* Chip Select Configuration */
- u32 cs3_config; /* Chip Select Configuration */
- u8 res4a[48];
- u32 cs0_config_2; /* Chip Select Configuration 2 */
- u32 cs1_config_2; /* Chip Select Configuration 2 */
- u32 cs2_config_2; /* Chip Select Configuration 2 */
- u32 cs3_config_2; /* Chip Select Configuration 2 */
- u8 res5[48];
- u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */
- u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */
- u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */
- u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */
- u32 sdram_cfg; /* SDRAM Control Configuration */
- u32 sdram_cfg_2; /* SDRAM Control Configuration 2 */
- u32 sdram_mode; /* SDRAM Mode Configuration */
- u32 sdram_mode_2; /* SDRAM Mode Configuration 2 */
- u32 sdram_md_cntl; /* SDRAM Mode Control */
- u32 sdram_interval; /* SDRAM Interval Configuration */
- u32 sdram_data_init; /* SDRAM Data initialization */
- u8 res6[4];
- u32 sdram_clk_cntl; /* SDRAM Clock Control */
- u8 res7[20];
- u32 init_addr; /* training init addr */
- u32 init_ext_addr; /* training init extended addr */
- u8 res8_1[16];
- u32 timing_cfg_4; /* SDRAM Timing Configuration 4 */
- u32 timing_cfg_5; /* SDRAM Timing Configuration 5 */
- u8 reg8_1a[8];
- u32 ddr_zq_cntl; /* ZQ calibration control*/
- u32 ddr_wrlvl_cntl; /* write leveling control*/
- u8 reg8_1aa[4];
- u32 ddr_sr_cntr; /* self refresh counter */
- u32 ddr_sdram_rcw_1; /* Control Words 1 */
- u32 ddr_sdram_rcw_2; /* Control Words 2 */
- u8 reg_1ab[8];
- u32 ddr_wrlvl_cntl_2; /* write leveling control 2 */
- u32 ddr_wrlvl_cntl_3; /* write leveling control 3 */
- u8 res8_1b[104];
- u32 sdram_mode_3; /* SDRAM Mode Configuration 3 */
- u32 sdram_mode_4; /* SDRAM Mode Configuration 4 */
- u32 sdram_mode_5; /* SDRAM Mode Configuration 5 */
- u32 sdram_mode_6; /* SDRAM Mode Configuration 6 */
- u32 sdram_mode_7; /* SDRAM Mode Configuration 7 */
- u32 sdram_mode_8; /* SDRAM Mode Configuration 8 */
- u8 res8_1ba[0x908];
- u32 ddr_dsr1; /* Debug Status 1 */
- u32 ddr_dsr2; /* Debug Status 2 */
- u32 ddr_cdr1; /* Control Driver 1 */
- u32 ddr_cdr2; /* Control Driver 2 */
- u8 res8_1c[200];
- u32 ip_rev1; /* IP Block Revision 1 */
- u32 ip_rev2; /* IP Block Revision 2 */
- u32 eor; /* Enhanced Optimization Register */
- u8 res8_2[252];
- u32 mtcr; /* Memory Test Control Register */
- u8 res8_3[28];
- u32 mtp1; /* Memory Test Pattern 1 */
- u32 mtp2; /* Memory Test Pattern 2 */
- u32 mtp3; /* Memory Test Pattern 3 */
- u32 mtp4; /* Memory Test Pattern 4 */
- u32 mtp5; /* Memory Test Pattern 5 */
- u32 mtp6; /* Memory Test Pattern 6 */
- u32 mtp7; /* Memory Test Pattern 7 */
- u32 mtp8; /* Memory Test Pattern 8 */
- u32 mtp9; /* Memory Test Pattern 9 */
- u32 mtp10; /* Memory Test Pattern 10 */
- u8 res8_4[184];
- u32 data_err_inject_hi; /* Data Path Err Injection Mask High */
- u32 data_err_inject_lo; /* Data Path Err Injection Mask Low */
- u32 ecc_err_inject; /* Data Path Err Injection Mask ECC */
- u8 res9[20];
- u32 capture_data_hi; /* Data Path Read Capture High */
- u32 capture_data_lo; /* Data Path Read Capture Low */
- u32 capture_ecc; /* Data Path Read Capture ECC */
- u8 res10[20];
- u32 err_detect; /* Error Detect */
- u32 err_disable; /* Error Disable */
- u32 err_int_en;
- u32 capture_attributes; /* Error Attrs Capture */
- u32 capture_address; /* Error Addr Capture */
- u32 capture_ext_address; /* Error Extended Addr Capture */
- u32 err_sbe; /* Single-Bit ECC Error Management */
- u8 res11[164];
- u32 debug[32]; /* debug_1 to debug_32 */
- u8 res12[128];
-} ccsr_ddr_t;
-
#define DDR_EOR_RD_BDW_OPT_DIS 0x80000000 /* Read BDW Opt. disable */
#define DDR_EOR_ADDR_HASH_EN 0x40000000 /* Address hash enabled */
@@ -282,7 +184,9 @@
u32 int_ack; /* PCIX IRQ Acknowledge */
u8 res000c[52];
u32 liodn_base; /* PCIX LIODN base register */
- u8 res0044[3004];
+ u8 res0044[2996];
+ u32 ipver1; /* PCIX IP block revision register 1 */
+ u32 ipver2; /* PCIX IP block revision register 2 */
u32 potar0; /* PCIX Outbound Transaction Addr 0 */
u32 potear0; /* PCIX Outbound Translation Extended Addr 0 */
u32 powbar0; /* PCIX Outbound Window Base Addr 0 */
@@ -1717,6 +1621,8 @@
#define FSL_CORENET_DEVDISR2_DTSEC1_10 0x00400000
#define FSL_CORENET_DEVDISR2_10GEC1_1 0x00800000
#define FSL_CORENET_DEVDISR2_10GEC1_2 0x00400000
+#define FSL_CORENET_DEVDISR2_10GEC1_3 0x80000000
+#define FSL_CORENET_DEVDISR2_10GEC1_4 0x40000000
#define FSL_CORENET_DEVDISR2_DTSEC2_1 0x00080000
#define FSL_CORENET_DEVDISR2_DTSEC2_2 0x00040000
#define FSL_CORENET_DEVDISR2_DTSEC2_3 0x00020000
@@ -1847,11 +1753,18 @@
#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000
#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 16
#define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
-#elif defined(CONFIG_PPC_T1040)
+#elif defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\
+defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24
#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000
#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 17
+#elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
+#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000
+#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24
+#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000
+#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 16
+#define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
#endif
#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL1 0x00800000
#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL2 0x00400000
@@ -1915,6 +1828,15 @@
#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC6_RGMII 0x08000000
#define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000
#endif
+#if defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
+#define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */
+#define FSL_CORENET_RCWSR13_EC1_DTSEC3_RGMII 0x00000000
+#define FSL_CORENET_RCWSR13_EC1_GPIO 0x40000000
+#define FSL_CORENET_RCWSR13_EC2 0x18000000 /* bits 419..420 */
+#define FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII 0x00000000
+#define FSL_CORENET_RCWSR13_EC2_DTSEC10_RGMII 0x08000000
+#define FSL_CORENET_RCWSR13_EC2_GPIO 0x10000000
+#endif
u8 res18[192];
u32 scratchrw[4]; /* Scratch Read/Write */
u8 res19[240];
@@ -2911,6 +2833,7 @@
#define CONFIG_SYS_FSL_CPC_OFFSET 0x10000
#define CONFIG_SYS_MPC85xx_DMA1_OFFSET 0x100000
#define CONFIG_SYS_MPC85xx_DMA2_OFFSET 0x101000
+#define CONFIG_SYS_MPC85xx_DMA3_OFFSET 0x102000
#define CONFIG_SYS_MPC85xx_DMA_OFFSET CONFIG_SYS_MPC85xx_DMA1_OFFSET
#define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x110000
#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x114000
@@ -3045,11 +2968,11 @@
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RCPM_OFFSET)
#define CONFIG_SYS_MPC85xx_ECM_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ECM_OFFSET)
-#define CONFIG_SYS_MPC8xxx_DDR_ADDR \
+#define CONFIG_SYS_FSL_DDR_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
-#define CONFIG_SYS_MPC8xxx_DDR2_ADDR \
+#define CONFIG_SYS_FSL_DDR2_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR2_OFFSET)
-#define CONFIG_SYS_MPC8xxx_DDR3_ADDR \
+#define CONFIG_SYS_FSL_DDR3_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR3_OFFSET)
#define CONFIG_SYS_LBC_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET)
diff --git a/arch/powerpc/include/asm/immap_86xx.h b/arch/powerpc/include/asm/immap_86xx.h
index 2a704fe..177918b 100644
--- a/arch/powerpc/include/asm/immap_86xx.h
+++ b/arch/powerpc/include/asm/immap_86xx.h
@@ -10,6 +10,7 @@
#ifndef __IMMAP_86xx__
#define __IMMAP_86xx__
+#include <fsl_immap.h>
#include <asm/types.h>
#include <asm/fsl_dma.h>
#include <asm/fsl_lbc.h>
@@ -89,75 +90,6 @@
char res31[488];
} ccsr_local_mcm_t;
-/* DDR memory controller registers(0x2000-0x3000) and (0x6000-0x7000) */
-
-typedef struct ccsr_ddr {
- uint cs0_bnds; /* 0x2000 - DDR Chip Select 0 Memory Bounds */
- char res1[4];
- uint cs1_bnds; /* 0x2008 - DDR Chip Select 1 Memory Bounds */
- char res2[4];
- uint cs2_bnds; /* 0x2010 - DDR Chip Select 2 Memory Bounds */
- char res3[4];
- uint cs3_bnds; /* 0x2018 - DDR Chip Select 3 Memory Bounds */
- char res4[4];
- uint cs4_bnds; /* 0x2020 - DDR Chip Select 4 Memory Bounds */
- char res5[4];
- uint cs5_bnds; /* 0x2028 - DDR Chip Select 5 Memory Bounds */
- char res6[84];
- uint cs0_config; /* 0x2080 - DDR Chip Select Configuration */
- uint cs1_config; /* 0x2084 - DDR Chip Select Configuration */
- uint cs2_config; /* 0x2088 - DDR Chip Select Configuration */
- uint cs3_config; /* 0x208c - DDR Chip Select Configuration */
- uint cs4_config; /* 0x2090 - DDR Chip Select Configuration */
- uint cs5_config; /* 0x2094 - DDR Chip Select Configuration */
- char res7[104];
- uint timing_cfg_3; /* 0x2100 - DDR SDRAM Timing Configuration Register 3 */
- uint timing_cfg_0; /* 0x2104 - DDR SDRAM Timing Configuration Register 0 */
- uint timing_cfg_1; /* 0x2108 - DDR SDRAM Timing Configuration Register 1 */
- uint timing_cfg_2; /* 0x210c - DDR SDRAM Timing Configuration Register 2 */
- uint sdram_cfg; /* 0x2110 - DDR SDRAM Control Configuration 1 */
- uint sdram_cfg_2; /* 0x2114 - DDR SDRAM Control Configuration 2 */
- uint sdram_mode; /* 0x2118 - DDR SDRAM Mode Configuration 1 */
- uint sdram_mode_2; /* 0x211c - DDR SDRAM Mode Configuration 2 */
- uint sdram_mode_cntl; /* 0x2120 - DDR SDRAM Mode Control */
- uint sdram_interval; /* 0x2124 - DDR SDRAM Interval Configuration */
- uint sdram_data_init; /* 0x2128 - DDR SDRAM Data Initialization */
- char res8[4];
- uint sdram_clk_cntl; /* 0x2130 - DDR SDRAM Clock Control */
- char res9[12];
- uint sdram_ocd_cntl; /* 0x2140 - DDR SDRAM OCD Control */
- uint sdram_ocd_status; /* 0x2144 - DDR SDRAM OCD Status */
- uint init_addr; /* 0x2148 - DDR training initialzation address */
- uint init_ext_addr; /* 0x214C - DDR training initialzation extended address */
- char res10[2728];
- uint ip_rev1; /* 0x2BF8 - DDR IP Block Revision 1 */
- uint ip_rev2; /* 0x2BFC - DDR IP Block Revision 2 */
- char res11[512];
- uint data_err_inject_hi; /* 0x2e00 - DDR Memory Data Path Error Injection Mask High */
- uint data_err_inject_lo; /* 0x2e04 - DDR Memory Data Path Error Injection Mask Low */
- uint ecc_err_inject; /* 0x2e08 - DDR Memory Data Path Error Injection Mask ECC */
- char res12[20];
- uint capture_data_hi; /* 0x2e20 - DDR Memory Data Path Read Capture High */
- uint capture_data_lo; /* 0x2e24 - DDR Memory Data Path Read Capture Low */
- uint capture_ecc; /* 0x2e28 - DDR Memory Data Path Read Capture ECC */
- char res13[20];
- uint err_detect; /* 0x2e40 - DDR Memory Error Detect */
- uint err_disable; /* 0x2e44 - DDR Memory Error Disable */
- uint err_int_en; /* 0x2e48 - DDR Memory Error Interrupt Enable */
- uint capture_attributes; /* 0x2e4c - DDR Memory Error Attributes Capture */
- uint capture_address; /* 0x2e50 - DDR Memory Error Address Capture */
- uint capture_ext_address; /* 0x2e54 - DDR Memory Error Extended Address Capture */
- uint err_sbe; /* 0x2e58 - DDR Memory Single-Bit ECC Error Management */
- char res14[164];
- uint debug_1; /* 0x2f00 */
- uint debug_2;
- uint debug_3;
- uint debug_4;
- uint debug_5;
- char res15[236];
-} ccsr_ddr_t;
-
-
/* Daul I2C Registers(0x3000-0x4000) */
typedef struct ccsr_i2c {
struct fsl_i2c i2c[2];
@@ -1225,11 +1157,11 @@
typedef struct immap {
ccsr_local_mcm_t im_local_mcm;
- ccsr_ddr_t im_ddr1;
+ struct ccsr_ddr im_ddr1;
ccsr_i2c_t im_i2c;
ccsr_duart_t im_duart;
fsl_lbc_t im_lbc;
- ccsr_ddr_t im_ddr2;
+ struct ccsr_ddr im_ddr2;
char res1[4096];
ccsr_pex_t im_pex1;
ccsr_pex_t im_pex2;
@@ -1253,9 +1185,9 @@
extern immap_t *immr;
#define CONFIG_SYS_MPC8xxx_DDR_OFFSET 0x2000
-#define CONFIG_SYS_MPC8xxx_DDR_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
+#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
#define CONFIG_SYS_MPC8xxx_DDR2_OFFSET 0x6000
-#define CONFIG_SYS_MPC8xxx_DDR2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR2_OFFSET)
+#define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR2_OFFSET)
#define CONFIG_SYS_MPC86xx_DMA_OFFSET 0x21000
#define CONFIG_SYS_MPC86xx_DMA_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DMA_OFFSET)
#define CONFIG_SYS_MPC86xx_PIC_OFFSET 0x40000
diff --git a/arch/powerpc/include/asm/mpc85xx_gpio.h b/arch/powerpc/include/asm/mpc85xx_gpio.h
index 3d11884..87bb4a0 100644
--- a/arch/powerpc/include/asm/mpc85xx_gpio.h
+++ b/arch/powerpc/include/asm/mpc85xx_gpio.h
@@ -20,7 +20,7 @@
static inline void mpc85xx_gpio_set(unsigned int mask,
unsigned int dir, unsigned int val)
{
- ccsr_gpio_t *gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR + 0xc00);
+ ccsr_gpio_t *gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
/* First mask off the unwanted parts of "dir" and "val" */
dir &= mask;
@@ -56,7 +56,7 @@
static inline unsigned int mpc85xx_gpio_get(unsigned int mask)
{
- ccsr_gpio_t *gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR + 0xc00);
+ ccsr_gpio_t *gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
/* Read the requested values */
return in_be32(&gpio->gpdat) & mask;
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 81f9d38..831804c 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -1127,6 +1127,8 @@
#define SVR_T1020 0x852100
#define SVR_T1021 0x852101
#define SVR_T1022 0x852102
+#define SVR_T2080 0x853000
+#define SVR_T2081 0x853100
#define SVR_8610 0x80A000
#define SVR_8641 0x809000
diff --git a/arch/sandbox/cpu/Makefile b/arch/sandbox/cpu/Makefile
index 404ff67..58c2537 100644
--- a/arch/sandbox/cpu/Makefile
+++ b/arch/sandbox/cpu/Makefile
@@ -10,5 +10,7 @@
obj-y := cpu.o os.o start.o state.o
# os.c is build in the system environment, so needs standard includes
-$(obj)os.o: ALL_CFLAGS := $(filter-out -nostdinc,$(ALL_CFLAGS))
-$(obj).depend.os: CPPFLAGS := $(filter-out -nostdinc,$(CPPFLAGS))
+$(obj)os.o: ALL_CFLAGS := $(BASE_CPPFLAGS) \
+ $(patsubst %, -idirafter %, $(BASE_INCLUDE_DIRS))
+$(obj).depend.os: CPPFLAGS := $(BASE_CPPFLAGS) \
+ $(patsubst %, -idirafter %, $(BASE_INCLUDE_DIRS))
diff --git a/arch/sandbox/cpu/os.c b/arch/sandbox/cpu/os.c
index c2e5f57..db66fd3 100644
--- a/arch/sandbox/cpu/os.c
+++ b/arch/sandbox/cpu/os.c
@@ -8,6 +8,7 @@
#include <fcntl.h>
#include <getopt.h>
#include <stdio.h>
+#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <termios.h>
@@ -136,7 +137,7 @@
usleep(usec);
}
-u64 __attribute__((no_instrument_function)) os_get_nsec(void)
+uint64_t __attribute__((no_instrument_function)) os_get_nsec(void)
{
#if defined(CLOCK_MONOTONIC) && defined(_POSIX_MONOTONIC_CLOCK)
struct timespec tp;
diff --git a/arch/sandbox/include/asm/io.h b/arch/sandbox/include/asm/io.h
index 9ac6a5f..7956041 100644
--- a/arch/sandbox/include/asm/io.h
+++ b/arch/sandbox/include/asm/io.h
@@ -38,6 +38,6 @@
}
/* Map from a pointer to our RAM buffer */
-phys_addr_t map_to_sysmem(void *ptr);
+phys_addr_t map_to_sysmem(const void *ptr);
#endif
diff --git a/arch/sandbox/include/asm/types.h b/arch/sandbox/include/asm/types.h
index 88c84ba..6d3eb1f 100644
--- a/arch/sandbox/include/asm/types.h
+++ b/arch/sandbox/include/asm/types.h
@@ -48,8 +48,8 @@
#define BITS_PER_LONG CONFIG_SANDBOX_BITS_PER_LONG
typedef unsigned long dma_addr_t;
-typedef unsigned long phys_addr_t;
-typedef unsigned long phys_size_t;
+typedef u32 phys_addr_t;
+typedef u32 phys_size_t;
#endif /* __KERNEL__ */
diff --git a/arch/sparc/cpu/leon3/start.S b/arch/sparc/cpu/leon3/start.S
index bbc1b34..cf897f6 100644
--- a/arch/sparc/cpu/leon3/start.S
+++ b/arch/sparc/cpu/leon3/start.S
@@ -1,33 +1,41 @@
+/* This is where the SPARC/LEON3 starts
+ * Copyright (C) 2007,
+ * Daniel Hellstrom, daniel@gaisler.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm-offsets.h>
#include <config.h>
+#include <asm/asmmacro.h>
+#include <asm/winmacro.h>
+#include <asm/psr.h>
+#include <asm/stack.h>
+#include <asm/leon.h>
+#include <version.h>
-TRAP ta 0; nop; nop; nop;
+/* Entry for traps which jump to a programmer-specified trap handler. */
+#define TRAPR(H) \
+ wr %g0, 0xfe0, %psr; \
+ mov %g0, %tbr; \
+ ba (H); \
+ mov %g0, %wim;
-/* Software trap. Treat as BAD_TRAP for the time being... */
-#define SOFT_TRAP TRAP(_hwerr)
+#define TRAP(H) \
+ mov %psr, %l0; \
+ ba (H); \
+ nop; nop;
-#define PSR_INIT 0x1FC0 /* Disable traps, set s and ps */
-#define WIM_INIT 2
+#define TRAPI(ilevel) \
+ mov ilevel, %l7; \
+ mov %psr, %l0; \
+ b _irq_entry; \
+ mov %wim, %l3
-/* All traps low-level code here must end with this macro. */
-#define RESTORE_ALL b ret_trap_entry; clr %l6;
-
-#define WRITE_PAUSE nop;nop;nop
-
-WINDOWSIZE = (16 * 4)
-ARGPUSHSIZE = (6 * 4)
-ARGPUSH = (WINDOWSIZE + 4)
-MINFRAME = (WINDOWSIZE + ARGPUSHSIZE + 4)
-
-/* Number of register windows */
-#ifndef CONFIG_SYS_SPARC_NWINDOWS
-#error Must define number of SPARC register windows, default is 8
-#endif
-
-#define STACK_ALIGN 8
-#define SA(X) (((X)+(STACK_ALIGN-1)) & ~(STACK_ALIGN-1))
-
- .section ".start", "ax"
- .globl _starttate */
+/* Unexcpected trap will halt the processor by forcing it to error state */
#undef BAD_TRAP
#define BAD_TRAP ta 0; nop; nop; nop;
diff --git a/board/LEOX/elpt860/u-boot.lds b/board/LEOX/elpt860/u-boot.lds
index b30b667..c5e57ec 100644
--- a/board/LEOX/elpt860/u-boot.lds
+++ b/board/LEOX/elpt860/u-boot.lds
@@ -30,10 +30,10 @@
arch/powerpc/cpu/mpc8xx/start.o (.text*)
arch/powerpc/cpu/mpc8xx/traps.o (.text*)
- common/libcommon.o (.text*)
- arch/powerpc/cpu/mpc8xx/libmpc8xx.o (.text*)
- board/LEOX/elpt860/libelpt860.o (.text*)
- arch/powerpc/lib/libpowerpc.o (.text*)
+ common/built-in.o (.text*)
+ arch/powerpc/cpu/mpc8xx/built-in.o (.text*)
+ board/LEOX/elpt860/built-in.o (.text*)
+ arch/powerpc/lib/built-in.o (.text*)
. = env_offset;
common/env_embedded.o (.text*)
diff --git a/board/LaCie/edminiv2/Makefile b/board/LaCie/edminiv2/Makefile
index 7ca06f5..035f686 100644
--- a/board/LaCie/edminiv2/Makefile
+++ b/board/LaCie/edminiv2/Makefile
@@ -9,8 +9,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
obj-y := edminiv2.o ../common/common.o
diff --git a/board/LaCie/net2big_v2/Makefile b/board/LaCie/net2big_v2/Makefile
index 4fa08c5..f3074af 100644
--- a/board/LaCie/net2big_v2/Makefile
+++ b/board/LaCie/net2big_v2/Makefile
@@ -9,10 +9,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
obj-y := net2big_v2.o ../common/common.o
ifneq ($(and $(CONFIG_KIRKWOOD_GPIO),$(CONFIG_NET2BIG_V2)),)
obj-y += ../common/cpld-gpio-bus.o
diff --git a/board/LaCie/netspace_v2/Makefile b/board/LaCie/netspace_v2/Makefile
index e5357e4..47778d8 100644
--- a/board/LaCie/netspace_v2/Makefile
+++ b/board/LaCie/netspace_v2/Makefile
@@ -9,8 +9,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
obj-y := netspace_v2.o ../common/common.o
diff --git a/board/LaCie/wireless_space/Makefile b/board/LaCie/wireless_space/Makefile
index 11c535e..90a84f4 100644
--- a/board/LaCie/wireless_space/Makefile
+++ b/board/LaCie/wireless_space/Makefile
@@ -9,8 +9,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
obj-y := wireless_space.o ../common/common.o
diff --git a/board/Marvell/db64360/Makefile b/board/Marvell/db64360/Makefile
index aad4776..aefe0a7 100644
--- a/board/Marvell/db64360/Makefile
+++ b/board/Marvell/db64360/Makefile
@@ -8,10 +8,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
obj-y = db64360.o ../common/flash.o ../common/serial.o ../common/memory.o pci.o \
mv_eth.o ../common/ns16550.o mpsc.o ../common/i2c.o \
sdram_init.o ../common/intel_flash.o ../common/misc.o
diff --git a/board/Marvell/db64460/Makefile b/board/Marvell/db64460/Makefile
index ea9e570..a970f9a 100644
--- a/board/Marvell/db64460/Makefile
+++ b/board/Marvell/db64460/Makefile
@@ -8,10 +8,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
obj-y += db64460.o ../common/flash.o ../common/serial.o ../common/memory.o pci.o \
mv_eth.o ../common/ns16550.o mpsc.o ../common/i2c.o \
sdram_init.o ../common/intel_flash.o ../common/misc.o
diff --git a/board/actux1/u-boot.lds b/board/actux1/u-boot.lds
index 12e018f..4716e4f 100644
--- a/board/actux1/u-boot.lds
+++ b/board/actux1/u-boot.lds
@@ -16,10 +16,10 @@
.text : {
*(.__image_copy_start)
arch/arm/cpu/ixp/start.o(.text*)
- net/libnet.o(.text*)
- board/actux1/libactux1.o(.text*)
- arch/arm/cpu/ixp/libixp.o(.text*)
- drivers/input/libinput.o(.text*)
+ net/built-in.o(.text*)
+ board/actux1/built-in.o(.text*)
+ arch/arm/cpu/ixp/built-in.o(.text*)
+ drivers/input/built-in.o(.text*)
. = env_offset;
common/env_embedded.o(.ppcenv)
diff --git a/board/actux2/u-boot.lds b/board/actux2/u-boot.lds
index 300273b..f00d7c7 100644
--- a/board/actux2/u-boot.lds
+++ b/board/actux2/u-boot.lds
@@ -16,10 +16,10 @@
.text : {
*(.__image_copy_start)
arch/arm/cpu/ixp/start.o(.text*)
- net/libnet.o(.text*)
- board/actux2/libactux2.o(.text*)
- arch/arm/cpu/ixp/libixp.o(.text*)
- drivers/input/libinput.o(.text*)
+ net/built-in.o(.text*)
+ board/actux2/built-in.o(.text*)
+ arch/arm/cpu/ixp/built-in.o(.text*)
+ drivers/input/built-in.o(.text*)
. = env_offset;
common/env_embedded.o(.ppcenv)
diff --git a/board/actux3/u-boot.lds b/board/actux3/u-boot.lds
index 9c97c53..2de3ca6 100644
--- a/board/actux3/u-boot.lds
+++ b/board/actux3/u-boot.lds
@@ -16,10 +16,10 @@
.text : {
*(.__image_copy_start)
arch/arm/cpu/ixp/start.o(.text*)
- net/libnet.o(.text*)
- board/actux3/libactux3.o(.text*)
- arch/arm/cpu/ixp/libixp.o(.text*)
- drivers/input/libinput.o(.text*)
+ net/built-in.o(.text*)
+ board/actux3/built-in.o(.text*)
+ arch/arm/cpu/ixp/built-in.o(.text*)
+ drivers/input/built-in.o(.text*)
. = env_offset;
common/env_embedded.o(.ppcenv)
diff --git a/board/altera/nios2-generic/Makefile b/board/altera/nios2-generic/Makefile
index 84c7bff..84690fe 100644
--- a/board/altera/nios2-generic/Makefile
+++ b/board/altera/nios2-generic/Makefile
@@ -6,10 +6,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
obj-y := nios2-generic.o
obj-$(CONFIG_CMD_IDE) += ../common/cfide.o
obj-$(CONFIG_EPLED) += ../common/epled.o
diff --git a/board/altera/nios2-generic/config.mk b/board/altera/nios2-generic/config.mk
index f9f317c..a673525 100644
--- a/board/altera/nios2-generic/config.mk
+++ b/board/altera/nios2-generic/config.mk
@@ -5,11 +5,7 @@
# SPDX-License-Identifier: GPL-2.0+
#
-# we get text_base from board config header, so do not use this
-#CONFIG_SYS_TEXT_BASE = do-not-use-me
-
PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul
-PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include
ifeq ($(debug),1)
PLATFORM_CPPFLAGS += -DDEBUG
diff --git a/board/atmel/sama5d3xek/sama5d3xek.c b/board/atmel/sama5d3xek/sama5d3xek.c
index 0ab8020..eff94a4 100644
--- a/board/atmel/sama5d3xek/sama5d3xek.c
+++ b/board/atmel/sama5d3xek/sama5d3xek.c
@@ -134,7 +134,8 @@
void lcd_show_board_info(void)
{
- ulong dram_size, nand_size;
+ ulong dram_size;
+ uint64_t nand_size;
int i;
char temp[32];
@@ -153,7 +154,7 @@
for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
nand_size += nand_info[i].size;
#endif
- lcd_printf("%ld MB SDRAM, %ld MB NAND\n",
+ lcd_printf("%ld MB SDRAM, %lld MB NAND\n",
dram_size >> 20, nand_size >> 20);
}
#endif /* CONFIG_LCD_INFO */
diff --git a/board/avionic-design/medcom-wide/Makefile b/board/avionic-design/medcom-wide/Makefile
index 6c4ab64..87e1912 100644
--- a/board/avionic-design/medcom-wide/Makefile
+++ b/board/avionic-design/medcom-wide/Makefile
@@ -7,8 +7,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-$(shell mkdir -p $(obj)../common $(obj)../../nvidia/common)
-
obj-y := ../common/tamonten.o
include ../../nvidia/common/common.mk
diff --git a/board/avionic-design/plutux/Makefile b/board/avionic-design/plutux/Makefile
index 6c4ab64..87e1912 100644
--- a/board/avionic-design/plutux/Makefile
+++ b/board/avionic-design/plutux/Makefile
@@ -7,8 +7,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-$(shell mkdir -p $(obj)../common $(obj)../../nvidia/common)
-
obj-y := ../common/tamonten.o
include ../../nvidia/common/common.mk
diff --git a/board/avionic-design/tec/Makefile b/board/avionic-design/tec/Makefile
index 6c4ab64..87e1912 100644
--- a/board/avionic-design/tec/Makefile
+++ b/board/avionic-design/tec/Makefile
@@ -7,8 +7,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-$(shell mkdir -p $(obj)../common $(obj)../../nvidia/common)
-
obj-y := ../common/tamonten.o
include ../../nvidia/common/common.mk
diff --git a/board/cogent/config.mk b/board/cogent/config.mk
deleted file mode 100644
index 1452d46..0000000
--- a/board/cogent/config.mk
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-#
-# Cogent Modular Architecture
-#
-
-PLATFORM_CPPFLAGS += -I$(TOPDIR)
diff --git a/board/cogent/dipsw.c b/board/cogent/dipsw.c
index d2027c9..ecfbc25 100644
--- a/board/cogent/dipsw.c
+++ b/board/cogent/dipsw.c
@@ -1,5 +1,5 @@
#include <common.h>
-#include <board/cogent/dipsw.h>
+#include "dipsw.h"
unsigned char
dipsw_raw(void)
diff --git a/board/cogent/flash.c b/board/cogent/flash.c
index d4ae4d0..1da8f10 100644
--- a/board/cogent/flash.c
+++ b/board/cogent/flash.c
@@ -6,7 +6,7 @@
*/
#include <common.h>
-#include <board/cogent/flash.h>
+#include "flash.h"
#include <linux/compiler.h>
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
diff --git a/board/cogent/lcd.c b/board/cogent/lcd.c
index 76f5ad1..8e90f98 100644
--- a/board/cogent/lcd.c
+++ b/board/cogent/lcd.c
@@ -48,7 +48,7 @@
#include <common.h>
#include <stdarg.h>
-#include <board/cogent/lcd.h>
+#include "lcd.h"
static char lines[2][LCD_LINE_LENGTH+1];
static int curline;
diff --git a/board/cogent/mb.c b/board/cogent/mb.c
index 603f123..3eea47d 100644
--- a/board/cogent/mb.c
+++ b/board/cogent/mb.c
@@ -6,11 +6,11 @@
*/
#include <common.h>
-#include <board/cogent/dipsw.h>
-#include <board/cogent/lcd.h>
-#include <board/cogent/rtc.h>
-#include <board/cogent/par.h>
-#include <board/cogent/pci.h>
+#include "dipsw.h"
+#include "lcd.h"
+#include "rtc.h"
+#include "par.h"
+#include "pci.h"
/* ------------------------------------------------------------------------- */
diff --git a/board/cogent/serial.c b/board/cogent/serial.c
index 20631d1..f0d6b22 100644
--- a/board/cogent/serial.c
+++ b/board/cogent/serial.c
@@ -4,7 +4,7 @@
*/
#include <common.h>
-#include <board/cogent/serial.h>
+#include "serial.h"
#include <serial.h>
#include <linux/compiler.h>
diff --git a/board/compal/paz00/Makefile b/board/compal/paz00/Makefile
index 824cd2e..b2d3b6b 100644
--- a/board/compal/paz00/Makefile
+++ b/board/compal/paz00/Makefile
@@ -14,8 +14,6 @@
# more details.
#
-$(shell mkdir -p $(obj)../../nvidia/common)
-
obj-y := paz00.o
include ../../nvidia/common/common.mk
diff --git a/board/compulab/cm_t335/u-boot.lds b/board/compulab/cm_t335/u-boot.lds
index 3bd96e9..1b609a2 100644
--- a/board/compulab/cm_t335/u-boot.lds
+++ b/board/compulab/cm_t335/u-boot.lds
@@ -19,7 +19,7 @@
{
*(.__image_copy_start)
CPUDIR/start.o (.text*)
- board/compulab/cm_t335/libcm_t335.o (.text*)
+ board/compulab/cm_t335/built-in.o (.text*)
*(.text*)
}
diff --git a/board/compulab/cm_t35/cm_t35.c b/board/compulab/cm_t35/cm_t35.c
index b9a99659..bc8e0ca 100644
--- a/board/compulab/cm_t35/cm_t35.c
+++ b/board/compulab/cm_t35/cm_t35.c
@@ -268,6 +268,9 @@
/* DVI enable */
MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | DIS | M4));/*GPMC_nCS3*/
+ /* DataImage backlight */
+ MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | DIS | M4));/*GPIO_58*/
+
/* CM-T3x Ethernet */
MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | DIS | M0)); /*GPMC_nCS5*/
MUX_VAL(CP(GPMC_CLK), (IEN | PTD | DIS | M4)); /*GPIO_59*/
@@ -374,6 +377,15 @@
MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)); /*MMC1_DAT1*/
MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)); /*MMC1_DAT2*/
MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)); /*MMC1_DAT3*/
+
+ /* SPI */
+ MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M1)); /*MCSPI4_CLK*/
+ MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | DIS | M1)); /*MCSPI4_SIMO*/
+ MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M1)); /*MCSPI4_SOMI*/
+ MUX_VAL(CP(MCBSP1_FSX), (IEN | PTU | EN | M1)); /*MCSPI4_CS0*/
+
+ /* display controls */
+ MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | DIS | M4)); /*GPIO_157*/
}
static void cm_t35_set_muxconf(void)
@@ -470,7 +482,7 @@
&ctrl_base->gpmc_nadv_ale);
}
-#ifdef CONFIG_DRIVER_OMAP34XX_I2C
+#ifdef CONFIG_SYS_I2C_OMAP34XX
/*
* Routine: reset_net_chip
* Description: reset the Ethernet controller via TPS65930 GPIO
diff --git a/board/compulab/common/Makefile b/board/compulab/common/Makefile
index 831be2e..6d7d068 100644
--- a/board/compulab/common/Makefile
+++ b/board/compulab/common/Makefile
@@ -6,5 +6,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(CONFIG_DRIVER_OMAP34XX_I2C) += eeprom.o
+obj-$(CONFIG_SYS_I2C_OMAP34XX) += eeprom.o
obj-$(CONFIG_LCD) += omap3_display.o
diff --git a/board/compulab/common/eeprom.h b/board/compulab/common/eeprom.h
index cf8c302..e871629 100644
--- a/board/compulab/common/eeprom.h
+++ b/board/compulab/common/eeprom.h
@@ -10,7 +10,7 @@
#ifndef _EEPROM_
#define _EEPROM_
-#ifdef CONFIG_DRIVER_OMAP34XX_I2C
+#ifdef CONFIG_SYS_I2C_OMAP34XX
int cl_eeprom_read_mac_addr(uchar *buf);
u32 cl_eeprom_get_board_rev(void);
#else
diff --git a/board/compulab/common/omap3_display.c b/board/compulab/common/omap3_display.c
index ead821e..61707f5 100644
--- a/board/compulab/common/omap3_display.c
+++ b/board/compulab/common/omap3_display.c
@@ -14,6 +14,7 @@
#include <stdio_dev.h>
#include <asm/arch/dss.h>
#include <lcd.h>
+#include <scf0403_lcd.h>
#include <asm/arch-omap3/dss.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -22,6 +23,7 @@
NONE,
DVI,
DVI_CUSTOM,
+ DATA_IMAGE, /* #define CONFIG_SCF0403_LCD to use */
};
#define CMAP_ADDR 0x80100000
@@ -119,6 +121,18 @@
.gfx_format = GFXFORMAT_RGB16,
};
+static const struct panel_config preset_dataimage_480X800 = {
+ .lcd_size = PANEL_LCD_SIZE(480, 800),
+ .timing_h = DSS_HBP(2) | DSS_HFP(2) | DSS_HSW(2),
+ .timing_v = DSS_VBP(17) | DSS_VFP(20) | DSS_VSW(3),
+ .pol_freq = DSS_IVS | DSS_IHS | DSS_IPC | DSS_ONOFF,
+ .divisor = 10 | (1 << 10),
+ .data_lines = LCD_INTERFACE_18_BIT,
+ .panel_type = ACTIVE_DISPLAY,
+ .load_mode = 2,
+ .gfx_format = GFXFORMAT_RGB16,
+};
+
/*
* set_resolution_params()
*
@@ -146,6 +160,13 @@
return DVI;
}
+static enum display_type set_dataimage_preset(const struct panel_config preset,
+ int x_res, int y_res)
+{
+ set_preset(preset, x_res, y_res);
+ return DATA_IMAGE;
+}
+
/*
* parse_mode() - parse the mode parameter of custom lcd settings
*
@@ -369,6 +390,8 @@
return set_dvi_preset(preset_dvi_1280X960, 1280, 960);
else if (!strncmp(displaytype, "dvi1280x1024", 12))
return set_dvi_preset(preset_dvi_1280X1024, 1280, 1024);
+ else if (!strncmp(displaytype, "dataimage480x800", 16))
+ return set_dataimage_preset(preset_dataimage_480X800, 480, 800);
return NONE;
}
@@ -401,12 +424,31 @@
clrsetbits_le32(&prcm->clksel_dss, 0xF, 3);
}
+#ifdef CONFIG_SCF0403_LCD
+static void scf0403_enable(void)
+{
+ gpio_direction_output(58, 1);
+ scf0403_init(157);
+}
+#else
+static inline void scf0403_enable(void) {}
+#endif
+
void lcd_enable(void)
{
- if (lcd_def == DVI || lcd_def == DVI_CUSTOM) {
+ switch (lcd_def) {
+ case NONE:
+ return;
+ case DVI:
+ case DVI_CUSTOM:
gpio_direction_output(54, 0); /* Turn on DVI */
- omap3_dss_enable();
+ break;
+ case DATA_IMAGE:
+ scf0403_enable();
+ break;
}
+
+ omap3_dss_enable();
}
void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue) {}
diff --git a/board/compulab/trimslice/Makefile b/board/compulab/trimslice/Makefile
index 0818673..f3bd00d 100644
--- a/board/compulab/trimslice/Makefile
+++ b/board/compulab/trimslice/Makefile
@@ -5,8 +5,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-$(shell mkdir -p $(obj)../../nvidia/common)
-
obj-y := trimslice.o
include ../../nvidia/common/common.mk
diff --git a/board/davinci/da8xxevm/u-boot-spl-hawk.lds b/board/davinci/da8xxevm/u-boot-spl-hawk.lds
index e43130a..d49c314 100644
--- a/board/davinci/da8xxevm/u-boot-spl-hawk.lds
+++ b/board/davinci/da8xxevm/u-boot-spl-hawk.lds
@@ -19,8 +19,8 @@
.text :
{
arch/arm/cpu/arm926ejs/start.o (.text*)
- arch/arm/cpu/arm926ejs/davinci/libdavinci.o (.text*)
- drivers/mtd/nand/libnand.o (.text*)
+ arch/arm/cpu/arm926ejs/davinci/built-in.o (.text*)
+ drivers/mtd/nand/built-in.o (.text*)
*(.text*)
}
diff --git a/board/dvlhost/u-boot.lds b/board/dvlhost/u-boot.lds
index 057d94b..ebcaf44 100644
--- a/board/dvlhost/u-boot.lds
+++ b/board/dvlhost/u-boot.lds
@@ -16,10 +16,10 @@
.text : {
*(.__image_copy_start)
arch/arm/cpu/ixp/start.o(.text*)
- net/libnet.o(.text*)
- board/dvlhost/libdvlhost.o(.text*)
- arch/arm/cpu/ixp/libixp.o(.text*)
- drivers/serial/libserial.o(.text*)
+ net/built-in.o(.text*)
+ board/dvlhost/built-in.o(.text*)
+ arch/arm/cpu/ixp/built-in.o(.text*)
+ drivers/serial/built-in.o(.text*)
. = env_offset;
common/env_embedded.o(.ppcenv)
diff --git a/board/emk/top5200/Makefile b/board/emk/top5200/Makefile
index 0930d48..b455c26 100644
--- a/board/emk/top5200/Makefile
+++ b/board/emk/top5200/Makefile
@@ -5,8 +5,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
obj-y := top5200.o ../common/flash.o ../common/vpd.o ../common/am79c874.o
diff --git a/board/emk/top860/Makefile b/board/emk/top860/Makefile
index b2645f6..0401639 100644
--- a/board/emk/top860/Makefile
+++ b/board/emk/top860/Makefile
@@ -5,7 +5,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
obj-y = top860.o ../common/flash.o ../common/vpd.o ../common/am79c874.o
diff --git a/board/esd/adciop/Makefile b/board/esd/adciop/Makefile
index a096e44..d0e264d 100644
--- a/board/esd/adciop/Makefile
+++ b/board/esd/adciop/Makefile
@@ -5,8 +5,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
obj-y = adciop.o flash.o ../common/misc.o ../common/pci.o
diff --git a/board/esd/apc405/Makefile b/board/esd/apc405/Makefile
index c6ab1a5..ada8bfd 100644
--- a/board/esd/apc405/Makefile
+++ b/board/esd/apc405/Makefile
@@ -5,10 +5,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
obj-y = apc405.o \
../common/misc.o \
../common/auto_update.o
diff --git a/board/esd/ar405/Makefile b/board/esd/ar405/Makefile
index 2d16313..dd54f54 100644
--- a/board/esd/ar405/Makefile
+++ b/board/esd/ar405/Makefile
@@ -5,8 +5,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
obj-y = ar405.o flash.o ../common/misc.o
diff --git a/board/esd/ash405/Makefile b/board/esd/ash405/Makefile
index 4c866ee..aab8de4 100644
--- a/board/esd/ash405/Makefile
+++ b/board/esd/ash405/Makefile
@@ -5,10 +5,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
obj-y = ash405.o flash.o \
../common/misc.o \
../common/esd405ep_nand.o \
diff --git a/board/esd/cms700/Makefile b/board/esd/cms700/Makefile
index 8cfe3ba..2bf5006 100644
--- a/board/esd/cms700/Makefile
+++ b/board/esd/cms700/Makefile
@@ -5,10 +5,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common/xilinx_jtag)
-endif
-
# Objects for Xilinx JTAG programming (CPLD)
CPLD = ../common/xilinx_jtag/lenval.o \
../common/xilinx_jtag/micro.o \
diff --git a/board/esd/cpci2dp/Makefile b/board/esd/cpci2dp/Makefile
index 1d15020..ce2c6dd 100644
--- a/board/esd/cpci2dp/Makefile
+++ b/board/esd/cpci2dp/Makefile
@@ -5,8 +5,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
obj-y = cpci2dp.o flash.o ../common/misc.o ../common/cmd_loadpci.o
diff --git a/board/esd/cpci405/Makefile b/board/esd/cpci405/Makefile
index 1af7e94..b140571 100644
--- a/board/esd/cpci405/Makefile
+++ b/board/esd/cpci405/Makefile
@@ -5,9 +5,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
obj-y = cpci405.o flash.o ../common/misc.o ../common/auto_update.o
obj-y += ../common/cmd_loadpci.o
diff --git a/board/esd/cpci5200/Makefile b/board/esd/cpci5200/Makefile
index fb6c0e2..8421f54 100644
--- a/board/esd/cpci5200/Makefile
+++ b/board/esd/cpci5200/Makefile
@@ -5,10 +5,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-# ifneq ($(OBJTREE),$(SRCTREE))
-# $(shell mkdir -p $(obj)../common/xilinx_jtag)
-# endif
-
# Objects for Xilinx JTAG programming (CPLD)
# CPLD = ../common/xilinx_jtag/lenval.o \
# ../common/xilinx_jtag/micro.o \
diff --git a/board/esd/cpci750/Makefile b/board/esd/cpci750/Makefile
index 8b3dc33..a3300c9 100644
--- a/board/esd/cpci750/Makefile
+++ b/board/esd/cpci750/Makefile
@@ -8,10 +8,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../../Marvell/common)
-endif
-
obj-y = misc.o
obj-y += cpci750.o serial.o ../../Marvell/common/memory.o pci.o \
mv_eth.o mpsc.o i2c.o \
diff --git a/board/esd/cpciiser4/Makefile b/board/esd/cpciiser4/Makefile
index 4d3c34a..b8d6bea 100644
--- a/board/esd/cpciiser4/Makefile
+++ b/board/esd/cpciiser4/Makefile
@@ -5,8 +5,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
obj-y = cpciiser4.o flash.o ../common/misc.o
diff --git a/board/esd/dasa_sim/Makefile b/board/esd/dasa_sim/Makefile
index f0a5a8f..eb9f5f8 100644
--- a/board/esd/dasa_sim/Makefile
+++ b/board/esd/dasa_sim/Makefile
@@ -5,8 +5,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
obj-y = dasa_sim.o flash.o cmd_dasa_sim.o eeprom.o ../common/pci.o
diff --git a/board/esd/dp405/Makefile b/board/esd/dp405/Makefile
index 6809c67..cfcfb66 100644
--- a/board/esd/dp405/Makefile
+++ b/board/esd/dp405/Makefile
@@ -5,10 +5,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common/xilinx_jtag)
-endif
-
# Objects for Xilinx JTAG programming (CPLD)
CPLD = ../common/xilinx_jtag/lenval.o \
../common/xilinx_jtag/micro.o \
diff --git a/board/esd/du405/Makefile b/board/esd/du405/Makefile
index 12ce41a..7914eab 100644
--- a/board/esd/du405/Makefile
+++ b/board/esd/du405/Makefile
@@ -5,8 +5,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
obj-y = du405.o flash.o ../common/misc.o
diff --git a/board/esd/hh405/Makefile b/board/esd/hh405/Makefile
index 0507f1b..fba21a3 100644
--- a/board/esd/hh405/Makefile
+++ b/board/esd/hh405/Makefile
@@ -5,10 +5,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
obj-y = hh405.o flash.o \
../common/misc.o \
../common/esd405ep_nand.o \
diff --git a/board/esd/hub405/Makefile b/board/esd/hub405/Makefile
index 5447a95..99e18b5 100644
--- a/board/esd/hub405/Makefile
+++ b/board/esd/hub405/Makefile
@@ -5,10 +5,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
obj-y = hub405.o flash.o \
../common/misc.o \
../common/esd405ep_nand.o \
diff --git a/board/esd/ocrtc/Makefile b/board/esd/ocrtc/Makefile
index 0d9a6fd..44b7d5d 100644
--- a/board/esd/ocrtc/Makefile
+++ b/board/esd/ocrtc/Makefile
@@ -5,8 +5,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
obj-y = ocrtc.o flash.o ../common/misc.o cmd_ocrtc.o
diff --git a/board/esd/pci405/Makefile b/board/esd/pci405/Makefile
index 2f8706b..9e659c7 100644
--- a/board/esd/pci405/Makefile
+++ b/board/esd/pci405/Makefile
@@ -5,9 +5,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
obj-y = pci405.o flash.o ../common/misc.o cmd_pci405.o
obj-y += writeibm.o
diff --git a/board/esd/pf5200/Makefile b/board/esd/pf5200/Makefile
index a9d20c9..a54289c 100644
--- a/board/esd/pf5200/Makefile
+++ b/board/esd/pf5200/Makefile
@@ -5,10 +5,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-# ifneq ($(OBJTREE),$(SRCTREE))
-# $(shell mkdir -p $(obj)../common/xilinx_jtag)
-# endif
-
# Objects for Xilinx JTAG programming (CPLD)
# CPLD = ../common/xilinx_jtag/lenval.o \
# ../common/xilinx_jtag/micro.o \
diff --git a/board/esd/plu405/Makefile b/board/esd/plu405/Makefile
index 45b962f..6ffae67 100644
--- a/board/esd/plu405/Makefile
+++ b/board/esd/plu405/Makefile
@@ -5,10 +5,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
obj-y = plu405.o flash.o \
../common/misc.o \
../common/esd405ep_nand.o \
diff --git a/board/esd/pmc405/Makefile b/board/esd/pmc405/Makefile
index f4aa1c9..ad98207 100644
--- a/board/esd/pmc405/Makefile
+++ b/board/esd/pmc405/Makefile
@@ -5,10 +5,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common/xilinx_jtag)
-endif
-
# Objects for Xilinx JTAG programming (CPLD)
CPLD = ../common/xilinx_jtag/lenval.o \
../common/xilinx_jtag/micro.o \
diff --git a/board/esd/pmc405de/Makefile b/board/esd/pmc405de/Makefile
index 7d5b273..b3f6dcd 100644
--- a/board/esd/pmc405de/Makefile
+++ b/board/esd/pmc405de/Makefile
@@ -5,10 +5,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
obj-y = pmc405de.o
obj-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
obj-y += ../common/cmd_loadpci.o
diff --git a/board/esd/pmc440/Makefile b/board/esd/pmc440/Makefile
index b1318c7..708e9d1 100644
--- a/board/esd/pmc440/Makefile
+++ b/board/esd/pmc440/Makefile
@@ -5,10 +5,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
obj-y = pmc440.o cmd_pmc440.o sdram.o fpga.o \
../common/cmd_loadpci.o
extra-y += init.o
diff --git a/board/esd/voh405/Makefile b/board/esd/voh405/Makefile
index 8fcfa37..3d82399 100644
--- a/board/esd/voh405/Makefile
+++ b/board/esd/voh405/Makefile
@@ -5,10 +5,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
obj-y = voh405.o flash.o \
../common/misc.o \
../common/esd405ep_nand.o \
diff --git a/board/esd/vom405/Makefile b/board/esd/vom405/Makefile
index c8a4a4e..7cf5c02 100644
--- a/board/esd/vom405/Makefile
+++ b/board/esd/vom405/Makefile
@@ -5,10 +5,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common/xilinx_jtag)
-endif
-
# Objects for Xilinx JTAG programming (CPLD)
CPLD = ../common/xilinx_jtag/lenval.o \
../common/xilinx_jtag/micro.o \
diff --git a/board/esd/wuh405/Makefile b/board/esd/wuh405/Makefile
index 046ebad..b9beeff 100644
--- a/board/esd/wuh405/Makefile
+++ b/board/esd/wuh405/Makefile
@@ -5,10 +5,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
obj-y = wuh405.o flash.o \
../common/misc.o \
../common/esd405ep_nand.o \
diff --git a/board/esteem192e/u-boot.lds b/board/esteem192e/u-boot.lds
index 87642d6..59a86bf 100644
--- a/board/esteem192e/u-boot.lds
+++ b/board/esteem192e/u-boot.lds
@@ -18,8 +18,8 @@
arch/powerpc/cpu/mpc8xx/start.o (.text*)
arch/powerpc/cpu/mpc8xx/traps.o (.text*)
- net/libnet.o (.text*)
- board/esteem192e/libesteem192e.o (.text*)
+ net/built-in.o (.text*)
+ board/esteem192e/built-in.o (.text*)
. = env_offset;
common/env_embedded.o (.text*)
diff --git a/board/exmeritus/hww1u1a/ddr.c b/board/exmeritus/hww1u1a/ddr.c
index 23a71d5..e1f6865 100644
--- a/board/exmeritus/hww1u1a/ddr.c
+++ b/board/exmeritus/hww1u1a/ddr.c
@@ -9,8 +9,8 @@
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
diff --git a/board/exmeritus/hww1u1a/hww1u1a.c b/board/exmeritus/hww1u1a/hww1u1a.c
index 7c11e38..97b84b3 100644
--- a/board/exmeritus/hww1u1a/hww1u1a.c
+++ b/board/exmeritus/hww1u1a/hww1u1a.c
@@ -13,7 +13,7 @@
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/io.h>
#include <miiphy.h>
#include <libfdt.h>
@@ -37,6 +37,7 @@
unsigned int gpio_low = 0;
unsigned int gpio_in = 0;
unsigned int i;
+ struct ccsr_ddr __iomem *ddr;
puts("Board: HWW-1U-1A ");
@@ -89,7 +90,7 @@
* and delay a while before we continue.
*/
if (mpc85xx_gpio_get(GPIO_RESETS)) {
- ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
+ ddr = (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
puts("Debugger detected... extra device reset enabled!\n");
diff --git a/board/freescale/b4860qds/ddr.c b/board/freescale/b4860qds/ddr.c
index 2d14923..187c3b3 100644
--- a/board/freescale/b4860qds/ddr.c
+++ b/board/freescale/b4860qds/ddr.c
@@ -9,11 +9,11 @@
#include <common.h>
#include <i2c.h>
#include <hwconfig.h>
+#include <fsl_ddr.h>
#include <asm/mmu.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
#include <asm/fsl_law.h>
-#include <../arch/powerpc/cpu/mpc8xxx/ddr/ddr.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/board/freescale/bsc9131rdb/ddr.c b/board/freescale/bsc9131rdb/ddr.c
index a9e92f2..339c576 100644
--- a/board/freescale/bsc9131rdb/ddr.c
+++ b/board/freescale/bsc9131rdb/ddr.c
@@ -8,8 +8,8 @@
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/processor.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
#include <asm/io.h>
#include <asm/fsl_law.h>
diff --git a/board/freescale/bsc9131rdb/spl_minimal.c b/board/freescale/bsc9131rdb/spl_minimal.c
index dd5ea95..bd8560b 100644
--- a/board/freescale/bsc9131rdb/spl_minimal.c
+++ b/board/freescale/bsc9131rdb/spl_minimal.c
@@ -10,7 +10,7 @@
#include <nand.h>
#include <linux/compiler.h>
#include <asm/fsl_law.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -20,7 +20,8 @@
*/
static void sdram_init(void)
{
- ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
+ struct ccsr_ddr __iomem *ddr =
+ (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
__raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
__raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
diff --git a/board/freescale/bsc9132qds/bsc9132qds.c b/board/freescale/bsc9132qds/bsc9132qds.c
index a895e4e..9377280 100644
--- a/board/freescale/bsc9132qds/bsc9132qds.c
+++ b/board/freescale/bsc9132qds/bsc9132qds.c
@@ -17,10 +17,10 @@
#include <tsec.h>
#include <mmc.h>
#include <netdev.h>
-#include <asm/fsl_ifc.h>
+#include <fsl_ifc.h>
#include <hwconfig.h>
#include <i2c.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#ifdef CONFIG_PCI
#include <pci.h>
@@ -133,16 +133,16 @@
*copy the ddr controller settings from PowerPC side DDR controller
*to the DSP DDR controller as connected DDR memories are similar.
*/
- ccsr_ddr_t __iomem *pa_ddr =
- (ccsr_ddr_t __iomem *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
- ccsr_ddr_t temp_ddr;
- ccsr_ddr_t __iomem *dsp_ddr =
- (ccsr_ddr_t __iomem *)CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR;
+ struct ccsr_ddr __iomem *pa_ddr =
+ (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
+ struct ccsr_ddr temp_ddr;
+ struct ccsr_ddr __iomem *dsp_ddr =
+ (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR;
- memcpy(&temp_ddr, pa_ddr, sizeof(ccsr_ddr_t));
+ memcpy(&temp_ddr, pa_ddr, sizeof(struct ccsr_ddr));
temp_ddr.cs0_bnds = CONFIG_SYS_DDR1_CS0_BNDS;
temp_ddr.sdram_cfg &= ~SDRAM_CFG_MEM_EN;
- memcpy(dsp_ddr, &temp_ddr, sizeof(ccsr_ddr_t));
+ memcpy(dsp_ddr, &temp_ddr, sizeof(struct ccsr_ddr));
dsp_ddr->sdram_cfg |= SDRAM_CFG_MEM_EN;
}
diff --git a/board/freescale/bsc9132qds/ddr.c b/board/freescale/bsc9132qds/ddr.c
index b3130be..43f163a 100644
--- a/board/freescale/bsc9132qds/ddr.c
+++ b/board/freescale/bsc9132qds/ddr.c
@@ -8,8 +8,8 @@
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/processor.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
#include <asm/io.h>
#include <asm/fsl_law.h>
diff --git a/board/freescale/bsc9132qds/spl_minimal.c b/board/freescale/bsc9132qds/spl_minimal.c
index 2bf0a0c..8f71431 100644
--- a/board/freescale/bsc9132qds/spl_minimal.c
+++ b/board/freescale/bsc9132qds/spl_minimal.c
@@ -10,14 +10,15 @@
#include <nand.h>
#include <linux/compiler.h>
#include <asm/fsl_law.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
static void sdram_init(void)
{
- ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
+ struct ccsr_ddr __iomem *ddr =
+ (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
#if CONFIG_DDR_CLK_FREQ == 100000000
__raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
__raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
diff --git a/board/freescale/c29xpcie/c29xpcie.c b/board/freescale/c29xpcie/c29xpcie.c
index 48c4b30..f964d61 100644
--- a/board/freescale/c29xpcie/c29xpcie.c
+++ b/board/freescale/c29xpcie/c29xpcie.c
@@ -18,7 +18,7 @@
#include <mmc.h>
#include <netdev.h>
#include <pci.h>
-#include <asm/fsl_ifc.h>
+#include <fsl_ifc.h>
#include <asm/fsl_pci.h>
#include "cpld.h"
diff --git a/board/freescale/c29xpcie/ddr.c b/board/freescale/c29xpcie/ddr.c
index 57a9b61..968655c 100644
--- a/board/freescale/c29xpcie/ddr.c
+++ b/board/freescale/c29xpcie/ddr.c
@@ -6,8 +6,8 @@
#include <common.h>
#include <asm/fsl_law.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
#include "cpld.h"
diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c
index 18e2ff6..e7e893a 100644
--- a/board/freescale/corenet_ds/ddr.c
+++ b/board/freescale/corenet_ds/ddr.c
@@ -10,8 +10,8 @@
#include <i2c.h>
#include <hwconfig.h>
#include <asm/mmu.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
#include <asm/fsl_law.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/board/freescale/corenet_ds/eth_p4080.c b/board/freescale/corenet_ds/eth_p4080.c
index e5beb55..5cbec7f 100644
--- a/board/freescale/corenet_ds/eth_p4080.c
+++ b/board/freescale/corenet_ds/eth_p4080.c
@@ -12,7 +12,7 @@
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_law.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
diff --git a/board/freescale/corenet_ds/p3041ds_ddr.c b/board/freescale/corenet_ds/p3041ds_ddr.c
index 5a8ed94..4dead9c 100644
--- a/board/freescale/corenet_ds/p3041ds_ddr.c
+++ b/board/freescale/corenet_ds/p3041ds_ddr.c
@@ -7,7 +7,7 @@
*/
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
fixed_ddr_parm_t fixed_ddr_parm_0[] = {
{0, 0, NULL}
diff --git a/board/freescale/corenet_ds/p4080ds_ddr.c b/board/freescale/corenet_ds/p4080ds_ddr.c
index 844e1d7..d572a5f 100644
--- a/board/freescale/corenet_ds/p4080ds_ddr.c
+++ b/board/freescale/corenet_ds/p4080ds_ddr.c
@@ -7,7 +7,7 @@
*/
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#define CONFIG_SYS_DDR_TIMING_3_1200 0x01030000
#define CONFIG_SYS_DDR_TIMING_0_1200 0xCC550104
diff --git a/board/freescale/corenet_ds/p5020ds_ddr.c b/board/freescale/corenet_ds/p5020ds_ddr.c
index e65de36..9aaf6db 100644
--- a/board/freescale/corenet_ds/p5020ds_ddr.c
+++ b/board/freescale/corenet_ds/p5020ds_ddr.c
@@ -7,7 +7,7 @@
*/
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
fixed_ddr_parm_t fixed_ddr_parm_0[] = {
{0, 0, NULL}
diff --git a/board/freescale/corenet_ds/p5040ds_ddr.c b/board/freescale/corenet_ds/p5040ds_ddr.c
index e65de36..9aaf6db 100644
--- a/board/freescale/corenet_ds/p5040ds_ddr.c
+++ b/board/freescale/corenet_ds/p5040ds_ddr.c
@@ -7,7 +7,7 @@
*/
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
fixed_ddr_parm_t fixed_ddr_parm_0[] = {
{0, 0, NULL}
diff --git a/board/freescale/m52277evb/config.mk b/board/freescale/m52277evb/config.mk
deleted file mode 100644
index 0ffb0a2..0000000
--- a/board/freescale/m52277evb/config.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# (C) Copyright 2000-2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
-
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE)
diff --git a/board/freescale/m52277evb/u-boot.lds b/board/freescale/m52277evb/u-boot.lds
index f3337a3..70121d9 100644
--- a/board/freescale/m52277evb/u-boot.lds
+++ b/board/freescale/m52277evb/u-boot.lds
@@ -13,8 +13,8 @@
.text :
{
arch/m68k/cpu/mcf5227x/start.o (.text*)
- arch/m68k/cpu/mcf5227x/libmcf5227x.o (.text*)
- arch/m68k/lib/libm68k.o (.text*)
+ arch/m68k/cpu/mcf5227x/built-in.o (.text*)
+ arch/m68k/lib/built-in.o (.text*)
*(.text*)
}
diff --git a/board/freescale/m5235evb/config.mk b/board/freescale/m5235evb/config.mk
deleted file mode 100644
index 9ab4582..0000000
--- a/board/freescale/m5235evb/config.mk
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# (C) Copyright 2000-2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-/*CONFIG_SYS_TEXT_BASE = 0xFFC00000*/
-sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
-
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE)
diff --git a/board/freescale/m53017evb/u-boot.lds b/board/freescale/m53017evb/u-boot.lds
index ef21299..de8d09b 100644
--- a/board/freescale/m53017evb/u-boot.lds
+++ b/board/freescale/m53017evb/u-boot.lds
@@ -12,9 +12,9 @@
/* Read-only sections, merged into text segment: */
.text :
{
- arch/m68k/cpu/mcf532x/start.o (.text*)
- arch/m68k/cpu/mcf532x/libmcf532x.o (.text*)
- arch/m68k/lib/libm68k.o (.text*)
+ arch/m68k/cpu/mcf532x/start.o (.text*)
+ arch/m68k/cpu/mcf532x/built-in.o (.text*)
+ arch/m68k/lib/built-in.o (.text*)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o (.text*)
diff --git a/board/freescale/m54451evb/config.mk b/board/freescale/m54451evb/config.mk
deleted file mode 100644
index 0ffb0a2..0000000
--- a/board/freescale/m54451evb/config.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# (C) Copyright 2000-2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
-
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE)
diff --git a/board/freescale/m54455evb/config.mk b/board/freescale/m54455evb/config.mk
deleted file mode 100644
index 0ffb0a2..0000000
--- a/board/freescale/m54455evb/config.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# (C) Copyright 2000-2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
-
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE)
diff --git a/board/freescale/mpc8349emds/Makefile b/board/freescale/mpc8349emds/Makefile
index 23880f5..5c315f9 100644
--- a/board/freescale/mpc8349emds/Makefile
+++ b/board/freescale/mpc8349emds/Makefile
@@ -7,4 +7,4 @@
obj-y += mpc8349emds.o
obj-$(CONFIG_PCI) += pci.o
-obj-$(CONFIG_FSL_DDR2) += ddr.o
+obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o
diff --git a/board/freescale/mpc8349emds/ddr.c b/board/freescale/mpc8349emds/ddr.c
index 3d257d0..aae003d 100644
--- a/board/freescale/mpc8349emds/ddr.c
+++ b/board/freescale/mpc8349emds/ddr.c
@@ -6,8 +6,8 @@
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
struct board_specific_parameters {
u32 n_ranks;
diff --git a/board/freescale/mpc8349emds/mpc8349emds.c b/board/freescale/mpc8349emds/mpc8349emds.c
index ec48487..d909220 100644
--- a/board/freescale/mpc8349emds/mpc8349emds.c
+++ b/board/freescale/mpc8349emds/mpc8349emds.c
@@ -12,8 +12,8 @@
#include <i2c.h>
#include <spi.h>
#include <miiphy.h>
-#ifdef CONFIG_FSL_DDR2
-#include <asm/fsl_ddr_sdram.h>
+#ifdef CONFIG_SYS_FSL_DDR2
+#include <fsl_ddr_sdram.h>
#else
#include <spd_sdram.h>
#endif
@@ -57,7 +57,7 @@
/* DDR SDRAM - Main SODIMM */
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
#if defined(CONFIG_SPD_EEPROM)
-#ifndef CONFIG_FSL_DDR2
+#ifndef CONFIG_SYS_FSL_DDR2
msize = spd_sdram() * 1024 * 1024;
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
ddr_enable_ecc(msize);
diff --git a/board/freescale/mpc8536ds/ddr.c b/board/freescale/mpc8536ds/ddr.c
index d10370c..ebe3ba4 100644
--- a/board/freescale/mpc8536ds/ddr.c
+++ b/board/freescale/mpc8536ds/ddr.c
@@ -8,8 +8,8 @@
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c
index 5daab69..467f4f2 100644
--- a/board/freescale/mpc8536ds/mpc8536ds.c
+++ b/board/freescale/mpc8536ds/mpc8536ds.c
@@ -12,7 +12,7 @@
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/io.h>
#include <asm/fsl_serdes.h>
#include <spd.h>
@@ -90,7 +90,7 @@
phys_size_t fixed_sdram (void)
{
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+ struct ccsr_ddr __iomem *ddr = &immap->im_ddr;
uint d_init;
ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
diff --git a/board/freescale/mpc8540ads/ddr.c b/board/freescale/mpc8540ads/ddr.c
index 9e79815..41d4cfe 100644
--- a/board/freescale/mpc8540ads/ddr.c
+++ b/board/freescale/mpc8540ads/ddr.c
@@ -8,8 +8,8 @@
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
diff --git a/board/freescale/mpc8540ads/mpc8540ads.c b/board/freescale/mpc8540ads/mpc8540ads.c
index 175eefc..93288c7 100644
--- a/board/freescale/mpc8540ads/mpc8540ads.c
+++ b/board/freescale/mpc8540ads/mpc8540ads.c
@@ -14,7 +14,7 @@
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <libfdt.h>
#include <fdt_support.h>
@@ -168,7 +168,8 @@
phys_size_t fixed_sdram(void)
{
#ifndef CONFIG_SYS_RAMBOOT
- volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR);
+ struct ccsr_ddr __iomem *ddr =
+ (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
diff --git a/board/freescale/mpc8541cds/ddr.c b/board/freescale/mpc8541cds/ddr.c
index 78d73b0..d2ac6c4 100644
--- a/board/freescale/mpc8541cds/ddr.c
+++ b/board/freescale/mpc8541cds/ddr.c
@@ -8,8 +8,8 @@
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
diff --git a/board/freescale/mpc8541cds/mpc8541cds.c b/board/freescale/mpc8541cds/mpc8541cds.c
index 8115e5c..7b264dd 100644
--- a/board/freescale/mpc8541cds/mpc8541cds.c
+++ b/board/freescale/mpc8541cds/mpc8541cds.c
@@ -11,7 +11,7 @@
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <ioports.h>
#include <spd_sdram.h>
#include <libfdt.h>
diff --git a/board/freescale/mpc8544ds/ddr.c b/board/freescale/mpc8544ds/ddr.c
index 6cf9bc1..aa30cab 100644
--- a/board/freescale/mpc8544ds/ddr.c
+++ b/board/freescale/mpc8544ds/ddr.c
@@ -8,8 +8,8 @@
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c
index dfd8fa6..1b33db6 100644
--- a/board/freescale/mpc8544ds/mpc8544ds.c
+++ b/board/freescale/mpc8544ds/mpc8544ds.c
@@ -11,7 +11,7 @@
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <asm/io.h>
#include <miiphy.h>
diff --git a/board/freescale/mpc8548cds/ddr.c b/board/freescale/mpc8548cds/ddr.c
index 996ffe2..b31ea34 100644
--- a/board/freescale/mpc8548cds/ddr.c
+++ b/board/freescale/mpc8548cds/ddr.c
@@ -8,8 +8,8 @@
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c
index 51e4bb5..ca9b43c 100644
--- a/board/freescale/mpc8548cds/mpc8548cds.c
+++ b/board/freescale/mpc8548cds/mpc8548cds.c
@@ -12,7 +12,7 @@
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <miiphy.h>
#include <libfdt.h>
diff --git a/board/freescale/mpc8555cds/ddr.c b/board/freescale/mpc8555cds/ddr.c
index 78d73b0..d2ac6c4 100644
--- a/board/freescale/mpc8555cds/ddr.c
+++ b/board/freescale/mpc8555cds/ddr.c
@@ -8,8 +8,8 @@
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
diff --git a/board/freescale/mpc8555cds/mpc8555cds.c b/board/freescale/mpc8555cds/mpc8555cds.c
index e2093d1..de5f566 100644
--- a/board/freescale/mpc8555cds/mpc8555cds.c
+++ b/board/freescale/mpc8555cds/mpc8555cds.c
@@ -9,7 +9,7 @@
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <ioports.h>
#include <spd_sdram.h>
#include <libfdt.h>
diff --git a/board/freescale/mpc8560ads/ddr.c b/board/freescale/mpc8560ads/ddr.c
index 9e79815..41d4cfe 100644
--- a/board/freescale/mpc8560ads/ddr.c
+++ b/board/freescale/mpc8560ads/ddr.c
@@ -8,8 +8,8 @@
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
diff --git a/board/freescale/mpc8560ads/mpc8560ads.c b/board/freescale/mpc8560ads/mpc8560ads.c
index 90a2522..7104e33 100644
--- a/board/freescale/mpc8560ads/mpc8560ads.c
+++ b/board/freescale/mpc8560ads/mpc8560ads.c
@@ -14,7 +14,7 @@
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <ioports.h>
#include <spd_sdram.h>
#include <miiphy.h>
@@ -373,7 +373,7 @@
phys_size_t fixed_sdram(void)
{
#ifndef CONFIG_SYS_RAMBOOT
- volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR);
+ volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_FSL_DDR_ADDR);
ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
diff --git a/board/freescale/mpc8568mds/ddr.c b/board/freescale/mpc8568mds/ddr.c
index b1f4f1f..6db92ef 100644
--- a/board/freescale/mpc8568mds/ddr.c
+++ b/board/freescale/mpc8568mds/ddr.c
@@ -8,8 +8,8 @@
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c
index ae80697..a8fdcb5 100644
--- a/board/freescale/mpc8568mds/mpc8568mds.c
+++ b/board/freescale/mpc8568mds/mpc8568mds.c
@@ -12,7 +12,7 @@
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <spd_sdram.h>
#include <i2c.h>
diff --git a/board/freescale/mpc8569mds/ddr.c b/board/freescale/mpc8569mds/ddr.c
index 68f686b..ef404b1 100644
--- a/board/freescale/mpc8569mds/ddr.c
+++ b/board/freescale/mpc8569mds/ddr.c
@@ -8,8 +8,8 @@
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c
index c928a96..cb55e1c 100644
--- a/board/freescale/mpc8569mds/mpc8569mds.c
+++ b/board/freescale/mpc8569mds/mpc8569mds.c
@@ -14,7 +14,7 @@
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <asm/io.h>
#include <spd_sdram.h>
@@ -231,7 +231,8 @@
#if !defined(CONFIG_SPD_EEPROM)
phys_size_t fixed_sdram(void)
{
- volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
+ struct ccsr_ddr __iomem *ddr =
+ (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
uint d_init;
out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
diff --git a/board/freescale/mpc8572ds/ddr.c b/board/freescale/mpc8572ds/ddr.c
index 52e4f42..2bfc1a1 100644
--- a/board/freescale/mpc8572ds/ddr.c
+++ b/board/freescale/mpc8572ds/ddr.c
@@ -8,8 +8,8 @@
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
struct board_specific_parameters {
u32 n_ranks;
diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c
index 657df6a..5686322 100644
--- a/board/freescale/mpc8572ds/mpc8572ds.c
+++ b/board/freescale/mpc8572ds/mpc8572ds.c
@@ -12,7 +12,7 @@
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/io.h>
#include <asm/fsl_serdes.h>
#include <miiphy.h>
@@ -62,7 +62,7 @@
phys_size_t fixed_sdram (void)
{
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+ struct ccsr_ddr __iomem *ddr = &immap->im_ddr;
uint d_init;
ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
diff --git a/board/freescale/mpc8610hpcd/Makefile b/board/freescale/mpc8610hpcd/Makefile
index 933ea17..2613004 100644
--- a/board/freescale/mpc8610hpcd/Makefile
+++ b/board/freescale/mpc8610hpcd/Makefile
@@ -4,6 +4,6 @@
#
obj-y += mpc8610hpcd.o
-obj-$(CONFIG_FSL_DDR2) += ddr.o
+obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o
obj-y += law.o
obj-$(CONFIG_FSL_DIU_FB) += mpc8610hpcd_diu.o
diff --git a/board/freescale/mpc8610hpcd/ddr.c b/board/freescale/mpc8610hpcd/ddr.c
index 6cf9bc1..aa30cab 100644
--- a/board/freescale/mpc8610hpcd/ddr.c
+++ b/board/freescale/mpc8610hpcd/ddr.c
@@ -8,8 +8,8 @@
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
index ffdcf24..d8740dd 100644
--- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c
+++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
@@ -10,7 +10,7 @@
#include <asm/processor.h>
#include <asm/immap_86xx.h>
#include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <i2c.h>
#include <asm/io.h>
@@ -143,7 +143,7 @@
{
#if !defined(CONFIG_SYS_RAMBOOT)
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
+ struct ccsr_ddr __iomem *ddr = &immap->im_ddr1;
uint d_init;
ddr->cs0_bnds = 0x0000001f;
diff --git a/board/freescale/mpc8641hpcn/Makefile b/board/freescale/mpc8641hpcn/Makefile
index 8d53af8..86c70bc 100644
--- a/board/freescale/mpc8641hpcn/Makefile
+++ b/board/freescale/mpc8641hpcn/Makefile
@@ -7,4 +7,4 @@
obj-y += mpc8641hpcn.o
obj-y += law.o
-obj-$(CONFIG_FSL_DDR2) += ddr.o
+obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o
diff --git a/board/freescale/mpc8641hpcn/ddr.c b/board/freescale/mpc8641hpcn/ddr.c
index 651652a..7cd0395 100644
--- a/board/freescale/mpc8641hpcn/ddr.c
+++ b/board/freescale/mpc8641hpcn/ddr.c
@@ -8,8 +8,8 @@
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
struct board_specific_parameters {
u32 n_ranks;
diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
index 46a543e..a58b5f9 100644
--- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c
+++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
@@ -9,7 +9,7 @@
#include <asm/processor.h>
#include <asm/immap_86xx.h>
#include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <asm/io.h>
#include <libfdt.h>
@@ -64,7 +64,7 @@
{
#if !defined(CONFIG_SYS_RAMBOOT)
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
+ struct ccsr_ddr __iomem *ddr = &immap->im_ddr1;
ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
diff --git a/board/freescale/mx31ads/u-boot.lds b/board/freescale/mx31ads/u-boot.lds
index 6cfca2d..1cca176 100644
--- a/board/freescale/mx31ads/u-boot.lds
+++ b/board/freescale/mx31ads/u-boot.lds
@@ -22,11 +22,11 @@
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/arm/cpu/arm1136/start.o (.text*)
- board/freescale/mx31ads/libmx31ads.o (.text*)
- arch/arm/lib/libarm.o (.text*)
- net/libnet.o (.text*)
- drivers/mtd/libmtd.o (.text*)
+ arch/arm/cpu/arm1136/start.o (.text*)
+ board/freescale/mx31ads/built-in.o (.text*)
+ arch/arm/lib/built-in.o (.text*)
+ net/built-in.o (.text*)
+ drivers/mtd/built-in.o (.text*)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o(.text*)
diff --git a/board/freescale/p1010rdb/README b/board/freescale/p1010rdb/README.P1010RDB-PA
similarity index 97%
rename from board/freescale/p1010rdb/README
rename to board/freescale/p1010rdb/README.P1010RDB-PA
index 7f18aaa..158a1b3 100644
--- a/board/freescale/p1010rdb/README
+++ b/board/freescale/p1010rdb/README.P1010RDB-PA
@@ -204,5 +204,5 @@
=> bootm 1000000 3000000 2000000
-Please contact your local field applications engineer or sales representative
-to obtain related documents, such as P1010-RDB User Guide for details.
+For more details, please refer to P1010RDB User Guide and access website
+www.freescale.com
diff --git a/board/freescale/p1010rdb/README.P1010RDB-PB b/board/freescale/p1010rdb/README.P1010RDB-PB
new file mode 100644
index 0000000..cf459b3
--- /dev/null
+++ b/board/freescale/p1010rdb/README.P1010RDB-PB
@@ -0,0 +1,188 @@
+Overview
+=========
+The P1010RDB-PB is a Freescale Reference Design Board that hosts the P1010 SoC.
+P1010RDB-PB is a variation of previous P1010RDB-PA board.
+
+The P1010 is a cost-effective, low-power, highly integrated host processor
+based on a Power Architecture e500v2 core (maximum core frequency 1GHz),that
+addresses the requirements of several routing, gateways, storage, consumer,
+and industrial applications. Applications of interest include the main CPUs and
+I/O processors in network attached storage (NAS), the voice over IP (VoIP)
+router/gateway, and wireless LAN (WLAN) and industrial controllers.
+
+The P1010RDB-PB board features are as following:
+Memory subsystem:
+ - 1G bytes unbuffered DDR3 SDRAM discrete devices (32-bit bus)
+ - 32M bytes NOR flash single-chip memory
+ - 2G bytes NAND flash memory
+ - 16M bytes SPI memory
+ - 256K bit M24256 I2C EEPROM
+ - I2C Board EEPROM 128x8 bit memory
+ - SD/MMC connector to interface with the SD memory card
+Interfaces:
+ - Three 10/100/1000 BaseT Ethernet ports (One RGMII and two SGMII)
+ - PCIe 2.0: two x1 mini-PCIe slots
+ - SATA 2.0: two SATA interfaces
+ - USB 2.0: one USB interface
+ - FlexCAN: two FlexCAN interfaces (revision 2.0B)
+ - UART: one USB-to-Serial interface
+ - TDM: 2 FXS ports connected via an external SLIC to the TDM interface.
+ 1 FXO port connected via a relay to FXS for switchover to POTS
+
+Board connectors:
+ - Mini-ITX power supply connector
+ - JTAG/COP for debugging
+
+POR: support critical POR setting changed via switch on board
+PCB: 6-layer routing (4-layer signals, 2-layer power and ground)
+
+Physical Memory Map on P1010RDB
+===============================
+Address Start Address End Memory type Attributes
+0x0000_0000 0x3fff_ffff DDR 1G Cacheable
+0xa000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable
+0xee00_0000 0xefff_ffff NOR Flash 32M non-cacheable
+0xffc2_0000 0xffc5_ffff PCI IO range 256K non-cacheable
+0xffa0_0000 0xffaf_ffff NAND Flash 1M cacheable
+0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable
+0xffd0_0000 0xffd0_3fff L1 for Stack 16K Cacheable TLB0
+0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
+
+
+Serial Port Configuration on P1010RDB
+=====================================
+Configure the serial port of the attached computer with the following values:
+ -Data rate: 115200 bps
+ -Number of data bits: 8
+ -Parity: None
+ -Number of Stop bits: 1
+ -Flow Control: Hardware/None
+
+
+P1010RDB-PB default DIP-switch settings
+=======================================
+SW1[1:8]= 10101010
+SW2[1:8]= 11011000
+SW3[1:8]= 10010000
+SW4[1:4]= 1010
+SW5[1:8]= 11111010
+
+
+P1010RDB-PB boot mode settings via DIP-switch
+=============================================
+SW4[1:4]= 1111 and SW3[3:4]= 00 for 16bit NOR boot
+SW4[1:4]= 1010 and SW3[3:4]= 01 for 8bit NAND boot
+SW4[1:4]= 0110 and SW3[3:4]= 00 for SPI boot
+SW4[1:4]= 0111 and SW3[3:4]= 10 for SD boot
+Note: 1 stands for 'on', 0 stands for 'off'
+
+
+Switch P1010RDB-PB boot mode via software without setting DIP-switch
+====================================================================
+=> run boot_bank0 (boot from NOR bank0)
+=> run boot_bank1 (boot from NOR bank1)
+=> run boot_nand (boot from NAND flash)
+=> run boot_spi (boot from SPI flash)
+=> run boot_sd (boot from SD card)
+
+
+Frequency combination support on P1010RDB-PB
+=============================================
+SW1[4:7] SW5[1] SW5[5:8] SW2[2] Core(MHz) Platform(MHz) DDR(MT/s)
+0101 1 1010 0 800 400 800
+1001 1 1010 0 800 400 667
+1010 1 1100 0 667 333 667
+1000 0 1010 0 533 266 667
+0101 1 1010 1 1000 400 800
+1001 1 1010 1 1000 400 667
+
+
+Setting of pin mux
+==================
+Since pins multiplexing, TDM and CAN are muxed with SPI flash.
+SDHC is muxed with IFC. IFC and SPI flash are enabled by default.
+
+To enable TDM:
+=> setenv hwconfig fsl_p1010mux:tdm_can=tdm
+=> save;reset
+
+To enable FlexCAN:
+=> setenv hwconfig fsl_p1010mux:tdm_can=can
+=> save;reset
+
+To enable SDHC in case of NOR/NAND/SPI boot
+ a) For temporary use case in runtime without reboot system
+ run 'mux sdhc' in u-boot to validate SDHC with invalidating IFC.
+
+ b) For long-term use case
+ set 'esdhc' in hwconfig and save it.
+
+To enable IFC in case of SD boot
+ a) For temporary use case in runtime without reboot system
+ run 'mux ifc' in u-boot to validate IFC with invalidating SDHC.
+
+ b) For long-term use case
+ set 'ifc' in hwconfig and save it.
+
+
+Build images for different boot mode
+====================================
+First setup cross compile environment on build host
+ $ export ARCH=powerpc
+ $ export CROSS_COMPILE=<your-compiler-path>/powerpc-linux-gnu-
+
+1. For NOR boot
+ $ make P1010RDB-PB_NOR
+
+2. For NAND boot
+ $ make P1010RDB-PB_NAND
+
+3. For SPI boot
+ $ make P1010RDB-PB_SPIFLASH
+
+4. For SD boot
+ $ make P1010RDB-PB_SDCARD
+
+
+Steps to program images to flash for different boot mode
+========================================================
+1. NOR boot
+ => tftp 1000000 u-boot.bin
+ For bank0
+ => pro off all;era eff80000 efffffff;cp.b 1000000 eff80000 $filesize
+ set SW1[8]=0, SW4[1:4]= 1111 and SW3[3:4]= 00, then power on the board
+
+ For bank1
+ => pro off all;era eef80000 eeffffff;cp.b 1000000 eef80000 $filesize
+ set SW1[8]=1, SW4[1:4]= 1111 and SW3[3:4]= 00, then power on the board
+
+2. NAND boot
+ => tftp 1000000 u-boot-nand.bin
+ => nand erase 0 $filesize; nand write $loadaddr 0 $filesize
+ Set SW4[1:4]= 1010 and SW3[3:4]= 01, then power on the board
+
+3. SPI boot
+ 1) cat p1010rdb-config-header.bin u-boot.bin > u-boot-spi-combined.bin
+ 2) => tftp 1000000 u-boot-spi-combined.bin
+ 3) => sf probe 0; sf erase 0 100000; sf write 1000000 0 100000
+ set SW4[1:4]= 0110 and SW3[3:4]= 00, then power on the board
+
+4. SD boot
+ 1) cat p1010rdb-config-header.bin u-boot.bin > u-boot-sd-combined.bin
+ 2) => tftp 1000000 u-boot-sd-combined.bin
+ 3) => mux sdhc
+ 4) => mmc write 1000000 0 1050
+ set SW4[1:4]= 0111 and SW3[3:4]= 10, then power on the board
+
+
+Boot Linux from network using TFTP on P1010RDB-PB
+=================================================
+Place uImage, p1010rdb.dtb and rootfs files in the TFTP download path.
+ => tftp 1000000 uImage
+ => tftp 2000000 p1010rdb.dtb
+ => tftp 3000000 rootfs.ext2.gz.uboot.p1010rdb
+ => bootm 1000000 3000000 2000000
+
+
+For more details, please refer to P1010RDB-PB User Guide and access website
+www.freescale.com and Freescale QorIQ SDK Infocenter document.
diff --git a/board/freescale/p1010rdb/ddr.c b/board/freescale/p1010rdb/ddr.c
index ab1b41d..b0d95ea 100644
--- a/board/freescale/p1010rdb/ddr.c
+++ b/board/freescale/p1010rdb/ddr.c
@@ -8,8 +8,8 @@
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/processor.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
#include <asm/io.h>
#include <asm/fsl_law.h>
diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c
index e940d22..62caf67 100644
--- a/board/freescale/p1010rdb/p1010rdb.c
+++ b/board/freescale/p1010rdb/p1010rdb.c
@@ -19,7 +19,7 @@
#include <netdev.h>
#include <pci.h>
#include <asm/fsl_serdes.h>
-#include <asm/fsl_ifc.h>
+#include <fsl_ifc.h>
#include <asm/fsl_pci.h>
#include <hwconfig.h>
#include <i2c.h>
diff --git a/board/freescale/p1010rdb/spl_minimal.c b/board/freescale/p1010rdb/spl_minimal.c
index d0e712e..39a5a0f 100644
--- a/board/freescale/p1010rdb/spl_minimal.c
+++ b/board/freescale/p1010rdb/spl_minimal.c
@@ -10,7 +10,7 @@
#include <nand.h>
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/fsl_law.h>
#include <asm/global_data.h>
@@ -19,7 +19,8 @@
void sdram_init(void)
{
- ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
+ struct ccsr_ddr __iomem *ddr =
+ (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
u32 ddr_ratio;
unsigned long ddr_freq_mhz;
diff --git a/board/freescale/p1022ds/ddr.c b/board/freescale/p1022ds/ddr.c
index 94d2c2b..09212bc 100644
--- a/board/freescale/p1022ds/ddr.c
+++ b/board/freescale/p1022ds/ddr.c
@@ -8,8 +8,8 @@
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
struct board_specific_parameters {
u32 n_ranks;
diff --git a/board/freescale/p1022ds/p1022ds.c b/board/freescale/p1022ds/p1022ds.c
index 3d1951c..ba789a4 100644
--- a/board/freescale/p1022ds/p1022ds.c
+++ b/board/freescale/p1022ds/p1022ds.c
@@ -14,7 +14,7 @@
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <asm/io.h>
#include <libfdt.h>
diff --git a/board/freescale/p1022ds/spl_minimal.c b/board/freescale/p1022ds/spl_minimal.c
index 8b34396..6c7e1ac 100644
--- a/board/freescale/p1022ds/spl_minimal.c
+++ b/board/freescale/p1022ds/spl_minimal.c
@@ -9,7 +9,7 @@
#include <asm/io.h>
#include <nand.h>
#include <asm/fsl_law.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
const static u32 sysclk_tbl[] = {
diff --git a/board/freescale/p1023rdb/ddr.c b/board/freescale/p1023rdb/ddr.c
index 9fb61fd..d587df5 100644
--- a/board/freescale/p1023rdb/ddr.c
+++ b/board/freescale/p1023rdb/ddr.c
@@ -8,8 +8,8 @@
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/processor.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
#include <asm/io.h>
#include <asm/fsl_law.h>
diff --git a/board/freescale/p1023rdb/p1023rdb.c b/board/freescale/p1023rdb/p1023rdb.c
index b52b092..d2d4f83 100644
--- a/board/freescale/p1023rdb/p1023rdb.c
+++ b/board/freescale/p1023rdb/p1023rdb.c
@@ -16,7 +16,7 @@
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/fsl_portals.h>
#include <libfdt.h>
#include <fdt_support.h>
diff --git a/board/freescale/p1023rds/p1023rds.c b/board/freescale/p1023rds/p1023rds.c
index 7c54b65..d8c8745 100644
--- a/board/freescale/p1023rds/p1023rds.c
+++ b/board/freescale/p1023rds/p1023rds.c
@@ -16,7 +16,7 @@
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/fsl_portals.h>
#include <libfdt.h>
#include <fdt_support.h>
@@ -58,7 +58,8 @@
phys_size_t fixed_sdram(void)
{
#ifndef CONFIG_SYS_RAMBOOT
- ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
+ struct ccsr_ddr __iomem *ddr =
+ (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
set_next_law(0, LAW_SIZE_2G, LAW_TRGT_IF_DDR_1);
diff --git a/board/freescale/p1_p2_rdb/ddr.c b/board/freescale/p1_p2_rdb/ddr.c
index 5bee22e..17d3bea 100644
--- a/board/freescale/p1_p2_rdb/ddr.c
+++ b/board/freescale/p1_p2_rdb/ddr.c
@@ -8,7 +8,7 @@
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/processor.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/io.h>
#include <asm/fsl_law.h>
diff --git a/board/freescale/p1_p2_rdb_pc/ddr.c b/board/freescale/p1_p2_rdb_pc/ddr.c
index 81cc093..946d503 100644
--- a/board/freescale/p1_p2_rdb_pc/ddr.c
+++ b/board/freescale/p1_p2_rdb_pc/ddr.c
@@ -10,8 +10,8 @@
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/processor.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
#include <asm/io.h>
#include <asm/fsl_law.h>
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
index 50553da..966abb2 100644
--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
@@ -14,7 +14,7 @@
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/io.h>
#include <asm/fsl_law.h>
#include <asm/fsl_lbc.h>
diff --git a/board/freescale/p1_p2_rdb_pc/spl_minimal.c b/board/freescale/p1_p2_rdb_pc/spl_minimal.c
index adfa7b1..92437bc 100644
--- a/board/freescale/p1_p2_rdb_pc/spl_minimal.c
+++ b/board/freescale/p1_p2_rdb_pc/spl_minimal.c
@@ -10,7 +10,7 @@
#include <nand.h>
#include <linux/compiler.h>
#include <asm/fsl_law.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/board/freescale/p1_twr/ddr.c b/board/freescale/p1_twr/ddr.c
index 67f69d7..a2ce75a 100644
--- a/board/freescale/p1_twr/ddr.c
+++ b/board/freescale/p1_twr/ddr.c
@@ -8,8 +8,8 @@
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/processor.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
#include <asm/io.h>
#include <asm/fsl_law.h>
diff --git a/board/freescale/p1_twr/p1_twr.c b/board/freescale/p1_twr/p1_twr.c
index ea8db6f..0e0d058 100644
--- a/board/freescale/p1_twr/p1_twr.c
+++ b/board/freescale/p1_twr/p1_twr.c
@@ -14,7 +14,7 @@
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/io.h>
#include <asm/fsl_law.h>
#include <asm/fsl_lbc.h>
diff --git a/board/freescale/p2020come/ddr.c b/board/freescale/p2020come/ddr.c
index da80477..b642e12 100644
--- a/board/freescale/p2020come/ddr.c
+++ b/board/freescale/p2020come/ddr.c
@@ -5,8 +5,8 @@
*/
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
diff --git a/board/freescale/p2020ds/ddr.c b/board/freescale/p2020ds/ddr.c
index b12141f..debe70b 100644
--- a/board/freescale/p2020ds/ddr.c
+++ b/board/freescale/p2020ds/ddr.c
@@ -8,8 +8,8 @@
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
struct board_specific_parameters {
u32 n_ranks;
@@ -37,7 +37,7 @@
* num| hi| clk| cpo|wrdata|2T
* ranks| mhz|adjst| | delay|
*/
-#ifdef CONFIG_FSL_DDR2
+#ifdef CONFIG_SYS_FSL_DDR2
{2, 549, 4, 0x1f, 2, 0},
{2, 680, 4, 0x1f, 3, 0},
{2, 850, 4, 0x1f, 4, 0},
diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c
index 58a4223..a0cf927 100644
--- a/board/freescale/p2020ds/p2020ds.c
+++ b/board/freescale/p2020ds/p2020ds.c
@@ -12,7 +12,7 @@
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/io.h>
#include <asm/fsl_serdes.h>
#include <miiphy.h>
@@ -68,7 +68,8 @@
phys_size_t fixed_sdram(void)
{
- volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
+ struct ccsr_ddr __iomem *ddr =
+ (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
uint d_init;
ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
diff --git a/board/freescale/p2041rdb/ddr.c b/board/freescale/p2041rdb/ddr.c
index cc1bfae..b8bbcdf 100644
--- a/board/freescale/p2041rdb/ddr.c
+++ b/board/freescale/p2041rdb/ddr.c
@@ -10,8 +10,8 @@
#include <i2c.h>
#include <hwconfig.h>
#include <asm/mmu.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
#include <asm/fsl_law.h>
struct board_specific_parameters {
diff --git a/board/freescale/t1040qds/Makefile b/board/freescale/t1040qds/Makefile
index a2dba6f..93af9eb 100644
--- a/board/freescale/t1040qds/Makefile
+++ b/board/freescale/t1040qds/Makefile
@@ -4,7 +4,7 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y += $(BOARD).o
+obj-y += t1040qds.o
obj-y += ddr.o
obj-$(CONFIG_PCI) += pci.o
obj-y += law.o
diff --git a/board/freescale/t1040qds/ddr.c b/board/freescale/t1040qds/ddr.c
index 4fd17da..da89a36 100644
--- a/board/freescale/t1040qds/ddr.c
+++ b/board/freescale/t1040qds/ddr.c
@@ -8,8 +8,8 @@
#include <i2c.h>
#include <hwconfig.h>
#include <asm/mmu.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
#include <asm/fsl_law.h>
#include "ddr.h"
diff --git a/board/freescale/t1040qds/t1040_pbi.cfg b/board/freescale/t1040qds/t1040_pbi.cfg
new file mode 100644
index 0000000..624398a
--- /dev/null
+++ b/board/freescale/t1040qds/t1040_pbi.cfg
@@ -0,0 +1,27 @@
+#PBI commands
+#Initialize CPC1
+09010000 00200400
+09138000 00000000
+091380c0 00000100
+#Configure CPC1 as 512KB SRAM
+09010100 00000000
+09010104 fffc0007
+09010f00 08000000
+09010000 80000000
+#Configure LAW for CPC1
+09000cf0 00000000
+09000cf4 fffc0000
+09000cf8 81000011
+#Configure alternate space
+09000010 00000000
+09000014 ff000000
+09000018 81000000
+#Configure SPI controller
+09110000 80000403
+09110020 2d170008
+09110024 00100008
+09110028 00100008
+0911002c 00100008
+#Flush PBL data
+09138000 00000000
+091380c0 00000000
diff --git a/board/freescale/t1040qds/t1040_rcw.cfg b/board/freescale/t1040qds/t1040_rcw.cfg
new file mode 100644
index 0000000..0d0dfa5
--- /dev/null
+++ b/board/freescale/t1040qds/t1040_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+# serdes protocol 0x66
+0a10000c 0c000000 00000000 00000000
+66000002 00000000 fc027000 01000000
+00000000 00000000 00000000 00030810
+00000000 03fc500f 00000000 00000000
diff --git a/board/freescale/t104xrdb/Makefile b/board/freescale/t104xrdb/Makefile
new file mode 100644
index 0000000..76c0c94
--- /dev/null
+++ b/board/freescale/t104xrdb/Makefile
@@ -0,0 +1,12 @@
+#
+# Copyright 2013 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+
+obj-y += t104xrdb.o
+obj-y += ddr.o
+obj-$(CONFIG_PCI) += pci.o
+obj-y += law.o
+obj-y += tlb.o
diff --git a/board/freescale/t104xrdb/README b/board/freescale/t104xrdb/README
new file mode 100644
index 0000000..2cd8219
--- /dev/null
+++ b/board/freescale/t104xrdb/README
@@ -0,0 +1,200 @@
+Overview
+--------
+The T1040RDB is a Freescale reference board that hosts the T1040 SoC
+(and variants). Variants inclued T1042 presonality of T1040, in which
+case T1040RDB can also be called T1042RDB.
+
+The T1042RDB_PI is a Freescale reference board that hosts the T1042 SoC.
+(a personality of T1040 SoC). The board is similar to T1040RDB but is
+designed specially with low power features targeted for Printing Image Market.
+
+T1040 SoC Overview
+------------------
+The QorIQ T1040/T1042 processor support four integrated 64-bit e5500 PA
+processor cores with high-performance data path acceleration architecture
+and network peripheral interfaces required for networking & telecommunications.
+
+The T1040/T1042 SoC includes the following function and features:
+
+ - Four e5500 cores, each with a private 256 KB L2 cache
+ - 256 KB shared L3 CoreNet platform cache (CPC)
+ - Interconnect CoreNet platform
+ - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
+ support
+ - Data Path Acceleration Architecture (DPAA) incorporating acceleration
+ for the following functions:
+ - Packet parsing, classification, and distribution
+ - Queue management for scheduling, packet sequencing, and congestion
+ management
+ - Cryptography Acceleration (SEC 5.0)
+ - RegEx Pattern Matching Acceleration (PME 2.2)
+ - IEEE Std 1588 support
+ - Hardware buffer management for buffer allocation and deallocation
+ - Ethernet interfaces
+ - Integrated 8-port Gigabit Ethernet switch (T1040 only)
+ - Four 1 Gbps Ethernet controllers
+ - Two RGMII interfaces or one RGMII and one MII interfaces
+ - High speed peripheral interfaces
+ - Four PCI Express 2.0 controllers running at up to 5 GHz
+ - Two SATA controllers supporting 1.5 and 3.0 Gb/s operation
+ - Upto two QSGMII interface
+ - Upto six SGMII interface supporting 1000 Mbps
+ - One SGMII interface supporting upto 2500 Mbps
+ - Additional peripheral interfaces
+ - Two USB 2.0 controllers with integrated PHY
+ - SD/eSDHC/eMMC
+ - eSPI controller
+ - Four I2C controllers
+ - Four UARTs
+ - Four GPIO controllers
+ - Integrated flash controller (IFC)
+ - LCD and HDMI interface (DIU) with 12 bit dual data rate
+ - TDM interface
+ - Multicore programmable interrupt controller (PIC)
+ - Two 8-channel DMA engines
+ - Single source clocking implementation
+ - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
+
+T1040 SoC Personalities
+-------------------------
+
+T1022 Personality:
+T1022 is a reduced personality of T1040 with less core/clusters.
+
+T1042 Personality:
+T1042 is a reduced personality of T1040 without Integrated 8-port Gigabit
+Ethernet switch. Rest of the blocks are same as T1040
+
+
+T1040RDB board Overview
+-------------------------
+ - SERDES Connections, 8 lanes information:
+ 1: None
+ 2: SGMII
+ 3: QSGMII
+ 4: QSGMII
+ 5: PCIe1 x1 slot
+ 6: mini PCIe connector
+ 7: mini PCIe connector
+ 8: SATA connector
+ - DDR Controller
+ - Supports rates of up to 1600 MHz data-rate
+ - Supports one DDR3LP UDIMM/RDIMMs, of single-, dual- or quad-rank types.
+ - IFC/Local Bus
+ - NAND flash: 1GB 8-bit NAND flash
+ - NOR: 128MB 16-bit NOR Flash
+ - Ethernet
+ - Two on-board RGMII 10/100/1G ethernet ports.
+ - CPLD
+ - Clocks
+ - System and DDR clock (SYSCLK, “DDRCLK”)
+ - SERDES clocks
+ - Power Supplies
+ - USB
+ - Supports two USB 2.0 ports with integrated PHYs
+ - Two type A ports with 5V@1.5A per port.
+ - SDHC
+ - SDHC/SDXC connector
+ - SPI
+ - On-board 64MB SPI flash
+ - Other IO
+ - Two Serial ports
+ - Four I2C ports
+
+T1042RDB_PI board Overview
+-------------------------
+ - SERDES Connections, 8 lanes information:
+ 1, 2, 3, 4 : PCIe x4 slot
+ 5: mini PCIe connector
+ 6: mini PCIe connector
+ 7: NA
+ 8: SATA connector
+ - DDR Controller
+ - Supports rates of up to 1600 MHz data-rate
+ - Supports one DDR3LP UDIMM/RDIMMs, of single-, dual- or quad-rank types.
+ - IFC/Local Bus
+ - NAND flash: 1GB 8-bit NAND flash
+ - NOR: 128MB 16-bit NOR Flash
+ - Ethernet
+ - Two on-board RGMII 10/100/1G ethernet ports.
+ - CPLD
+ - Clocks
+ - System and DDR clock (SYSCLK, “DDRCLK”)
+ - SERDES clocks
+ - Video
+ - DIU supports video at up to 1280x1024x32bpp
+ - Power Supplies
+ - USB
+ - Supports two USB 2.0 ports with integrated PHYs
+ - Two type A ports with 5V@1.5A per port.
+ - SDHC
+ - SDHC/SDXC connector
+ - SPI
+ - On-board 64MB SPI flash
+ - Other IO
+ - Two Serial ports
+ - Four I2C ports
+
+Memory map
+-----------
+The addresses in brackets are physical addresses.
+
+Start Address End Address Description Size
+0xF_FFDF_0000 0xF_FFDF_0FFF IFC - CPLD 4KB
+0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB
+0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB
+0xF_F803_0000 0xF_F803_FFFF PCI Express 4 I/O Space 64KB
+0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB
+0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB
+0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB
+0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB
+0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB
+0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB
+0xF_0000_0000 0xF_003F_FFFF DCSR 4MB
+0xC_3000_0000 0xC_3FFF_FFFF PCI Express 4 Mem Space 256MB
+0xC_2000_0000 0xC_2FFF_FFFF PCI Express 3 Mem Space 256MB
+0xC_1000_0000 0xC_1FFF_FFFF PCI Express 2 Mem Space 256MB
+0xC_0000_0000 0xC_0FFF_FFFF PCI Express 1 Mem Space 256MB
+0x0_0000_0000 0x0_ffff_ffff DDR 2GB
+
+
+NOR Flash memory Map
+---------------------
+ Start End Definition Size
+0xEFF80000 0xEFFFFFFF u-boot (current bank) 512KB
+0xEFF60000 0xEFF7FFFF u-boot env (current bank) 128KB
+0xEFF40000 0xEFF5FFFF FMAN Ucode (current bank) 128KB
+0xED300000 0xEFF3FFFF rootfs (alt bank) 44MB + 256KB
+0xEC800000 0xEC8FFFF Hardware device tree (alt bank) 1MB
+0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB
+0xEC000000 0xEC01FFFF RCW (alt bank) 128KB
+0xEBF80000 0xEBFFFFFF u-boot (alt bank) 512KB
+0xEBF60000 0xEBF7FFFF u-boot env (alt bank) 128KB
+0xEBF40000 0xEBF5FFFF FMAN ucode (alt bank) 128KB
+0xE9300000 0xEBF3FFFF rootfs (current bank) 44MB + 256KB
+0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 11MB + 512KB
+0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB
+0xE8000000 0xE801FFFF RCW (current bank) 128KB
+
+
+Various Software configurations/environment variables/commands
+--------------------------------------------------------------
+The below commands apply to the board
+
+1. U-boot environment variable hwconfig
+ The default hwconfig is:
+ hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;usb1:
+ dr_mode=host,phy_type=utmi
+ Note: For USB gadget set "dr_mode=peripheral"
+
+2. FMAN Ucode versions
+ fsl_fman_ucode_t1040.bin
+
+3. Switching to alternate bank
+ Commands for switching to alternate bank.
+
+ 1. To change from vbank0 to vbank4
+ => qixis_reset altbank (it will boot using vbank4)
+
+ 2.To change from vbank4 to vbank0
+ => qixis reset (it will boot using vbank0)
diff --git a/board/freescale/t104xrdb/ddr.c b/board/freescale/t104xrdb/ddr.c
new file mode 100644
index 0000000..9009afa
--- /dev/null
+++ b/board/freescale/t104xrdb/ddr.c
@@ -0,0 +1,132 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <hwconfig.h>
+#include <asm/mmu.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include <asm/fsl_law.h>
+#include "ddr.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
+ unsigned int controller_number,
+ unsigned int dimm_number)
+{
+ const char dimm_model[] = "RAW timing DDR";
+
+ if ((controller_number == 0) && (dimm_number == 0)) {
+ memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
+ memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
+ memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
+ }
+
+ return 0;
+}
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+ ulong ddr_freq;
+
+ if (ctrl_num > 1) {
+ printf("Not supported controller number %d\n", ctrl_num);
+ return;
+ }
+ if (!pdimm->n_ranks)
+ return;
+
+ pbsp = udimms[0];
+
+ /* Get clk_adjust, cpo, write_data_delay,2t, according to the board ddr
+ * freqency and n_banks specified in board_specific_parameters table.
+ */
+ ddr_freq = get_ddr_freq(0) / 1000000;
+ while (pbsp->datarate_mhz_high) {
+ if (pbsp->n_ranks == pdimm->n_ranks &&
+ (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
+ if (ddr_freq <= pbsp->datarate_mhz_high) {
+ popts->cpo_override = pbsp->cpo;
+ popts->write_data_delay =
+ pbsp->write_data_delay;
+ popts->clk_adjust = pbsp->clk_adjust;
+ popts->wrlvl_start = pbsp->wrlvl_start;
+ popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+ popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+ popts->twot_en = pbsp->force_2t;
+ goto found;
+ }
+ pbsp_highest = pbsp;
+ }
+ pbsp++;
+ }
+
+ if (pbsp_highest) {
+ printf("Error: board specific timing not found\n");
+ printf("for data rate %lu MT/s\n", ddr_freq);
+ printf("Trying to use the highest speed (%u) parameters\n",
+ pbsp_highest->datarate_mhz_high);
+ popts->cpo_override = pbsp_highest->cpo;
+ popts->write_data_delay = pbsp_highest->write_data_delay;
+ popts->clk_adjust = pbsp_highest->clk_adjust;
+ popts->wrlvl_start = pbsp_highest->wrlvl_start;
+ popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+ popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+ popts->twot_en = pbsp_highest->force_2t;
+ } else {
+ panic("DIMM is not supported by this board");
+ }
+found:
+ debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
+ "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
+ "wrlvl_ctrl_3 0x%x\n",
+ pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
+ pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
+ pbsp->wrlvl_ctl_3);
+
+ /*
+ * Factors to consider for half-strength driver enable:
+ * - number of DIMMs installed
+ */
+ popts->half_strength_driver_enable = 0;
+ /*
+ * Write leveling override
+ */
+ popts->wrlvl_override = 1;
+ popts->wrlvl_sample = 0xf;
+
+ /*
+ * rtt and rtt_wr override
+ */
+ popts->rtt_override = 0;
+
+ /* Enable ZQ calibration */
+ popts->zq_en = 1;
+
+ /* DHC_EN =1, ODT = 75 Ohm */
+ popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
+ popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+}
+
+phys_size_t initdram(int board_type)
+{
+ phys_size_t dram_size;
+
+ puts("Initializing....using SPD\n");
+
+ dram_size = fsl_ddr_sdram();
+
+ dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+ dram_size *= 0x100000;
+
+ puts(" DDR: ");
+ return dram_size;
+}
diff --git a/board/freescale/t104xrdb/ddr.h b/board/freescale/t104xrdb/ddr.h
new file mode 100644
index 0000000..9276b59
--- /dev/null
+++ b/board/freescale/t104xrdb/ddr.h
@@ -0,0 +1,76 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __DDR_H__
+#define __DDR_H__
+
+dimm_params_t ddr_raw_timing = {
+ .n_ranks = 2,
+ .rank_density = 2147483648u,
+ .capacity = 4294967296u,
+ .primary_sdram_width = 64,
+ .ec_sdram_width = 8,
+ .registered_dimm = 0,
+ .mirrored_dimm = 1,
+ .n_row_addr = 15,
+ .n_col_addr = 10,
+ .n_banks_per_sdram_device = 8,
+ .edc_config = 2, /* ECC */
+ .burst_lengths_bitmask = 0x0c,
+
+ .tckmin_x_ps = 1071,
+ .caslat_x = 0x2fe << 4, /* 5,6,7,8,9,10,11,13 */
+ .taa_ps = 13910,
+ .twr_ps = 15000,
+ .trcd_ps = 13910,
+ .trrd_ps = 6000,
+ .trp_ps = 13910,
+ .tras_ps = 34000,
+ .trc_ps = 48910,
+ .trfc_ps = 260000,
+ .twtr_ps = 7500,
+ .trtp_ps = 7500,
+ .refresh_rate_ps = 7800000,
+ .tfaw_ps = 35000,
+};
+
+struct board_specific_parameters {
+ u32 n_ranks;
+ u32 datarate_mhz_high;
+ u32 rank_gb;
+ u32 clk_adjust;
+ u32 wrlvl_start;
+ u32 wrlvl_ctl_2;
+ u32 wrlvl_ctl_3;
+ u32 cpo;
+ u32 write_data_delay;
+ u32 force_2t;
+};
+
+/*
+ * These tables contain all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+
+static const struct board_specific_parameters udimm0[] = {
+ /*
+ * memory controller 0
+ * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
+ * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
+ */
+ {2, 1066, 4, 8, 4, 0x05070609, 0x08090a08, 0xff, 2, 0},
+ {2, 1350, 4, 4, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
+ {2, 1350, 0, 5, 7, 0x0709090b, 0x0c0c0d09, 0xff, 2, 0},
+ {2, 1666, 4, 4, 8, 0x080a0a0d, 0x0d10100b, 0xff, 2, 0},
+ {2, 1666, 0, 5, 7, 0x080a0a0c, 0x0d0d0e0a, 0xff, 2, 0},
+ {}
+};
+
+static const struct board_specific_parameters *udimms[] = {
+ udimm0,
+};
+#endif
diff --git a/board/freescale/t104xrdb/law.c b/board/freescale/t104xrdb/law.c
new file mode 100644
index 0000000..2362d43
--- /dev/null
+++ b/board/freescale/t104xrdb/law.c
@@ -0,0 +1,32 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+#ifndef CONFIG_SYS_NO_FLASH
+ SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
+#endif
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+ SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+ SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
+#endif
+#ifdef CONFIG_SYS_CPLD_BASE_PHYS
+ SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC),
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+ SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE_PHYS
+ SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/t104xrdb/pci.c b/board/freescale/t104xrdb/pci.c
new file mode 100644
index 0000000..c53e3b7
--- /dev/null
+++ b/board/freescale/t104xrdb/pci.c
@@ -0,0 +1,23 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/fsl_pci.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/fsl_serdes.h>
+
+void pci_init_board(void)
+{
+ fsl_pcie_init_board(0);
+}
+
+void pci_of_setup(void *blob, bd_t *bd)
+{
+ FT_FSL_PCI_SETUP;
+}
diff --git a/board/freescale/t104xrdb/t104xrdb.c b/board/freescale/t104xrdb/t104xrdb.c
new file mode 100644
index 0000000..6e29d64
--- /dev/null
+++ b/board/freescale/t104xrdb/t104xrdb.c
@@ -0,0 +1,93 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <netdev.h>
+#include <linux/compiler.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <fm_eth.h>
+
+#include "t104xrdb.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ struct cpu_type *cpu = gd->arch.cpu;
+
+ printf("Board: %sRDB\n", cpu->name);
+ return 0;
+}
+
+int board_early_init_r(void)
+{
+#ifdef CONFIG_SYS_FLASH_BASE
+ const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+ const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+ /*
+ * Remap Boot flash region to caching-inhibited
+ * so that flash can be erased properly.
+ */
+
+ /* Flush d-cache and invalidate i-cache of any FLASH data */
+ flush_dcache();
+ invalidate_icache();
+
+ /* invalidate existing TLB entry for flash */
+ disable_tlb(flash_esel);
+
+ set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, flash_esel, BOOKE_PAGESZ_256M, 1);
+#endif
+ set_liodns();
+#ifdef CONFIG_SYS_DPAA_QBMAN
+ setup_portals();
+#endif
+
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ return 0;
+}
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ phys_addr_t base;
+ phys_size_t size;
+
+ ft_cpu_setup(blob, bd);
+
+ base = getenv_bootm_low();
+ size = getenv_bootm_size();
+
+ fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#ifdef CONFIG_PCI
+ pci_of_setup(blob, bd);
+#endif
+
+ fdt_fixup_liodn(blob);
+
+#ifdef CONFIG_HAS_FSL_DR_USB
+ fdt_fixup_dr_usb(blob, bd);
+#endif
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+ fdt_fixup_fman_ethernet(blob);
+#endif
+}
diff --git a/board/freescale/t104xrdb/t104xrdb.h b/board/freescale/t104xrdb/t104xrdb.h
new file mode 100644
index 0000000..e7cc0c7
--- /dev/null
+++ b/board/freescale/t104xrdb/t104xrdb.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __T104x_RDB_H__
+#define __T104x_RDB_H__
+
+void fdt_fixup_board_enet(void *blob);
+void pci_of_setup(void *blob, bd_t *bd);
+
+#endif
diff --git a/board/freescale/t104xrdb/tlb.c b/board/freescale/t104xrdb/tlb.c
new file mode 100644
index 0000000..84f97a4
--- /dev/null
+++ b/board/freescale/t104xrdb/tlb.c
@@ -0,0 +1,107 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /* TLB 1 */
+ /* *I*** - Covers boot page */
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
+ /*
+ * *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the
+ * SRAM is at 0xfffc0000, it covered the 0xfffff000.
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_256K, 1),
+#else
+ SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_4K, 1),
+#endif
+
+ /* *I*G* - CCSRBAR */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_16M, 1),
+
+ /* *I*G* - Flash, localbus */
+ /* This will be changed to *I*G* after relocation to RAM. */
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_256M, 1),
+
+ /* *I*G* - PCI */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_1G, 1),
+
+ /* *I*G* - PCI I/O */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_256K, 1),
+
+ /* Bman/Qman */
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 5, BOOKE_PAGESZ_16M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
+ CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 6, BOOKE_PAGESZ_16M, 1),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 7, BOOKE_PAGESZ_16M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
+ CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 8, BOOKE_PAGESZ_16M, 1),
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 9, BOOKE_PAGESZ_4M, 1),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE
+ /*
+ * *I*G - NAND
+ * entry 14 and 15 has been used hard coded, they will be disabled
+ * in cpu_init_f, so we use entry 16 for nand.
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 10, BOOKE_PAGESZ_64K, 1),
+#endif
+#ifdef CONFIG_SYS_CPLD_BASE
+ SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 11, BOOKE_PAGESZ_256K, 1),
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/t2080qds/Makefile b/board/freescale/t2080qds/Makefile
new file mode 100644
index 0000000..0b8747b
--- /dev/null
+++ b/board/freescale/t2080qds/Makefile
@@ -0,0 +1,12 @@
+#
+# Copyright 2013 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-$(CONFIG_T2080QDS) += t2080qds.o
+obj-$(CONFIG_T2080QDS) += eth_t2080qds.o
+obj-$(CONFIG_PCI) += pci.o
+obj-y += ddr.o
+obj-y += law.o
+obj-y += tlb.o
diff --git a/board/freescale/t2080qds/ddr.c b/board/freescale/t2080qds/ddr.c
new file mode 100644
index 0000000..5db5d21
--- /dev/null
+++ b/board/freescale/t2080qds/ddr.c
@@ -0,0 +1,127 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 or later as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <hwconfig.h>
+#include <asm/mmu.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include <asm/fsl_law.h>
+#include "ddr.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+ ulong ddr_freq;
+
+ if (ctrl_num > 2) {
+ printf("Not supported controller number %d\n", ctrl_num);
+ return;
+ }
+ if (!pdimm->n_ranks)
+ return;
+
+ /*
+ * we use identical timing for all slots. If needed, change the code
+ * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
+ */
+ if (popts->registered_dimm_en)
+ pbsp = rdimms[0];
+ else
+ pbsp = udimms[0];
+
+
+ /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
+ * freqency and n_banks specified in board_specific_parameters table.
+ */
+ ddr_freq = get_ddr_freq(0) / 1000000;
+ while (pbsp->datarate_mhz_high) {
+ if (pbsp->n_ranks == pdimm->n_ranks &&
+ (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
+ if (ddr_freq <= pbsp->datarate_mhz_high) {
+ popts->cpo_override = pbsp->cpo;
+ popts->write_data_delay =
+ pbsp->write_data_delay;
+ popts->clk_adjust = pbsp->clk_adjust;
+ popts->wrlvl_start = pbsp->wrlvl_start;
+ popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+ popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+ popts->twot_en = pbsp->force_2t;
+ goto found;
+ }
+ pbsp_highest = pbsp;
+ }
+ pbsp++;
+ }
+
+ if (pbsp_highest) {
+ printf("Error: board specific timing not found");
+ printf("for data rate %lu MT/s\n", ddr_freq);
+ printf("Trying to use the highest speed (%u) parameters\n",
+ pbsp_highest->datarate_mhz_high);
+ popts->cpo_override = pbsp_highest->cpo;
+ popts->write_data_delay = pbsp_highest->write_data_delay;
+ popts->clk_adjust = pbsp_highest->clk_adjust;
+ popts->wrlvl_start = pbsp_highest->wrlvl_start;
+ popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+ popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+ popts->twot_en = pbsp_highest->force_2t;
+ } else {
+ panic("DIMM is not supported by this board");
+ }
+found:
+ debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
+ "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
+ "wrlvl_ctrl_3 0x%x\n",
+ pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
+ pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
+ pbsp->wrlvl_ctl_3);
+
+ /*
+ * Factors to consider for half-strength driver enable:
+ * - number of DIMMs installed
+ */
+ popts->half_strength_driver_enable = 0;
+ /*
+ * Write leveling override
+ */
+ popts->wrlvl_override = 1;
+ popts->wrlvl_sample = 0xf;
+
+ /*
+ * Rtt and Rtt_WR override
+ */
+ popts->rtt_override = 0;
+
+ /* Enable ZQ calibration */
+ popts->zq_en = 1;
+
+ /* DHC_EN =1, ODT = 75 Ohm */
+ popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
+ popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+}
+
+phys_size_t initdram(int board_type)
+{
+ phys_size_t dram_size;
+
+ puts("Initializing....using SPD\n");
+
+ dram_size = fsl_ddr_sdram();
+
+ dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+ dram_size *= 0x100000;
+
+ puts(" DDR: ");
+ return dram_size;
+}
diff --git a/board/freescale/t2080qds/ddr.h b/board/freescale/t2080qds/ddr.h
new file mode 100644
index 0000000..964eaad
--- /dev/null
+++ b/board/freescale/t2080qds/ddr.h
@@ -0,0 +1,85 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __DDR_H__
+#define __DDR_H__
+struct board_specific_parameters {
+ u32 n_ranks;
+ u32 datarate_mhz_high;
+ u32 rank_gb;
+ u32 clk_adjust;
+ u32 wrlvl_start;
+ u32 wrlvl_ctl_2;
+ u32 wrlvl_ctl_3;
+ u32 cpo;
+ u32 write_data_delay;
+ u32 force_2t;
+};
+
+/*
+ * These tables contain all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+
+static const struct board_specific_parameters udimm0[] = {
+ /*
+ * memory controller 0
+ * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
+ * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
+ */
+ {2, 1350, 4, 4, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
+ {2, 1350, 0, 5, 7, 0x0709090b, 0x0c0c0d09, 0xff, 2, 0},
+ {2, 1666, 4, 4, 8, 0x080a0a0d, 0x0d10100b, 0xff, 2, 0},
+ {2, 1666, 0, 5, 7, 0x080a0a0c, 0x0d0d0e0a, 0xff, 2, 0},
+ {2, 1900, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0},
+ {2, 2140, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0},
+ {1, 1350, 0, 5, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
+ {1, 1700, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0},
+ {1, 1800, 2, 5, 6, 0x06070709, 0x110a0b08, 0xff, 2, 0},
+ {1, 1866, 2, 4, 6, 0x06060708, 0x09090a07, 0xff, 2, 0},
+ {1, 1900, 2, 4, 6, 0x06060708, 0x09090a07, 0xff, 2, 0},
+ {1, 2000, 2, 4, 8, 0x090a0b0d, 0x0e0f110b, 0xff, 2, 0},
+ {1, 2133, 2, 4, 8, 0x090a0b0d, 0x0e0f110b, 0xff, 2, 0},
+ {}
+};
+
+static const struct board_specific_parameters rdimm0[] = {
+ /*
+ * memory controller 0
+ * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
+ * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
+ */
+ {4, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff, 2, 0},
+ {4, 1666, 0, 5, 11, 0x0a080706, 0x07090906, 0xff, 2, 0},
+ {4, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0},
+ {2, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff, 2, 0},
+ {2, 1666, 0, 5, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0},
+ {2, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0},
+ {1, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff, 2, 0},
+ {1, 1666, 0, 5, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0},
+ {1, 2140, 0, 4, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0},
+ {}
+};
+
+/*
+ * The three slots have slightly different timing. The center values are good
+ * for all slots. We use identical speed tables for them. In future use, if
+ * DIMMs require separated tables, make more entries as needed.
+ */
+static const struct board_specific_parameters *udimms[] = {
+ udimm0,
+};
+
+/*
+ * The three slots have slightly different timing. See comments above.
+ */
+static const struct board_specific_parameters *rdimms[] = {
+ rdimm0,
+};
+
+
+#endif
diff --git a/board/freescale/t2080qds/eth_t2080qds.c b/board/freescale/t2080qds/eth_t2080qds.c
new file mode 100644
index 0000000..3613f93
--- /dev/null
+++ b/board/freescale/t2080qds/eth_t2080qds.c
@@ -0,0 +1,511 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * Shengzhou Liu <Shengzhou.Liu@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <netdev.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <malloc.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <miiphy.h>
+#include <phy.h>
+#include <asm/fsl_dtsec.h>
+#include <asm/fsl_serdes.h>
+#include "../common/qixis.h"
+#include "../common/fman.h"
+#include "t2080qds_qixis.h"
+
+#define EMI_NONE 0xFFFFFFFF
+#define EMI1_RGMII1 0
+#define EMI1_RGMII2 1
+#define EMI1_SLOT1 2
+#define EMI1_SLOT2 6
+#define EMI1_SLOT3 3
+#define EMI1_SLOT4 4
+#define EMI1_SLOT5 5
+#define EMI2 7
+
+static int mdio_mux[NUM_FM_PORTS];
+
+static const char * const mdio_names[] = {
+ "T2080QDS_MDIO_RGMII1",
+ "T2080QDS_MDIO_RGMII2",
+ "T2080QDS_MDIO_SLOT1",
+ "T2080QDS_MDIO_SLOT3",
+ "T2080QDS_MDIO_SLOT4",
+ "T2080QDS_MDIO_SLOT5",
+ "T2080QDS_MDIO_SLOT2",
+ "T2080QDS_MDIO_10GC",
+};
+
+/* Map SerDes1 8 lanes to default slot, will be initialized dynamically */
+static u8 lane_to_slot[] = {3, 3, 3, 3, 1, 1, 1, 1};
+
+static const char *T2080qds_mdio_name_for_muxval(u8 muxval)
+{
+ return mdio_names[muxval];
+}
+
+struct mii_dev *mii_dev_for_muxval(u8 muxval)
+{
+ struct mii_dev *bus;
+ const char *name = T2080qds_mdio_name_for_muxval(muxval);
+
+ if (!name) {
+ printf("No bus for muxval %x\n", muxval);
+ return NULL;
+ }
+
+ bus = miiphy_get_dev_by_name(name);
+
+ if (!bus) {
+ printf("No bus by name %s\n", name);
+ return NULL;
+ }
+
+ return bus;
+}
+
+struct T2080qds_mdio {
+ u8 muxval;
+ struct mii_dev *realbus;
+};
+
+static void T2080qds_mux_mdio(u8 muxval)
+{
+ u8 brdcfg4;
+ if (muxval < 7) {
+ brdcfg4 = QIXIS_READ(brdcfg[4]);
+ brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
+ brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
+ QIXIS_WRITE(brdcfg[4], brdcfg4);
+ }
+}
+
+static int T2080qds_mdio_read(struct mii_dev *bus, int addr, int devad,
+ int regnum)
+{
+ struct T2080qds_mdio *priv = bus->priv;
+
+ T2080qds_mux_mdio(priv->muxval);
+
+ return priv->realbus->read(priv->realbus, addr, devad, regnum);
+}
+
+static int T2080qds_mdio_write(struct mii_dev *bus, int addr, int devad,
+ int regnum, u16 value)
+{
+ struct T2080qds_mdio *priv = bus->priv;
+
+ T2080qds_mux_mdio(priv->muxval);
+
+ return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
+}
+
+static int T2080qds_mdio_reset(struct mii_dev *bus)
+{
+ struct T2080qds_mdio *priv = bus->priv;
+
+ return priv->realbus->reset(priv->realbus);
+}
+
+static int T2080qds_mdio_init(char *realbusname, u8 muxval)
+{
+ struct T2080qds_mdio *pmdio;
+ struct mii_dev *bus = mdio_alloc();
+
+ if (!bus) {
+ printf("Failed to allocate T2080QDS MDIO bus\n");
+ return -1;
+ }
+
+ pmdio = malloc(sizeof(*pmdio));
+ if (!pmdio) {
+ printf("Failed to allocate T2080QDS private data\n");
+ free(bus);
+ return -1;
+ }
+
+ bus->read = T2080qds_mdio_read;
+ bus->write = T2080qds_mdio_write;
+ bus->reset = T2080qds_mdio_reset;
+ sprintf(bus->name, T2080qds_mdio_name_for_muxval(muxval));
+
+ pmdio->realbus = miiphy_get_dev_by_name(realbusname);
+
+ if (!pmdio->realbus) {
+ printf("No bus with name %s\n", realbusname);
+ free(bus);
+ free(pmdio);
+ return -1;
+ }
+
+ pmdio->muxval = muxval;
+ bus->priv = pmdio;
+
+ return mdio_register(bus);
+}
+
+void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
+ enum fm_port port, int offset)
+{
+ int phy;
+ char alias[20];
+ struct fixed_link f_link;
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 srds_s1 = in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+
+ srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+ if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
+ phy = fm_info_get_phy_address(port);
+ switch (port) {
+ case FM1_DTSEC1:
+ case FM1_DTSEC2:
+ case FM1_DTSEC9:
+ case FM1_DTSEC10:
+ sprintf(alias, "phy_sgmii_s3_%x", phy);
+ fdt_set_phy_handle(fdt, compat, addr, alias);
+ fdt_status_okay_by_alias(fdt, "emi1_slot3");
+ break;
+ case FM1_DTSEC5:
+ case FM1_DTSEC6:
+ if (mdio_mux[port] == EMI1_SLOT1) {
+ sprintf(alias, "phy_sgmii_s1_%x", phy);
+ fdt_set_phy_handle(fdt, compat, addr, alias);
+ fdt_status_okay_by_alias(fdt, "emi1_slot1");
+ } else if (mdio_mux[port] == EMI1_SLOT2) {
+ sprintf(alias, "phy_sgmii_s2_%x", phy);
+ fdt_set_phy_handle(fdt, compat, addr, alias);
+ fdt_status_okay_by_alias(fdt, "emi1_slot2");
+ }
+ break;
+ default:
+ break;
+ }
+
+ } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) {
+ switch (srds_s1) {
+ case 0x66: /* XFI interface */
+ case 0x6b:
+ case 0x6c:
+ case 0x6d:
+ case 0x71:
+ f_link.phy_id = port;
+ f_link.duplex = 1;
+ f_link.link_speed = 10000;
+ f_link.pause = 0;
+ f_link.asym_pause = 0;
+ /* no PHY for XFI */
+ fdt_delprop(fdt, offset, "phy-handle");
+ fdt_setprop(fdt, offset, "fixed-link", &f_link,
+ sizeof(f_link));
+ break;
+ default:
+ break;
+ }
+ }
+}
+
+void fdt_fixup_board_enet(void *fdt)
+{
+ return;
+}
+
+/*
+ * This function reads RCW to check if Serdes1{E,F,G,H} is configured
+ * as slot 1/2/3 and update the lane_to_slot[] array accordingly
+ */
+static void initialize_lane_to_slot(void)
+{
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 srds_s1 = in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+
+ srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+ switch (srds_s1) {
+ case 0x51:
+ case 0x5f:
+ case 0x65:
+ case 0x6b:
+ case 0x71:
+ lane_to_slot[5] = 2;
+ lane_to_slot[6] = 2;
+ lane_to_slot[7] = 2;
+ break;
+ case 0xa6:
+ case 0x8e:
+ case 0x8f:
+ case 0x82:
+ case 0x83:
+ case 0xd3:
+ case 0xd9:
+ case 0xcb:
+ lane_to_slot[6] = 2;
+ lane_to_slot[7] = 2;
+ break;
+ case 0xda:
+ lane_to_slot[4] = 3;
+ lane_to_slot[5] = 3;
+ lane_to_slot[6] = 3;
+ lane_to_slot[7] = 3;
+ break;
+ default:
+ break;
+ }
+}
+
+int board_eth_init(bd_t *bis)
+{
+#if defined(CONFIG_FMAN_ENET)
+ int i, idx, lane, slot, interface;
+ struct memac_mdio_info dtsec_mdio_info;
+ struct memac_mdio_info tgec_mdio_info;
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
+ u32 srds_s1;
+
+ srds_s1 = in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+ srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+ initialize_lane_to_slot();
+
+ /* Initialize the mdio_mux array so we can recognize empty elements */
+ for (i = 0; i < NUM_FM_PORTS; i++)
+ mdio_mux[i] = EMI_NONE;
+
+ dtsec_mdio_info.regs =
+ (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
+
+ dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+ /* Register the 1G MDIO bus */
+ fm_memac_mdio_init(bis, &dtsec_mdio_info);
+
+ tgec_mdio_info.regs =
+ (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
+ tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
+
+ /* Register the 10G MDIO bus */
+ fm_memac_mdio_init(bis, &tgec_mdio_info);
+
+ /* Register the muxing front-ends to the MDIO buses */
+ T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
+ T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
+ T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
+ T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
+ T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
+ T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
+ T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
+ T2080qds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
+
+ /* Set the two on-board RGMII PHY address */
+ fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
+ if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
+ FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII)
+ fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
+ else
+ fm_info_set_phy_address(FM1_DTSEC10, RGMII_PHY2_ADDR);
+
+ switch (srds_s1) {
+ case 0x1c:
+ case 0x95:
+ case 0xa2:
+ case 0x94:
+ /* SGMII in Slot3 */
+ fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
+ /* SGMII in Slot2 */
+ fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
+ break;
+ case 0x51:
+ case 0x5f:
+ case 0x65:
+ /* XAUI/HiGig in Slot3 */
+ fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
+ /* SGMII in Slot2 */
+ fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
+ break;
+ case 0x66:
+ /*
+ * XFI does not need a PHY to work, but to avoid U-boot use
+ * default PHY address which is zero to a MAC when it found
+ * a MAC has no PHY address, we give a PHY address to XFI
+ * MAC, and should not use a real XAUI PHY address, since
+ * MDIO can access it successfully, and then MDIO thinks
+ * the XAUI card is used for the XFI MAC, which will cause
+ * error.
+ */
+ fm_info_set_phy_address(FM1_10GEC1, 4);
+ fm_info_set_phy_address(FM1_10GEC2, 5);
+ fm_info_set_phy_address(FM1_10GEC3, 6);
+ fm_info_set_phy_address(FM1_10GEC4, 7);
+ break;
+ case 0x6b:
+ fm_info_set_phy_address(FM1_10GEC1, 4);
+ fm_info_set_phy_address(FM1_10GEC2, 5);
+ fm_info_set_phy_address(FM1_10GEC3, 6);
+ fm_info_set_phy_address(FM1_10GEC4, 7);
+ /* SGMII in Slot2 */
+ fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
+ break;
+ case 0x6c:
+ case 0x6d:
+ /* SGMII in Slot3 */
+ fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR);
+ break;
+ case 0x71:
+ /* SGMII in Slot3 */
+ fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
+ /* SGMII in Slot2 */
+ fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
+ break;
+ case 0xa6:
+ case 0x8e:
+ case 0x8f:
+ case 0x82:
+ case 0x83:
+ /* SGMII in Slot3 */
+ fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
+ /* SGMII in Slot2 */
+ fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
+ break;
+ case 0xa4:
+ case 0x96:
+ case 0x8a:
+ /* SGMII in Slot3 */
+ fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
+ break;
+ case 0xd9:
+ case 0xd3:
+ case 0xcb:
+ /* SGMII in Slot3 */
+ fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
+ /* SGMII in Slot2 */
+ fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
+ break;
+ default:
+ puts("Invalid SerDes1 protocol for T2080QDS\n");
+ break;
+ }
+
+ for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+ idx = i - FM1_DTSEC1;
+ interface = fm_info_get_enet_if(i);
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ lane = serdes_get_first_lane(FSL_SRDS_1,
+ SGMII_FM1_DTSEC1 + idx);
+ if (lane < 0)
+ break;
+ slot = lane_to_slot[lane];
+ debug("FM1@DTSEC%u expects SGMII in slot %u\n",
+ idx + 1, slot);
+ if (QIXIS_READ(present2) & (1 << (slot - 1)))
+ fm_disable_port(i);
+
+ switch (slot) {
+ case 1:
+ mdio_mux[i] = EMI1_SLOT1;
+ fm_info_set_mdio(i, mii_dev_for_muxval(
+ mdio_mux[i]));
+ break;
+ case 2:
+ mdio_mux[i] = EMI1_SLOT2;
+ fm_info_set_mdio(i, mii_dev_for_muxval(
+ mdio_mux[i]));
+ break;
+ };
+ break;
+ case PHY_INTERFACE_MODE_RGMII:
+ if (i == FM1_DTSEC3)
+ mdio_mux[i] = EMI1_RGMII1;
+ else if (i == FM1_DTSEC4 || FM1_DTSEC10)
+ mdio_mux[i] = EMI1_RGMII2;
+ fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
+ break;
+ default:
+ break;
+ }
+ }
+
+ for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
+ idx = i - FM1_10GEC1;
+ switch (fm_info_get_enet_if(i)) {
+ case PHY_INTERFACE_MODE_XGMII:
+ if (srds_s1 == 0x51) {
+ lane = serdes_get_first_lane(FSL_SRDS_1,
+ XAUI_FM1_MAC9 + idx);
+ } else if ((srds_s1 == 0x5f) || (srds_s1 == 0x65)) {
+ lane = serdes_get_first_lane(FSL_SRDS_1,
+ HIGIG_FM1_MAC9 + idx);
+ } else {
+ if (i == FM1_10GEC1 || i == FM1_10GEC2)
+ lane = serdes_get_first_lane(FSL_SRDS_1,
+ XFI_FM1_MAC9 + idx);
+ else
+ lane = serdes_get_first_lane(FSL_SRDS_1,
+ XFI_FM1_MAC1 + idx);
+ }
+
+ if (lane < 0)
+ break;
+ mdio_mux[i] = EMI2;
+ fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
+
+ if ((srds_s1 == 0x66) || (srds_s1 == 0x6b) ||
+ (srds_s1 == 0x6c) || (srds_s1 == 0x6d) ||
+ (srds_s1 == 0x71)) {
+ /* As XFI is in cage intead of a slot, so
+ * ensure doesn't disable the corresponding port
+ */
+ break;
+ }
+
+ slot = lane_to_slot[lane];
+ if (QIXIS_READ(present2) & (1 << (slot - 1)))
+ fm_disable_port(i);
+ break;
+ default:
+ break;
+ }
+ }
+
+ cpu_eth_init(bis);
+#endif /* CONFIG_FMAN_ENET */
+
+ return pci_eth_init(bis);
+}
diff --git a/board/freescale/t2080qds/law.c b/board/freescale/t2080qds/law.c
new file mode 100644
index 0000000..74e2a53
--- /dev/null
+++ b/board/freescale/t2080qds/law.c
@@ -0,0 +1,34 @@
+/*
+ * Copyright 2008-2012 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+ SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+ SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+ SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
+#endif
+#ifdef QIXIS_BASE_PHYS
+ SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+ /* Limit DCSR to 32M to access NPC Trace Buffer */
+ SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE_PHYS
+ SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/t2080qds/pci.c b/board/freescale/t2080qds/pci.c
new file mode 100644
index 0000000..84a89da
--- /dev/null
+++ b/board/freescale/t2080qds/pci.c
@@ -0,0 +1,23 @@
+/*
+ * Copyright 2007-2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/fsl_pci.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/fsl_serdes.h>
+
+void pci_init_board(void)
+{
+ fsl_pcie_init_board(0);
+}
+
+void pci_of_setup(void *blob, bd_t *bd)
+{
+ FT_FSL_PCI_SETUP;
+}
diff --git a/board/freescale/t2080qds/t2080_pbi.cfg b/board/freescale/t2080qds/t2080_pbi.cfg
new file mode 100644
index 0000000..e200d92
--- /dev/null
+++ b/board/freescale/t2080qds/t2080_pbi.cfg
@@ -0,0 +1,41 @@
+#
+# Copyright 2013 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Refer doc/README.pblimage for more details about how-to configure
+# and create PBL boot image
+#
+
+#PBI commands
+#Initialize CPC1
+09010000 00200400
+09138000 00000000
+091380c0 00000100
+#512KB SRAM
+09010100 00000000
+09010104 fff80009
+09010f00 08000000
+#enable CPC1
+09010000 80000000
+#Configure LAW for CPC1
+09000d00 00000000
+09000d04 fff80000
+09000d08 81000012
+#Initialize eSPI controller, default configuration is slow for eSPI to
+#load data, this configuration comes from u-boot eSPI driver.
+09110000 80000403
+09110020 2d170008
+09110024 00100008
+09110028 00100008
+0911002c 00100008
+#Errata for slowing down the MDC clock to make it <= 2.5 MHZ
+094fc030 00008148
+094fd030 00008148
+#Configure alternate space
+09000010 00000000
+09000014 ff000000
+09000018 81000000
+#Flush PBL data
+09138000 00000000
+091380c0 00000000
diff --git a/board/freescale/t2080qds/t2080_rcw.cfg b/board/freescale/t2080qds/t2080_rcw.cfg
new file mode 100644
index 0000000..c2ad0fd
--- /dev/null
+++ b/board/freescale/t2080qds/t2080_rcw.cfg
@@ -0,0 +1,8 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+#SerDes Protocol: 0x66_0x16
+#Core/DDR: 1533Mhz/2133MT/s
+12100017 15000000 00000000 00000000
+66160002 00008400 e8104000 c1000000
+00000000 00000000 00000000 000307fc
+00000000 00000000 00000000 00000004
diff --git a/board/freescale/t2080qds/t2080qds.c b/board/freescale/t2080qds/t2080qds.c
new file mode 100644
index 0000000..cac32fe
--- /dev/null
+++ b/board/freescale/t2080qds/t2080qds.c
@@ -0,0 +1,324 @@
+/*
+ * Copyright 2009-2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+#include <netdev.h>
+#include <linux/compiler.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <fm_eth.h>
+
+#include "../common/qixis.h"
+#include "../common/vsc3316_3308.h"
+#include "t2080qds.h"
+#include "t2080qds_qixis.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ char buf[64];
+ u8 sw;
+ struct cpu_type *cpu = gd->arch.cpu;
+ static const char *freq[4] = {
+ "100.00MHZ(from 8T49N222A)", "125.00MHz",
+ "156.25MHZ", "100.00MHz"
+ };
+
+ printf("Board: %sQDS, ", cpu->name);
+ sw = QIXIS_READ(arch);
+ printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4);
+ printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1);
+
+ sw = QIXIS_READ(brdcfg[0]);
+ sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
+
+ if (sw < 0x8)
+ printf("vBank%d\n", sw);
+ else if (sw == 0x8)
+ puts("Promjet\n");
+ else if (sw == 0x9)
+ puts("NAND\n");
+ else
+ printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
+
+ printf("FPGA: v%d (%s), build %d", (int)QIXIS_READ(scver),
+ qixis_read_tag(buf), (int)qixis_read_minor());
+ /* the timestamp string contains "\n" at the end */
+ printf(" on %s", qixis_read_time(buf));
+
+ puts("SERDES Reference Clocks:\n");
+ sw = QIXIS_READ(brdcfg[2]);
+ printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[sw >> 6],
+ freq[(sw >> 4) & 0x3]);
+ printf("SD2_CLK1=%s, SD2_CLK2=%s\n", freq[(sw & 0xf) >> 2],
+ freq[sw & 0x3]);
+
+ return 0;
+}
+
+int select_i2c_ch_pca9547(u8 ch)
+{
+ int ret;
+
+ ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+ if (ret) {
+ puts("PCA: failed to select proper channel\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+int brd_mux_lane_to_slot(void)
+{
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 srds_prtcl_s1, srds_prtcl_s2;
+
+ srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+ srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+ srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
+ srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
+
+ switch (srds_prtcl_s1) {
+ case 0:
+ /* SerDes1 is not enabled */
+ break;
+ case 0x1c:
+ case 0x95:
+ case 0xa2:
+ case 0x94:
+ /* SD1(A:D) => SLOT3 SGMII
+ * SD1(G:H) => SLOT1 SGMII
+ */
+ QIXIS_WRITE(brdcfg[12], 0x58);
+ break;
+ case 0x51:
+ /* SD1(A:D) => SLOT3 XAUI
+ * SD1(E) => SLOT1 PCIe4
+ * SD1(F:H) => SLOT2 SGMII
+ */
+ QIXIS_WRITE(brdcfg[12], 0x15);
+ break;
+ case 0x66:
+ case 0x67:
+ /* SD1(A:D) => XFI cage
+ * SD1(E:H) => SLOT1 PCIe4
+ */
+ QIXIS_WRITE(brdcfg[12], 0xfe);
+ break;
+ case 0x6b:
+ /* SD1(A:D) => XFI cage
+ * SD1(E) => SLOT1 PCIe4
+ * SD1(F:H) => SLOT2 SGMII
+ */
+ QIXIS_WRITE(brdcfg[12], 0xf1);
+ break;
+ case 0x6c:
+ case 0x6d:
+ /* SD1(A:B) => XFI cage
+ * SD1(C:D) => SLOT3 SGMII
+ * SD1(E:H) => SLOT1 PCIe4
+ */
+ QIXIS_WRITE(brdcfg[12], 0xda);
+ break;
+ default:
+ printf("WARNING: unsupported for SerDes1 Protocol %d\n",
+ srds_prtcl_s1);
+ return -1;
+ }
+
+ switch (srds_prtcl_s2) {
+ case 0:
+ /* SerDes2 is not enabled */
+ break;
+ case 0x01:
+ case 0x02:
+ /* SD2(A:H) => SLOT4 PCIe1 */
+ QIXIS_WRITE(brdcfg[13], 0x20);
+ break;
+ case 0x15:
+ case 0x16:
+ /*
+ * SD2(A:D) => SLOT4 PCIe1
+ * SD2(E:F) => SLOT5 PCIe2
+ * SD2(G:H) => SATA1,SATA2
+ */
+ QIXIS_WRITE(brdcfg[13], 0xb0);
+ break;
+ case 0x18:
+ /*
+ * SD2(A:D) => SLOT4 PCIe1
+ * SD2(E:F) => SLOT5 Aurora
+ * SD2(G:H) => SATA1,SATA2
+ */
+ QIXIS_WRITE(brdcfg[13], 0x70);
+ break;
+ case 0x1f:
+ /*
+ * SD2(A:D) => SLOT4 PCIe1
+ * SD2(E:H) => SLOT5 PCIe2
+ */
+ QIXIS_WRITE(brdcfg[13], 0xa0);
+ break;
+ case 0x29:
+ case 0x2d:
+ case 0x2e:
+ /*
+ * SD2(A:D) => SLOT4 SRIO2
+ * SD2(E:H) => SLOT5 SRIO1
+ */
+ QIXIS_WRITE(brdcfg[13], 0x50);
+ break;
+ default:
+ printf("WARNING: unsupported for SerDes2 Protocol %d\n",
+ srds_prtcl_s2);
+ return -1;
+ }
+ return 0;
+}
+
+int board_early_init_r(void)
+{
+ const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+ const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+ /*
+ * Remap Boot flash + PROMJET region to caching-inhibited
+ * so that flash can be erased properly.
+ */
+
+ /* Flush d-cache and invalidate i-cache of any FLASH data */
+ flush_dcache();
+ invalidate_icache();
+
+ /* invalidate existing TLB entry for flash + promjet */
+ disable_tlb(flash_esel);
+
+ set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, flash_esel, BOOKE_PAGESZ_256M, 1);
+
+ set_liodns();
+#ifdef CONFIG_SYS_DPAA_QBMAN
+ setup_portals();
+#endif
+
+ /* Disable remote I2C connection to qixis fpga */
+ QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE);
+
+ brd_mux_lane_to_slot();
+ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+
+ return 0;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+ u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
+#ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
+ /* use accurate clock measurement */
+ int freq = QIXIS_READ(clk_freq[0]) << 8 | QIXIS_READ(clk_freq[1]);
+ int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
+ u32 val;
+
+ val = freq * base;
+ if (val) {
+ debug("SYS Clock measurement is: %d\n", val);
+ return val;
+ } else {
+ printf("Warning: SYS clock measurement is invalid, ");
+ printf("using value from brdcfg1.\n");
+ }
+#endif
+
+ switch (sysclk_conf & 0x0F) {
+ case QIXIS_SYSCLK_83:
+ return 83333333;
+ case QIXIS_SYSCLK_100:
+ return 100000000;
+ case QIXIS_SYSCLK_125:
+ return 125000000;
+ case QIXIS_SYSCLK_133:
+ return 133333333;
+ case QIXIS_SYSCLK_150:
+ return 150000000;
+ case QIXIS_SYSCLK_160:
+ return 160000000;
+ case QIXIS_SYSCLK_166:
+ return 166666666;
+ }
+ return 66666666;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+ u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
+#ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
+ /* use accurate clock measurement */
+ int freq = QIXIS_READ(clk_freq[2]) << 8 | QIXIS_READ(clk_freq[3]);
+ int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
+ u32 val;
+
+ val = freq * base;
+ if (val) {
+ debug("DDR Clock measurement is: %d\n", val);
+ return val;
+ } else {
+ printf("Warning: DDR clock measurement is invalid, ");
+ printf("using value from brdcfg1.\n");
+ }
+#endif
+
+ switch ((ddrclk_conf & 0x30) >> 4) {
+ case QIXIS_DDRCLK_100:
+ return 100000000;
+ case QIXIS_DDRCLK_125:
+ return 125000000;
+ case QIXIS_DDRCLK_133:
+ return 133333333;
+ }
+ return 66666666;
+}
+
+int misc_init_r(void)
+{
+ return 0;
+}
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ phys_addr_t base;
+ phys_size_t size;
+
+ ft_cpu_setup(blob, bd);
+
+ base = getenv_bootm_low();
+ size = getenv_bootm_size();
+
+ fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#ifdef CONFIG_PCI
+ pci_of_setup(blob, bd);
+#endif
+
+ fdt_fixup_liodn(blob);
+ fdt_fixup_dr_usb(blob, bd);
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+ fdt_fixup_fman_ethernet(blob);
+ fdt_fixup_board_enet(blob);
+#endif
+}
diff --git a/board/freescale/t2080qds/t2080qds.h b/board/freescale/t2080qds/t2080qds.h
new file mode 100644
index 0000000..39fcef2
--- /dev/null
+++ b/board/freescale/t2080qds/t2080qds.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright 2011-2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CORENET_DS_H__
+#define __CORENET_DS_H__
+
+void fdt_fixup_board_enet(void *blob);
+void pci_of_setup(void *blob, bd_t *bd);
+
+#endif
diff --git a/board/freescale/t2080qds/t2080qds_qixis.h b/board/freescale/t2080qds/t2080qds_qixis.h
new file mode 100644
index 0000000..fc83da7
--- /dev/null
+++ b/board/freescale/t2080qds/t2080qds_qixis.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __T2080QDS_QIXIS_H__
+#define __T2080QDS_QIXIS_H__
+
+/* Definitions of QIXIS Registers for T2080QDS */
+
+#define QIXIS_SRDS1CLK_122 0x5a
+#define QIXIS_SRDS1CLK_125 0x5e
+
+
+/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */
+#define BRDCFG4_EMISEL_MASK 0xE0
+#define BRDCFG4_EMISEL_SHIFT 5
+
+/* SYSCLK */
+#define QIXIS_SYSCLK_66 0x0
+#define QIXIS_SYSCLK_83 0x1
+#define QIXIS_SYSCLK_100 0x2
+#define QIXIS_SYSCLK_125 0x3
+#define QIXIS_SYSCLK_133 0x4
+#define QIXIS_SYSCLK_150 0x5
+#define QIXIS_SYSCLK_160 0x6
+#define QIXIS_SYSCLK_166 0x7
+
+/* DDRCLK */
+#define QIXIS_DDRCLK_66 0x0
+#define QIXIS_DDRCLK_100 0x1
+#define QIXIS_DDRCLK_125 0x2
+#define QIXIS_DDRCLK_133 0x3
+
+#define BRDCFG5_IRE 0x20 /* i2c Remote i2c1 enable */
+
+#define BRDCFG12_SD3EN_MASK 0x20
+#define BRDCFG12_SD3MX_MASK 0x08
+#define BRDCFG12_SD3MX_SLOT5 0x08
+#define BRDCFG12_SD3MX_SLOT6 0x00
+#define BRDCFG12_SD4EN_MASK 0x04
+#define BRDCFG12_SD4MX_MASK 0x03
+#define BRDCFG12_SD4MX_SLOT7 0x02
+#define BRDCFG12_SD4MX_SLOT8 0x01
+#define BRDCFG12_SD4MX_AURO_SATA 0x00
+#endif
diff --git a/board/freescale/t2080qds/tlb.c b/board/freescale/t2080qds/tlb.c
new file mode 100644
index 0000000..62cd110
--- /dev/null
+++ b/board/freescale/t2080qds/tlb.c
@@ -0,0 +1,146 @@
+/*
+ * Copyright 2008-2013 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /* TLB 1 */
+ /* *I*** - Covers boot page */
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
+ /*
+ * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
+ * SRAM is at 0xfff00000, it covered the 0xfffff000.
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_1M, 1),
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+ /*
+ * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
+ * space is at 0xfff00000, it covered the 0xfffff000.
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
+ CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_1M, 1),
+#else
+ SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_4K, 1),
+#endif
+
+ /* *I*G* - CCSRBAR */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_16M, 1),
+
+ /* *I*G* - Flash, localbus */
+ /* This will be changed to *I*G* after relocation to RAM. */
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_256M, 1),
+
+ /* *I*G* - PCIe 1, 0x80000000 */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_512M, 1),
+
+ /* *I*G* - PCIe 2, 0xa0000000 */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_VIRT, CONFIG_SYS_PCIE2_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_256M, 1),
+
+ /* *I*G* - PCIe 3, 0xb0000000 */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_256M, 1),
+
+
+ /* *I*G* - PCIe 4, 0xc0000000 */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE4_MEM_VIRT, CONFIG_SYS_PCIE4_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 6, BOOKE_PAGESZ_256M, 1),
+
+ /* *I*G* - PCI I/O */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 7, BOOKE_PAGESZ_256K, 1),
+
+ /* Bman/Qman */
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 9, BOOKE_PAGESZ_16M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
+ CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 10, BOOKE_PAGESZ_16M, 1),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 11, BOOKE_PAGESZ_16M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
+ CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 12, BOOKE_PAGESZ_16M, 1),
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 13, BOOKE_PAGESZ_32M, 1),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE
+ /*
+ * *I*G - NAND
+ * entry 14 and 15 has been used hard coded, they will be disabled
+ * in cpu_init_f, so we use entry 16 for nand.
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 16, BOOKE_PAGESZ_64K, 1),
+#endif
+#ifdef QIXIS_BASE_PHYS
+ SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 17, BOOKE_PAGESZ_4K, 1),
+#endif
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+ /*
+ * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for
+ * fetching ucode and ENV from master
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
+ CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
+ 0, 18, BOOKE_PAGESZ_1M, 1),
+#endif
+
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/t4qds/ddr.c b/board/freescale/t4qds/ddr.c
index d70c310..7586cc3 100644
--- a/board/freescale/t4qds/ddr.c
+++ b/board/freescale/t4qds/ddr.c
@@ -10,8 +10,8 @@
#include <i2c.h>
#include <hwconfig.h>
#include <asm/mmu.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
#include <asm/fsl_law.h>
#include "ddr.h"
diff --git a/board/freescale/t4qds/eth.c b/board/freescale/t4qds/eth.c
index b5f488b..24cf907 100644
--- a/board/freescale/t4qds/eth.c
+++ b/board/freescale/t4qds/eth.c
@@ -12,7 +12,7 @@
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_law.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
diff --git a/board/gaisler/gr_cpci_ax2000/config.mk b/board/gaisler/gr_cpci_ax2000/config.mk
index e9c6028..309c879 100644
--- a/board/gaisler/gr_cpci_ax2000/config.mk
+++ b/board/gaisler/gr_cpci_ax2000/config.mk
@@ -18,5 +18,4 @@
# U-BOOT IN SDRAM
#CONFIG_SYS_TEXT_BASE = 0x60000000
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE) \
- -I$(TOPDIR)/board
+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board
diff --git a/board/gaisler/gr_ep2s60/config.mk b/board/gaisler/gr_ep2s60/config.mk
index 6c31a17..d57efae 100644
--- a/board/gaisler/gr_ep2s60/config.mk
+++ b/board/gaisler/gr_ep2s60/config.mk
@@ -16,5 +16,4 @@
# U-BOOT IN SDRAM
#CONFIG_SYS_TEXT_BASE = 0x40000000
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE) \
- -I$(TOPDIR)/board
+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board
diff --git a/board/gaisler/gr_xc3s_1500/config.mk b/board/gaisler/gr_xc3s_1500/config.mk
index 3b59cca..e87320b 100644
--- a/board/gaisler/gr_xc3s_1500/config.mk
+++ b/board/gaisler/gr_xc3s_1500/config.mk
@@ -15,5 +15,4 @@
# U-BOOT IN RAM
#CONFIG_SYS_TEXT_BASE = 0x40000000
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE) \
- -I$(TOPDIR)/board
+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board
diff --git a/board/gaisler/grsim/config.mk b/board/gaisler/grsim/config.mk
index d98ed54..df26f82 100644
--- a/board/gaisler/grsim/config.mk
+++ b/board/gaisler/grsim/config.mk
@@ -15,5 +15,4 @@
# U-BOOT IN RAM
#CONFIG_SYS_TEXT_BASE = 0x40000000
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE) \
- -I$(TOPDIR)/board
+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board
diff --git a/board/gaisler/grsim_leon2/config.mk b/board/gaisler/grsim_leon2/config.mk
index 59e4e31..99f9a68 100644
--- a/board/gaisler/grsim_leon2/config.mk
+++ b/board/gaisler/grsim_leon2/config.mk
@@ -15,5 +15,4 @@
# RUN U-BOOT FROM RAM
#CONFIG_SYS_TEXT_BASE = 0x40000000
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE) \
- -I$(TOPDIR)/board
+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board
diff --git a/board/gdsys/p1022/controlcenterd.c b/board/gdsys/p1022/controlcenterd.c
index 81c22bc..8ccd9ce 100644
--- a/board/gdsys/p1022/controlcenterd.c
+++ b/board/gdsys/p1022/controlcenterd.c
@@ -29,7 +29,7 @@
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <asm/io.h>
#include <libfdt.h>
diff --git a/board/gdsys/p1022/ddr.c b/board/gdsys/p1022/ddr.c
index 4a652de..7596736 100644
--- a/board/gdsys/p1022/ddr.c
+++ b/board/gdsys/p1022/ddr.c
@@ -12,8 +12,8 @@
#include <common.h>
#include <i2c.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm,
unsigned int ctrl_num)
diff --git a/board/genietv/u-boot.lds b/board/genietv/u-boot.lds
index e217f06..70ab702 100644
--- a/board/genietv/u-boot.lds
+++ b/board/genietv/u-boot.lds
@@ -18,11 +18,11 @@
arch/powerpc/cpu/mpc8xx/start.o (.text*)
arch/powerpc/cpu/mpc8xx/traps.o (.text*)
- lib/libgeneric.o (.text*)
- net/libnet.o (.text*)
- arch/powerpc/cpu/mpc8xx/libmpc8xx.o (.text*)
- board/genietv/libgenietv.o (.text*)
- arch/powerpc/lib/libpowerpc.o (.text*)
+ lib/built-in.o (.text*)
+ net/built-in.o (.text*)
+ arch/powerpc/cpu/mpc8xx/built-in.o (.text*)
+ board/genietv/built-in.o (.text*)
+ arch/powerpc/lib/built-in.o (.text*)
*(.text.do_load_serial*)
*(.text.do_mem_*)
*(.text.do_bootm*)
diff --git a/board/h2200/Makefile b/board/h2200/Makefile
index b654a96..d4fa153 100644
--- a/board/h2200/Makefile
+++ b/board/h2200/Makefile
@@ -10,8 +10,5 @@
extra-y := h2200-header.bin
-$(obj)h2200-header.o: h2200-header.S
- $(CC) $(CFLAGS) -c -o $@ $<
-
$(obj)h2200-header.bin: $(obj)h2200-header.o
$(OBJCOPY) -O binary $< $@
diff --git a/board/hermes/u-boot.lds b/board/hermes/u-boot.lds
index 9419f83..0309860 100644
--- a/board/hermes/u-boot.lds
+++ b/board/hermes/u-boot.lds
@@ -17,7 +17,7 @@
/* the sector layout of our flash chips! XXX FIXME XXX */
arch/powerpc/cpu/mpc8xx/start.o (.text*)
arch/powerpc/cpu/mpc8xx/traps.o (.text*)
- board/hermes/libhermes.o (.text*)
+ board/hermes/built-in.o (.text*)
. = env_offset;
common/env_embedded.o (.text*)
diff --git a/board/qemu-malta/Makefile b/board/imgtec/malta/Makefile
similarity index 80%
rename from board/qemu-malta/Makefile
rename to board/imgtec/malta/Makefile
index 5d727f6..19dd3a3 100644
--- a/board/qemu-malta/Makefile
+++ b/board/imgtec/malta/Makefile
@@ -5,5 +5,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y = qemu-malta.o
+obj-y = malta.o
obj-y += lowlevel_init.o
+obj-y += superio.o
diff --git a/board/imgtec/malta/flash-malta-boot.tcl b/board/imgtec/malta/flash-malta-boot.tcl
new file mode 100644
index 0000000..0eedf07
--- /dev/null
+++ b/board/imgtec/malta/flash-malta-boot.tcl
@@ -0,0 +1,40 @@
+#
+# Copyright (C) 2013 Imagination Technologies
+#
+# Programs a MIPS Malta boot flash with a flat binary image.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+proc flash-boot { binfile } {
+ puts "flash monitor binary $binfile"
+ config Coherent on
+ config CoherencyDuringLoad on
+
+ if {[endian]=="big"} {
+ puts "CPU in BE mode"
+ flash device sharp_16x32_be;
+ } else {
+ puts "CPU in LE mode"
+ flash device sharp_16x32;
+ }
+
+ flash clear all;
+ flash set 0xBE000000..0xBE0FFFFF
+ flash erase sector 0xbe000000;
+ flash erase sector 0xbe020000;
+ flash erase sector 0xbe040000;
+ flash erase sector 0xbe060000;
+ flash erase sector 0xbe080000;
+ flash erase sector 0xbe0a0000;
+ flash erase sector 0xbe0c0000;
+ flash erase sector 0xbe0e0000;
+ puts "finished erasing boot flash";
+
+ puts "programming flash, please be patient"
+ load bin 0xbe000000 $binfile size4
+
+ flash clear all
+ config CoherencyDuringLoad off
+ puts "finished programming boot flash";
+}
diff --git a/board/imgtec/malta/lowlevel_init.S b/board/imgtec/malta/lowlevel_init.S
new file mode 100644
index 0000000..ae09c27
--- /dev/null
+++ b/board/imgtec/malta/lowlevel_init.S
@@ -0,0 +1,238 @@
+/*
+ * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <config.h>
+#include <gt64120.h>
+#include <msc01.h>
+#include <pci.h>
+
+#include <asm/addrspace.h>
+#include <asm/regdef.h>
+#include <asm/malta.h>
+#include <asm/mipsregs.h>
+
+#ifdef CONFIG_SYS_BIG_ENDIAN
+#define CPU_TO_GT32(_x) ((_x))
+#else
+#define CPU_TO_GT32(_x) ( \
+ (((_x) & 0xff) << 24) | (((_x) & 0xff00) << 8) | \
+ (((_x) & 0xff0000) >> 8) | (((_x) & 0xff000000) >> 24))
+#endif
+
+ .text
+ .set noreorder
+ .set mips32
+
+ .globl lowlevel_init
+lowlevel_init:
+ /* disable any L2 cache for now */
+ sync
+ mfc0 t0, CP0_CONFIG, 2
+ ori t0, t0, 0x1 << 12
+ mtc0 t0, CP0_CONFIG, 2
+
+ /* detect the core card */
+ li t0, KSEG1ADDR(MALTA_REVISION)
+ lw t0, 0(t0)
+ srl t0, t0, MALTA_REVISION_CORID_SHF
+ andi t0, t0, (MALTA_REVISION_CORID_MSK >> \
+ MALTA_REVISION_CORID_SHF)
+
+ /* core cards using the gt64120 system controller */
+ li t1, MALTA_REVISION_CORID_CORE_LV
+ beq t0, t1, _gt64120
+
+ /* core cards using the MSC01 system controller */
+ li t1, MALTA_REVISION_CORID_CORE_FPGA6
+ beq t0, t1, _msc01
+ nop
+
+ /* unknown system controller */
+ b .
+ nop
+
+ /*
+ * Load BAR registers of GT64120 as done by YAMON
+ *
+ * based on a patch sent by Antony Pavlov <antonynpavlov@gmail.com>
+ * to the barebox mailing list.
+ * The subject of the original patch:
+ * 'MIPS: qemu-malta: add YAMON-style GT64120 memory map'
+ * URL:
+ * http://www.mail-archive.com/barebox@lists.infradead.org/msg06128.html
+ *
+ * based on write_bootloader() in qemu.git/hw/mips_malta.c
+ * see GT64120 manual and qemu.git/hw/gt64xxx.c for details
+ */
+_gt64120:
+ /* move GT64120 registers from 0x14000000 to 0x1be00000 */
+ li t1, KSEG1ADDR(GT_DEF_BASE)
+ li t0, CPU_TO_GT32(0xdf000000)
+ sw t0, GT_ISD_OFS(t1)
+
+ /* setup MEM-to-PCI0 mapping */
+ li t1, KSEG1ADDR(MALTA_GT_BASE)
+
+ /* setup PCI0 io window to 0x18000000-0x181fffff */
+ li t0, CPU_TO_GT32(0xc0000000)
+ sw t0, GT_PCI0IOLD_OFS(t1)
+ li t0, CPU_TO_GT32(0x40000000)
+ sw t0, GT_PCI0IOHD_OFS(t1)
+
+ /* setup PCI0 mem windows */
+ li t0, CPU_TO_GT32(0x80000000)
+ sw t0, GT_PCI0M0LD_OFS(t1)
+ li t0, CPU_TO_GT32(0x3f000000)
+ sw t0, GT_PCI0M0HD_OFS(t1)
+
+ li t0, CPU_TO_GT32(0xc1000000)
+ sw t0, GT_PCI0M1LD_OFS(t1)
+ li t0, CPU_TO_GT32(0x5e000000)
+ sw t0, GT_PCI0M1HD_OFS(t1)
+
+ jr ra
+ nop
+
+ /*
+ *
+ */
+_msc01:
+ /* setup peripheral bus controller clock divide */
+ li t0, KSEG1ADDR(MALTA_MSC01_PBC_BASE)
+ li t1, 0x1 << MSC01_PBC_CLKCFG_SHF
+ sw t1, MSC01_PBC_CLKCFG_OFS(t0)
+
+ /* tweak peripheral bus controller timings */
+ li t1, (0x1 << MSC01_PBC_CS0TIM_CDT_SHF) | \
+ (0x1 << MSC01_PBC_CS0TIM_CAT_SHF)
+ sw t1, MSC01_PBC_CS0TIM_OFS(t0)
+ li t1, (0x0 << MSC01_PBC_CS0RW_RDT_SHF) | \
+ (0x2 << MSC01_PBC_CS0RW_RAT_SHF) | \
+ (0x0 << MSC01_PBC_CS0RW_WDT_SHF) | \
+ (0x2 << MSC01_PBC_CS0RW_WAT_SHF)
+ sw t1, MSC01_PBC_CS0RW_OFS(t0)
+ lw t1, MSC01_PBC_CS0CFG_OFS(t0)
+ li t2, MSC01_PBC_CS0CFG_DTYP_MSK
+ and t1, t2
+ ori t1, (0x0 << MSC01_PBC_CS0CFG_ADM_SHF) | \
+ (0x3 << MSC01_PBC_CS0CFG_WSIDLE_SHF) | \
+ (0x10 << MSC01_PBC_CS0CFG_WS_SHF)
+ sw t1, MSC01_PBC_CS0CFG_OFS(t0)
+
+ /* setup basic address decode */
+ li t0, KSEG1ADDR(MALTA_MSC01_BIU_BASE)
+ li t1, 0x0
+ li t2, -CONFIG_SYS_MEM_SIZE
+ sw t1, MSC01_BIU_MCBAS1L_OFS(t0)
+ sw t2, MSC01_BIU_MCMSK1L_OFS(t0)
+ sw t1, MSC01_BIU_MCBAS2L_OFS(t0)
+ sw t2, MSC01_BIU_MCMSK2L_OFS(t0)
+
+ /* initialise IP1 - unused */
+ li t1, MALTA_MSC01_IP1_BASE
+ li t2, -MALTA_MSC01_IP1_SIZE
+ sw t1, MSC01_BIU_IP1BAS1L_OFS(t0)
+ sw t2, MSC01_BIU_IP1MSK1L_OFS(t0)
+ sw t1, MSC01_BIU_IP1BAS2L_OFS(t0)
+ sw t2, MSC01_BIU_IP1MSK2L_OFS(t0)
+
+ /* initialise IP2 - PCI */
+ li t1, MALTA_MSC01_IP2_BASE1
+ li t2, -MALTA_MSC01_IP2_SIZE1
+ sw t1, MSC01_BIU_IP2BAS1L_OFS(t0)
+ sw t2, MSC01_BIU_IP2MSK1L_OFS(t0)
+ li t1, MALTA_MSC01_IP2_BASE2
+ li t2, -MALTA_MSC01_IP2_SIZE2
+ sw t1, MSC01_BIU_IP2BAS2L_OFS(t0)
+ sw t2, MSC01_BIU_IP2MSK2L_OFS(t0)
+
+ /* initialise IP3 - peripheral bus controller */
+ li t1, MALTA_MSC01_IP3_BASE
+ li t2, -MALTA_MSC01_IP3_SIZE
+ sw t1, MSC01_BIU_IP3BAS1L_OFS(t0)
+ sw t2, MSC01_BIU_IP3MSK1L_OFS(t0)
+ sw t1, MSC01_BIU_IP3BAS2L_OFS(t0)
+ sw t2, MSC01_BIU_IP3MSK2L_OFS(t0)
+
+ /* setup PCI memory */
+ li t0, KSEG1ADDR(MALTA_MSC01_PCI_BASE)
+ li t1, MALTA_MSC01_PCIMEM_BASE
+ li t2, (-MALTA_MSC01_PCIMEM_SIZE) & MSC01_PCI_SC2PMMSKL_MSK_MSK
+ li t3, MALTA_MSC01_PCIMEM_MAP
+ sw t1, MSC01_PCI_SC2PMBASL_OFS(t0)
+ sw t2, MSC01_PCI_SC2PMMSKL_OFS(t0)
+ sw t3, MSC01_PCI_SC2PMMAPL_OFS(t0)
+
+ /* setup PCI I/O */
+ li t1, MALTA_MSC01_PCIIO_BASE
+ li t2, (-MALTA_MSC01_PCIIO_SIZE) & MSC01_PCI_SC2PIOMSKL_MSK_MSK
+ li t3, MALTA_MSC01_PCIIO_MAP
+ sw t1, MSC01_PCI_SC2PIOBASL_OFS(t0)
+ sw t2, MSC01_PCI_SC2PIOMSKL_OFS(t0)
+ sw t3, MSC01_PCI_SC2PIOMAPL_OFS(t0)
+
+ /* setup PCI_BAR0 memory window */
+ li t1, -CONFIG_SYS_MEM_SIZE
+ sw t1, MSC01_PCI_BAR0_OFS(t0)
+
+ /* setup PCI to SysCon/CPU translation */
+ sw t1, MSC01_PCI_P2SCMSKL_OFS(t0)
+ sw zero, MSC01_PCI_P2SCMAPL_OFS(t0)
+
+ /* setup PCI vendor & device IDs */
+ li t1, (PCI_VENDOR_ID_MIPS << MSC01_PCI_HEAD0_VENDORID_SHF) | \
+ (PCI_DEVICE_ID_MIPS_MSC01 << MSC01_PCI_HEAD0_DEVICEID_SHF)
+ sw t1, MSC01_PCI_HEAD0_OFS(t0)
+
+ /* setup PCI subsystem vendor & device IDs */
+ sw t1, MSC01_PCI_HEAD11_OFS(t0)
+
+ /* setup PCI class, revision */
+ li t1, (PCI_CLASS_BRIDGE_HOST << MSC01_PCI_HEAD2_CLASS_SHF) | \
+ (0x1 << MSC01_PCI_HEAD2_REV_SHF)
+ sw t1, MSC01_PCI_HEAD2_OFS(t0)
+
+ /* ensure a sane setup */
+ sw zero, MSC01_PCI_HEAD3_OFS(t0)
+ sw zero, MSC01_PCI_HEAD4_OFS(t0)
+ sw zero, MSC01_PCI_HEAD5_OFS(t0)
+ sw zero, MSC01_PCI_HEAD6_OFS(t0)
+ sw zero, MSC01_PCI_HEAD7_OFS(t0)
+ sw zero, MSC01_PCI_HEAD8_OFS(t0)
+ sw zero, MSC01_PCI_HEAD9_OFS(t0)
+ sw zero, MSC01_PCI_HEAD10_OFS(t0)
+ sw zero, MSC01_PCI_HEAD12_OFS(t0)
+ sw zero, MSC01_PCI_HEAD13_OFS(t0)
+ sw zero, MSC01_PCI_HEAD14_OFS(t0)
+ sw zero, MSC01_PCI_HEAD15_OFS(t0)
+
+ /* setup PCI command register */
+ li t1, (PCI_COMMAND_FAST_BACK | \
+ PCI_COMMAND_SERR | \
+ PCI_COMMAND_PARITY | \
+ PCI_COMMAND_MASTER | \
+ PCI_COMMAND_MEMORY)
+ sw t1, MSC01_PCI_HEAD1_OFS(t0)
+
+ /* setup PCI byte swapping */
+#ifdef CONFIG_SYS_BIG_ENDIAN
+ li t1, (0x1 << MSC01_PCI_SWAP_BAR0_BSWAP_SHF) | \
+ (0x1 << MSC01_PCI_SWAP_IO_BSWAP_SHF)
+ sw t1, MSC01_PCI_SWAP_OFS(t0)
+#else
+ sw zero, MSC01_PCI_SWAP_OFS(t0)
+#endif
+
+ /* enable PCI host configuration cycles */
+ lw t1, MSC01_PCI_CFG_OFS(t0)
+ li t2, MSC01_PCI_CFG_RA_MSK | \
+ MSC01_PCI_CFG_G_MSK | \
+ MSC01_PCI_CFG_EN_MSK
+ or t1, t1, t2
+ sw t1, MSC01_PCI_CFG_OFS(t0)
+
+ jr ra
+ nop
diff --git a/board/imgtec/malta/malta.c b/board/imgtec/malta/malta.c
new file mode 100644
index 0000000..d363e49
--- /dev/null
+++ b/board/imgtec/malta/malta.c
@@ -0,0 +1,220 @@
+/*
+ * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2013 Imagination Technologies
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <pci.h>
+#include <pci_gt64120.h>
+#include <pci_msc01.h>
+#include <rtc.h>
+#include <serial.h>
+
+#include <asm/addrspace.h>
+#include <asm/io.h>
+#include <asm/malta.h>
+
+#include "superio.h"
+
+enum core_card {
+ CORE_UNKNOWN,
+ CORE_LV,
+ CORE_FPGA6,
+};
+
+enum sys_con {
+ SYSCON_UNKNOWN,
+ SYSCON_GT64120,
+ SYSCON_MSC01,
+};
+
+static void malta_lcd_puts(const char *str)
+{
+ int i;
+ void *reg = (void *)CKSEG1ADDR(MALTA_ASCIIPOS0);
+
+ /* print up to 8 characters of the string */
+ for (i = 0; i < min(strlen(str), 8); i++) {
+ __raw_writel(str[i], reg);
+ reg += MALTA_ASCIIPOS1 - MALTA_ASCIIPOS0;
+ }
+
+ /* fill the rest of the display with spaces */
+ for (; i < 8; i++) {
+ __raw_writel(' ', reg);
+ reg += MALTA_ASCIIPOS1 - MALTA_ASCIIPOS0;
+ }
+}
+
+static enum core_card malta_core_card(void)
+{
+ u32 corid, rev;
+
+ rev = __raw_readl(CKSEG1ADDR(MALTA_REVISION));
+ corid = (rev & MALTA_REVISION_CORID_MSK) >> MALTA_REVISION_CORID_SHF;
+
+ switch (corid) {
+ case MALTA_REVISION_CORID_CORE_LV:
+ return CORE_LV;
+
+ case MALTA_REVISION_CORID_CORE_FPGA6:
+ return CORE_FPGA6;
+
+ default:
+ return CORE_UNKNOWN;
+ }
+}
+
+static enum sys_con malta_sys_con(void)
+{
+ switch (malta_core_card()) {
+ case CORE_LV:
+ return SYSCON_GT64120;
+
+ case CORE_FPGA6:
+ return SYSCON_MSC01;
+
+ default:
+ return SYSCON_UNKNOWN;
+ }
+}
+
+phys_size_t initdram(int board_type)
+{
+ return CONFIG_SYS_MEM_SIZE;
+}
+
+int checkboard(void)
+{
+ enum core_card core;
+
+ malta_lcd_puts("U-boot");
+ puts("Board: MIPS Malta");
+
+ core = malta_core_card();
+ switch (core) {
+ case CORE_LV:
+ puts(" CoreLV");
+ break;
+
+ case CORE_FPGA6:
+ puts(" CoreFPGA6");
+ break;
+
+ default:
+ puts(" CoreUnknown");
+ }
+
+ putc('\n');
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
+
+void _machine_restart(void)
+{
+ void __iomem *reset_base;
+
+ reset_base = (void __iomem *)CKSEG1ADDR(MALTA_RESET_BASE);
+ __raw_writel(GORESET, reset_base);
+}
+
+int board_early_init_f(void)
+{
+ void *io_base;
+
+ /* choose correct PCI I/O base */
+ switch (malta_sys_con()) {
+ case SYSCON_GT64120:
+ io_base = (void *)CKSEG1ADDR(MALTA_GT_PCIIO_BASE);
+ break;
+
+ case SYSCON_MSC01:
+ io_base = (void *)CKSEG1ADDR(MALTA_MSC01_PCIIO_BASE);
+ break;
+
+ default:
+ return -1;
+ }
+
+ /* setup FDC37M817 super I/O controller */
+ malta_superio_init(io_base);
+
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ rtc_reset();
+
+ return 0;
+}
+
+struct serial_device *default_serial_console(void)
+{
+ switch (malta_sys_con()) {
+ case SYSCON_GT64120:
+ return &eserial1_device;
+
+ default:
+ case SYSCON_MSC01:
+ return &eserial2_device;
+ }
+}
+
+void pci_init_board(void)
+{
+ pci_dev_t bdf;
+ u32 val32;
+ u8 val8;
+
+ switch (malta_sys_con()) {
+ case SYSCON_GT64120:
+ set_io_port_base(CKSEG1ADDR(MALTA_GT_PCIIO_BASE));
+
+ gt64120_pci_init((void *)CKSEG1ADDR(MALTA_GT_BASE),
+ 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE,
+ 0x10000000, 0x10000000, 128 * 1024 * 1024,
+ 0x00000000, 0x00000000, 0x20000);
+ break;
+
+ default:
+ case SYSCON_MSC01:
+ set_io_port_base(CKSEG1ADDR(MALTA_MSC01_PCIIO_BASE));
+
+ msc01_pci_init((void *)CKSEG1ADDR(MALTA_MSC01_PCI_BASE),
+ 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE,
+ MALTA_MSC01_PCIMEM_MAP,
+ CKSEG1ADDR(MALTA_MSC01_PCIMEM_BASE),
+ MALTA_MSC01_PCIMEM_SIZE, MALTA_MSC01_PCIIO_MAP,
+ 0x00000000, MALTA_MSC01_PCIIO_SIZE);
+ break;
+ }
+
+ bdf = pci_find_device(PCI_VENDOR_ID_INTEL,
+ PCI_DEVICE_ID_INTEL_82371AB_0, 0);
+ if (bdf == -1)
+ panic("Failed to find PIIX4 PCI bridge\n");
+
+ /* setup PCI interrupt routing */
+ pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCA, 10);
+ pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCB, 10);
+ pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCC, 11);
+ pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCD, 11);
+
+ /* mux SERIRQ onto SERIRQ pin */
+ pci_read_config_dword(bdf, PCI_CFG_PIIX4_GENCFG, &val32);
+ val32 |= PCI_CFG_PIIX4_GENCFG_SERIRQ;
+ pci_write_config_dword(bdf, PCI_CFG_PIIX4_GENCFG, val32);
+
+ /* enable SERIRQ - Linux currently depends upon this */
+ pci_read_config_byte(bdf, PCI_CFG_PIIX4_SERIRQC, &val8);
+ val8 |= PCI_CFG_PIIX4_SERIRQC_EN | PCI_CFG_PIIX4_SERIRQC_CONT;
+ pci_write_config_byte(bdf, PCI_CFG_PIIX4_SERIRQC, val8);
+}
diff --git a/board/imgtec/malta/superio.c b/board/imgtec/malta/superio.c
new file mode 100644
index 0000000..eaa14df
--- /dev/null
+++ b/board/imgtec/malta/superio.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright (C) 2013 Imagination Technologies
+ * Author: Paul Burton <paul.burton@imgtec.com>
+ *
+ * Setup code for the FDC37M817 super I/O controller
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+#define SIO_CONF_PORT 0x3f0
+#define SIO_DATA_PORT 0x3f1
+
+enum sio_conf_key {
+ SIOCONF_DEVNUM = 0x07,
+ SIOCONF_ACTIVATE = 0x30,
+ SIOCONF_ENTER_SETUP = 0x55,
+ SIOCONF_BASE_HIGH = 0x60,
+ SIOCONF_BASE_LOW = 0x61,
+ SIOCONF_PRIMARY_INT = 0x70,
+ SIOCONF_EXIT_SETUP = 0xaa,
+ SIOCONF_MODE = 0xf0,
+};
+
+static struct {
+ u8 key;
+ u8 data;
+} sio_config[] = {
+ /* tty0 */
+ { SIOCONF_DEVNUM, 0x04 },
+ { SIOCONF_BASE_HIGH, 0x03 },
+ { SIOCONF_BASE_LOW, 0xf8 },
+ { SIOCONF_MODE, 0x02 },
+ { SIOCONF_PRIMARY_INT, 0x04 },
+ { SIOCONF_ACTIVATE, 0x01 },
+
+ /* tty1 */
+ { SIOCONF_DEVNUM, 0x05 },
+ { SIOCONF_BASE_HIGH, 0x02 },
+ { SIOCONF_BASE_LOW, 0xf8 },
+ { SIOCONF_MODE, 0x02 },
+ { SIOCONF_PRIMARY_INT, 0x03 },
+ { SIOCONF_ACTIVATE, 0x01 },
+};
+
+void malta_superio_init(void *io_base)
+{
+ unsigned i;
+
+ /* enter config state */
+ writeb(SIOCONF_ENTER_SETUP, io_base + SIO_CONF_PORT);
+
+ /* configure peripherals */
+ for (i = 0; i < ARRAY_SIZE(sio_config); i++) {
+ writeb(sio_config[i].key, io_base + SIO_CONF_PORT);
+ writeb(sio_config[i].data, io_base + SIO_DATA_PORT);
+ }
+
+ /* exit config state */
+ writeb(SIOCONF_EXIT_SETUP, io_base + SIO_CONF_PORT);
+}
diff --git a/board/imgtec/malta/superio.h b/board/imgtec/malta/superio.h
new file mode 100644
index 0000000..1450da5
--- /dev/null
+++ b/board/imgtec/malta/superio.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2013 Imagination Technologies
+ * Author: Paul Burton <paul.burton@imgtec.com>
+ *
+ * Setup code for the FDC37M817 super I/O controller
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __BOARD_MALTA_SUPERIO_H__
+#define __BOARD_MALTA_SUPERIO_H__
+
+extern void malta_superio_init(void *io_base);
+
+#endif /* __BOARD_MALTA_SUPERIO_H__ */
diff --git a/board/keymile/km82xx/Makefile b/board/keymile/km82xx/Makefile
index b44582f..20f193a 100644
--- a/board/keymile/km82xx/Makefile
+++ b/board/keymile/km82xx/Makefile
@@ -5,7 +5,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
obj-y := km82xx.o ../common/common.o ../common/ivm.o
diff --git a/board/keymile/km83xx/Makefile b/board/keymile/km83xx/Makefile
index 7bdddf3..6c32688 100644
--- a/board/keymile/km83xx/Makefile
+++ b/board/keymile/km83xx/Makefile
@@ -5,8 +5,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
obj-y += km83xx.o ../common/common.o ../common/ivm.o km83xx_i2c.o
diff --git a/board/keymile/km_arm/Makefile b/board/keymile/km_arm/Makefile
index 32eaa93..a17d8d9 100644
--- a/board/keymile/km_arm/Makefile
+++ b/board/keymile/km_arm/Makefile
@@ -6,10 +6,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
obj-y := km_arm.o ../common/common.o ../common/ivm.o
ifdef CONFIG_KM_FPGA_CONFIG
diff --git a/board/keymile/kmp204x/Makefile b/board/keymile/kmp204x/Makefile
index 64eb37c..3e69ee2 100644
--- a/board/keymile/kmp204x/Makefile
+++ b/board/keymile/kmp204x/Makefile
@@ -8,9 +8,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
-obj-y := $(BOARD).o ddr.o eth.o tlb.o pci.o law.o \
+obj-y := kmp204x.o ddr.o eth.o tlb.o pci.o law.o \
../common/common.o ../common/ivm.o
diff --git a/board/keymile/kmp204x/ddr.c b/board/keymile/kmp204x/ddr.c
index bd425aa..34ac697 100644
--- a/board/keymile/kmp204x/ddr.c
+++ b/board/keymile/kmp204x/ddr.c
@@ -11,8 +11,8 @@
#include <i2c.h>
#include <hwconfig.h>
#include <asm/mmu.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
diff --git a/board/kmc/kzm9g/kzm9g.c b/board/kmc/kzm9g/kzm9g.c
index b669ffe..ea36fa4 100644
--- a/board/kmc/kzm9g/kzm9g.c
+++ b/board/kmc/kzm9g/kzm9g.c
@@ -289,7 +289,6 @@
{
u8 data;
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
data = 0x35;
i2c_set_bus_num(0);
i2c_write(0x40, 3, 1, &data, 1);
diff --git a/board/kup/kup4k/Makefile b/board/kup/kup4k/Makefile
index b3ad86c..c896fcd 100644
--- a/board/kup/kup4k/Makefile
+++ b/board/kup/kup4k/Makefile
@@ -5,8 +5,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
obj-y = kup4k.o ../common/flash.o ../common/kup.o ../common/load_sernum_ethaddr.o ../common/pcmcia.o
diff --git a/board/kup/kup4x/Makefile b/board/kup/kup4x/Makefile
index 05a1afc..6945943 100644
--- a/board/kup/kup4x/Makefile
+++ b/board/kup/kup4x/Makefile
@@ -5,8 +5,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
obj-y = kup4x.o ../common/flash.o ../common/kup.o ../common/load_sernum_ethaddr.o ../common/pcmcia.o
diff --git a/board/logicpd/am3517evm/am3517evm.c b/board/logicpd/am3517evm/am3517evm.c
index b6c68da..1569905 100644
--- a/board/logicpd/am3517evm/am3517evm.c
+++ b/board/logicpd/am3517evm/am3517evm.c
@@ -98,8 +98,8 @@
*/
int misc_init_r(void)
{
-#ifdef CONFIG_DRIVER_OMAP34XX_I2C
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+#ifdef CONFIG_SYS_I2C_OMAP34XX
+ i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
#endif
dieid_num_r();
diff --git a/board/matrix_vision/mvsmr/u-boot.lds b/board/matrix_vision/mvsmr/u-boot.lds
index 08ce014..e885b7c 100644
--- a/board/matrix_vision/mvsmr/u-boot.lds
+++ b/board/matrix_vision/mvsmr/u-boot.lds
@@ -18,7 +18,7 @@
/* the first two sectors (=8KB) of our S29GL flash chip */
arch/powerpc/cpu/mpc5xxx/start.o (.text*)
arch/powerpc/cpu/mpc5xxx/traps.o (.text*)
- board/matrix_vision/common/libmatrix_vision.o (.text*)
+ board/matrix_vision/common/built-in.o (.text*)
/* This is only needed to force failure if size of above code will ever */
/* increase and grow into reserved space. */
diff --git a/board/mpl/mip405/Makefile b/board/mpl/mip405/Makefile
index 509eb59..5bcf130 100644
--- a/board/mpl/mip405/Makefile
+++ b/board/mpl/mip405/Makefile
@@ -5,10 +5,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
obj-y = mip405.o cmd_mip405.o \
../common/pci.o \
../common/usb_uhci.o \
diff --git a/board/mpl/pati/Makefile b/board/mpl/pati/Makefile
index 67381c1..9822082 100644
--- a/board/mpl/pati/Makefile
+++ b/board/mpl/pati/Makefile
@@ -5,9 +5,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
obj-y := pati.o cmd_pati.o \
../common/common_util.o
diff --git a/board/mpl/pip405/Makefile b/board/mpl/pip405/Makefile
index 3d73cc3..0a3d059 100644
--- a/board/mpl/pip405/Makefile
+++ b/board/mpl/pip405/Makefile
@@ -5,10 +5,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
obj-y = pip405.o cmd_pip405.o \
../common/pci.o \
../common/isa.o \
diff --git a/board/mpl/vcma9/Makefile b/board/mpl/vcma9/Makefile
index e0e9669..175a19f 100644
--- a/board/mpl/vcma9/Makefile
+++ b/board/mpl/vcma9/Makefile
@@ -5,10 +5,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
obj-y := ../common/common_util.o
obj-y += vcma9.o cmd_vcma9.o
diff --git a/board/mvblue/u-boot.lds b/board/mvblue/u-boot.lds
index 121354b..5034a96 100644
--- a/board/mvblue/u-boot.lds
+++ b/board/mvblue/u-boot.lds
@@ -14,12 +14,12 @@
.text :
{
arch/powerpc/cpu/mpc824x/start.o (.text*)
- lib/libgeneric.o (.text*)
- net/libnet.o (.text*)
- drivers/pci/libpci.o (.text*)
- arch/powerpc/cpu/mpc824x/libmpc824x.o (.text*)
- board/mvblue/libmvblue.o (.text*)
- arch/powerpc/lib/libpowerpc.o (.text*)
+ lib/built-in.o (.text*)
+ net/built-in.o (.text*)
+ drivers/pci/built-in.o (.text*)
+ arch/powerpc/cpu/mpc824x/built-in.o (.text*)
+ board/mvblue/built-in.o (.text*)
+ arch/powerpc/lib/built-in.o (.text*)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o (.ppcenv*)
diff --git a/board/nvidia/beaver/Makefile b/board/nvidia/beaver/Makefile
index f828f52..1f7c31d 100644
--- a/board/nvidia/beaver/Makefile
+++ b/board/nvidia/beaver/Makefile
@@ -14,6 +14,4 @@
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
-$(shell mkdir -p $(obj)../cardhu)
-
obj-y = ../cardhu/cardhu.o
diff --git a/board/nvidia/ventana/Makefile b/board/nvidia/ventana/Makefile
index 7265cfc..f67044f 100644
--- a/board/nvidia/ventana/Makefile
+++ b/board/nvidia/ventana/Makefile
@@ -5,6 +5,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-$(shell mkdir -p $(obj)../seaboard)
-
obj-y = ../seaboard/seaboard.o
diff --git a/board/overo/overo.c b/board/overo/overo.c
index aace42a..9ac35d2 100644
--- a/board/overo/overo.c
+++ b/board/overo/overo.c
@@ -92,7 +92,7 @@
{
int revision;
-#ifdef CONFIG_DRIVER_OMAP34XX_I2C
+#ifdef CONFIG_SYS_I2C_OMAP34XX
unsigned char data;
/* board revisions <= R2410 connect 4030 irq_1 to gpio112 */
diff --git a/board/phytec/pcm051/board.c b/board/phytec/pcm051/board.c
index 6a27e56..68463e7 100644
--- a/board/phytec/pcm051/board.c
+++ b/board/phytec/pcm051/board.c
@@ -130,7 +130,7 @@
{
/* Initalize the board header */
enable_i2c0_pin_mux();
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+ i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
enable_board_pin_mux();
}
@@ -141,7 +141,7 @@
*/
int board_init(void)
{
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+ i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
diff --git a/board/pn62/Makefile b/board/pn62/Makefile
deleted file mode 100644
index 7572ed8..0000000
--- a/board/pn62/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = pn62.o cmd_pn62.o misc.o
diff --git a/board/pn62/cmd_pn62.c b/board/pn62/cmd_pn62.c
deleted file mode 100644
index a0326b4..0000000
--- a/board/pn62/cmd_pn62.c
+++ /dev/null
@@ -1,146 +0,0 @@
-/*
- * (C) Copyright 2002
- * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <malloc.h>
-#include <net.h>
-#include <asm/io.h>
-#include <pci.h>
-#include <command.h>
-#include "pn62.h"
-
-#if defined(CONFIG_CMD_BSP)
-
-/*
- * Command led: controls the various LEDs 0..11 on the PN62 card.
- */
-int do_led(cmd_tbl_t * cmdtp, int flag, int argc, char *const argv[])
-{
- unsigned int number, function;
-
- if (argc != 3)
- return cmd_usage(cmdtp);
-
- number = simple_strtoul(argv[1], NULL, 10);
- if (number > PN62_LED_MAX)
- return 1;
-
- function = simple_strtoul(argv[2], NULL, 16);
- set_led(number, function);
- return 0;
-}
-U_BOOT_CMD(
- led , 3, 1, do_led,
- "set LED 0..11 on the PN62 board",
- "i fun"
- " - set 'i'th LED to function 'fun'"
-);
-
-/*
- * Command loadpci: loads a image over PCI.
- */
-#define CMD_MOVE_WINDOW 0x1
-#define CMD_BOOT_IMAGE 0x2
-
-int do_loadpci (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- char *s;
- ulong addr = 0, count = 0;
- u32 off;
- int cmd, rcode = 0;
-
- /* pre-set load_addr */
- if ((s = getenv("loadaddr")) != NULL) {
- addr = simple_strtoul(s, NULL, 16);
- }
-
- switch (argc) {
- case 1:
- break;
- case 2:
- addr = simple_strtoul(argv[1], NULL, 16);
- break;
- default:
- return cmd_usage(cmdtp);
- }
-
- printf ("## Ready for image download ...\n");
-
- show_startup_phase(12);
-
- while (1) {
- /* Alive indicator */
- i2155x_write_scrapad(BOOT_PROTO, BOOT_PROTO_READY);
-
- /* Toggle status LEDs */
- cmd = (count / 200) % 4; /* downscale */
- set_led(4, cmd == 0 ? LED_1 : LED_0);
- set_led(5, cmd == 1 ? LED_1 : LED_0);
- set_led(6, cmd == 2 ? LED_1 : LED_0);
- set_led(7, cmd == 3 ? LED_1 : LED_0);
- udelay(1000);
- count++;
-
- cmd = i2155x_read_scrapad(BOOT_CMD);
-
- if (cmd == BOOT_CMD_MOVE) {
- off = i2155x_read_scrapad(BOOT_DATA);
- off += addr;
- i2155x_set_bar_base(3, off);
- printf ("## BAR3 Addr moved = 0x%08x\n", off);
- i2155x_write_scrapad(BOOT_CMD, ~cmd);
- show_startup_phase(13);
- }
- else if (cmd == BOOT_CMD_BOOT) {
- set_led(4, LED_1);
- set_led(5, LED_1);
- set_led(6, LED_1);
- set_led(7, LED_1);
-
- i2155x_write_scrapad(BOOT_CMD, ~cmd);
- show_startup_phase(14);
- break;
- }
-
- /* Abort if ctrl-c was pressed */
- if (ctrlc()) {
- printf("\nAbort\n");
- return 0;
- }
-
- }
-
- /* Repoint to the default shared memory */
- i2155x_set_bar_base(3, PN62_SMEM_DEFAULT);
-
- load_addr = addr;
- printf ("## Start Addr = 0x%08lx\n", addr);
-
- show_startup_phase(15);
-
- /* Loading ok, check if we should attempt an auto-start */
- if (((s = getenv("autostart")) != NULL) && (strcmp(s,"yes") == 0)) {
- char *local_args[2];
- local_args[0] = argv[0];
- local_args[1] = NULL;
-
- printf ("Automatic boot of image at addr 0x%08lX ...\n",
- load_addr);
- rcode = do_bootm (cmdtp, 0, 1, local_args);
- }
-
- return rcode;
-}
-
-U_BOOT_CMD(
- loadpci, 2, 1, do_loadpci,
- "load binary file over PCI",
- "[addr]\n"
- " - load binary file over PCI to address 'addr'"
-);
-
-#endif
diff --git a/board/pn62/misc.c b/board/pn62/misc.c
deleted file mode 100644
index 98e0dfa..0000000
--- a/board/pn62/misc.c
+++ /dev/null
@@ -1,219 +0,0 @@
-/*
- * (C) Copyright 2002 Wolfgang Grandegger <wg@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc824x.h>
-#include <asm/io.h>
-#include <pci.h>
-
-#include "pn62.h"
-
-typedef struct {
- pci_dev_t devno;
- volatile u32 *csr;
-
-} i2155x_t;
-
-static i2155x_t i2155x = { 0, NULL };
-
-static struct pci_device_id i2155x_ids[] = {
- { 0x1011, 0x0046 }, /* i21554 */
- { 0x8086, 0xb555 } /* i21555 */
-};
-
-int i2155x_init(void)
-{
- pci_dev_t devno;
- u32 val;
- int i;
-
- /*
- * Find the Intel bridge.
- */
- if ((devno = pci_find_devices(i2155x_ids, 0)) < 0) {
- printf("Error: Intel bridge 2155x not found!\n");
- return -1;
- }
- i2155x.devno = devno;
-
- /*
- * Get auto-configured base address for CSR access.
- */
- pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &val);
- if (val & PCI_BASE_ADDRESS_SPACE_IO) {
- val &= PCI_BASE_ADDRESS_IO_MASK;
- i2155x.csr = (volatile u32 *)(_IO_BASE + val);
- } else {
- val &= PCI_BASE_ADDRESS_MEM_MASK;
- i2155x.csr = (volatile u32 *)val;
- }
-
- /*
- * Translate downstream memory 2 (bar3) to base of shared memory.
- */
- i2155x_set_bar_base(3, PN62_SMEM_DEFAULT);
-
- /*
- * Enable memory space, I/O space and bus master bits
- * in both Primary and Secondary command registers.
- */
- val = PCI_COMMAND_MEMORY|PCI_COMMAND_MASTER|PCI_COMMAND_IO;
- pci_write_config_word(devno, 0x44, val);
- pci_write_config_word(devno, 0x04, val);
-
- /*
- * Clear scratchpad registers.
- */
- for (i = 0; i < (I2155X_SCRAPAD_MAX - 1); i++) {
- i2155x_write_scrapad(i, 0x0);
- }
-
- /*
- * Set interrupt line for Linux.
- */
- pci_write_config_byte(devno, PCI_INTERRUPT_LINE, 3);
-
- return 0;
-}
-
-/*
- * Access the Scratchpad registers 0..7 of the Intel bridge.
- */
-void i2155x_write_scrapad(int idx, u32 val)
-{
- if (idx >= 0 && idx < I2155X_SCRAPAD_MAX)
- out_le32(i2155x.csr + (I2155X_SCRAPAD_ADDR/4) + idx, val);
- else
- printf("i2155x_write_scrapad: invalid index\n");
-}
-
-u32 i2155x_read_scrapad(int idx)
-{
- if (idx >= 0 && idx < I2155X_SCRAPAD_MAX)
- return in_le32(i2155x.csr + (I2155X_SCRAPAD_ADDR/4) + idx);
- else
- printf("i2155x_read_scrapad: invalid index\n");
- return -1;
-}
-
-void i2155x_set_bar_base(int bar, u32 base)
-{
- if (bar >= 2 && bar <= 4) {
- pci_write_config_dword(i2155x.devno,
- I2155X_BAR2_BASE + (bar - 2) * 4,
- base);
- }
-}
-
-/*
- * Read Vital Product Data (VPD) from the Serial EPROM attached
- * to the Intel bridge.
- */
-int i2155x_read_vpd(int offset, int size, unsigned char *data)
-{
- int i, n;
- u16 val16;
-
- for (i = 0; i < size; i++) {
- pci_write_config_word(i2155x.devno, I2155X_VPD_ADDR,
- offset + i - I2155X_VPD_START);
- for (n = 10000; n > 0; n--) {
- pci_read_config_word(i2155x.devno, I2155X_VPD_ADDR, &val16);
- if ((val16 & 0x8000) != 0) /* wait for completion */
- break;
- udelay(100);
- }
- if (n == 0) {
- printf("i2155x_read_vpd: TIMEOUT\n");
- return -1;
- }
-
- pci_read_config_byte(i2155x.devno, I2155X_VPD_DATA, &data[i]);
- }
-
- return i;
-}
-
-static struct pci_device_id am79c95x_ids [] = {
- { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE },
- { }
-};
-
-
-/*
- * Initialize the AMD ethernet controllers.
- */
-int am79c95x_init(void)
-{
- pci_dev_t devno;
- int i;
-
- /*
- * Set interrupt line for Linux.
- */
- for (i = 0; i < 2; i++) {
- if ((devno = pci_find_devices(am79c95x_ids, i)) < 0)
- break;
- pci_write_config_byte(devno, PCI_INTERRUPT_LINE, 2+i);
- }
- if (i < 2)
- printf("Error: Only %d AMD Ethernet Controller found!\n", i);
-
- return 0;
-}
-
-
-void set_led(unsigned int number, unsigned int function)
-{
- volatile u8 *addr;
-
- if ((number >= 0) && (number < PN62_LED_MAX) &&
- (function >= 0) && (function <= LED_LAST_FUNCTION)) {
- addr = (volatile u8 *)(PN62_LED_BASE + number * 8);
- out_8(addr, function&0xff);
- }
-}
-
-/*
- * Show fatal error indicated by Kinght Rider(tm) effect
- * in LEDS 0-7. LEDS 8-11 contain 4 bit error code.
- * Note: this function will not terminate.
- */
-void fatal_error(unsigned int error_code)
-{
- int i, d;
-
- for (i = 0; i < 12; i++) {
- set_led(i, LED_0);
- }
-
- /*
- * Write error code.
- */
- set_led(8, (error_code & 0x01) ? LED_1 : LED_0);
- set_led(9, (error_code & 0x02) ? LED_1 : LED_0);
- set_led(10, (error_code & 0x04) ? LED_1 : LED_0);
- set_led(11, (error_code & 0x08) ? LED_1 : LED_0);
-
- /*
- * Yay - Knight Rider effect!
- */
- while(1) {
- unsigned int delay = 2000;
-
- for (i = 0; i < 8; i++) {
- set_led(i, LED_1);
- for (d = 0; d < delay; d++);
- set_led(i, LED_0);
- }
-
- for (i = 7; i > 0; i--) {
- set_led(i, LED_1);
- for (d = 0; d < delay; d++);
- set_led(i, LED_0);
- }
- }
-}
diff --git a/board/pn62/pn62.c b/board/pn62/pn62.c
deleted file mode 100644
index 81829dd..0000000
--- a/board/pn62/pn62.c
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
- * (C) Copyright 2002 Wolfgang Grandegger <wg@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc824x.h>
-#include <net.h>
-#include <pci.h>
-#include <netdev.h>
-
-#include "pn62.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static int get_serial_number (char *string, int size);
-static void get_mac_address(int id, u8 *mac);
-
-#ifdef CONFIG_SHOW_BOOT_PROGRESS
-void show_boot_progress (int phase)
-{
- /*
- * Show phases of the bootm command on the front panel
- * LEDs and the scratchpad register #3 as well. We use
- * blinking LEDs for logical "1".
- */
- if (phase > 0) {
- set_led (8, (phase & 0x1) ? LED_SLOW_CLOCK : LED_0);
- set_led (9, (phase & 0x2) ? LED_SLOW_CLOCK : LED_0);
- set_led (10, (phase & 0x4) ? LED_SLOW_CLOCK : LED_0);
- set_led (11, (phase & 0x8) ? LED_SLOW_CLOCK : LED_0);
- }
- i2155x_write_scrapad (BOOT_STATUS, phase);
- if (phase < 0)
- i2155x_write_scrapad (BOOT_DONE, BOOT_DONE_ERROR);
-}
-#endif
-
-void show_startup_phase (int phase)
-{
- /*
- * Show the phase of U-Boot startup on the front panel
- * LEDs and the scratchpad register #3 as well.
- */
- if (phase > 0) {
- set_led (8, (phase & 0x1) ? LED_1 : LED_0);
- set_led (9, (phase & 0x2) ? LED_1 : LED_0);
- set_led (10, (phase & 0x4) ? LED_1 : LED_0);
- set_led (11, (phase & 0x8) ? LED_1 : LED_0);
- }
- i2155x_write_scrapad (BOOT_STATUS, phase);
- if (phase < 0)
- i2155x_write_scrapad (BOOT_DONE, BOOT_DONE_ERROR);
-}
-
-int checkboard (void)
-{
- show_startup_phase (1);
- puts ("Board: PN62\n");
- return 0;
-}
-
-phys_size_t initdram (int board_type)
-{
- long size;
- long new_bank0_end;
- long mear1;
- long emear1;
-
- show_startup_phase (2);
-
- size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE);
-
- new_bank0_end = size - 1;
- mear1 = mpc824x_mpc107_getreg (MEAR1);
- emear1 = mpc824x_mpc107_getreg (EMEAR1);
- mear1 = (mear1 & 0xFFFFFF00) |
- ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
- emear1 = (emear1 & 0xFFFFFF00) |
- ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
- mpc824x_mpc107_setreg (MEAR1, mear1);
- mpc824x_mpc107_setreg (EMEAR1, emear1);
-
- return (size);
-}
-
-/*
- * Initialize PCI Devices. We rely on auto-configuration.
- */
-#ifndef CONFIG_PCI_PNP
-#error "CONFIG_PCI_PNP is not defined, please correct!"
-#endif
-
-struct pci_controller hose = {
-};
-
-void pci_init_board (void)
-{
- show_startup_phase (4);
- pci_mpc824x_init (&hose);
-
- show_startup_phase (5);
- i2155x_init ();
- show_startup_phase (6);
- am79c95x_init ();
- show_startup_phase (7);
-}
-
-int misc_init_r (void)
-{
- char str[20];
- u8 mac[6];
-
- show_startup_phase (8);
- /*
- * Get serial number and ethernet addresses if not already defined
- * and update the board info structure and the environment.
- */
- if (getenv ("serial#") == NULL &&
- get_serial_number (str, strlen (str)) > 0) {
- setenv ("serial#", str);
- }
- show_startup_phase (9);
-
- if (!eth_getenv_enetaddr("ethaddr", mac)) {
- get_mac_address(0, mac);
- eth_setenv_enetaddr("ethaddr", mac);
- }
- show_startup_phase (10);
-
-#ifdef CONFIG_HAS_ETH1
- if (!eth_getenv_enetaddr("eth1addr", mac)) {
- get_mac_address(1, mac);
- eth_setenv_enetaddr("eth1addr", mac);
- }
-#endif /* CONFIG_HAS_ETH1 */
- show_startup_phase (11);
-
- /* Tell everybody that U-Boot is up and runnig */
- i2155x_write_scrapad (0, 0x12345678);
- return (0);
-}
-
-static int get_serial_number (char *string, int size)
-{
- int i;
- char c;
-
- if (size < I2155X_VPD_SN_SIZE)
- size = I2155X_VPD_SN_SIZE;
- for (i = 0; i < (size - 1); i++) {
- i2155x_read_vpd (I2155X_VPD_SN_START + i, 1, (uchar *)&c);
- if (c == '\0')
- break;
- string[i] = c;
- }
- string[i] = '\0'; /* make sure it's terminated */
-
- return i;
-}
-
-static void get_mac_address(int id, u8 *mac)
-{
- i2155x_read_vpd (I2155X_VPD_MAC0_START + 6 * id, 6, mac);
-}
-
-int board_eth_init(bd_t *bis)
-{
- return pci_eth_init(bis);
-}
diff --git a/board/pn62/pn62.h b/board/pn62/pn62.h
deleted file mode 100644
index 10290c3..0000000
--- a/board/pn62/pn62.h
+++ /dev/null
@@ -1,145 +0,0 @@
-/*
- * (C) Copyright 2002 Wolfgang Grandegger <wg@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _PN62_H_
-#define _PN62_H_
-
-/*
- * Definitions for the Intel Bridge 21554 or 21555.
- */
-#define I2155X_VPD_ADDR 0xe6
-#define I2155X_VPD_DATA 0xe8
-
-#define I2155X_VPD_START 0x80
-#define I2155X_VPD_SN_START 0x80
-#define I2155X_VPD_SN_SIZE 0x10
-#define I2155X_VPD_MAC0_START 0x90
-#define I2155X_VPD_MAC1_START 0x96
-
-#define I2155X_SCRAPAD_ADDR 0xa8
-#define I2155X_SCRAPAD_MAX 8
-
-#define I2155X_BAR2_BASE 0x98
-#define I2155X_BAR3_BASE 0x9c
-#define I2155X_BAR4_BASE 0xa0
-
-#define I2155X_BAR2_SETUP 0xb0
-#define I2155X_BAR3_SETUP 0xb4
-#define I2155X_BAR4_SETUP 0xb8
-
-/*
- * Interrupt request numbers
- */
-#define PN62_IRQ_HOST 0x0
-#define PN62_IRQ_PLX9054 0x1
-#define PN62_IRQ_ETH0 0x2
-#define PN62_IRQ_ETH1 0x3
-#define PN62_IRQ_COM1 0x4
-#define PN62_IRQ_COM2 0x4
-
-/*
- * Miscellaneous definitons.
- */
-#define PN62_SMEM_DEFAULT 0x1f00000
-
-/*
- * Definitions for boot protocol using Scratchpad registers.
- */
-#define BOOT_DONE 0
-#define BOOT_DONE_CLEAR 0x00dead00
-#define BOOT_DONE_ERROR 0xbad0dead
-#define BOOT_DONE_U_BOOT 0x12345678
-#define BOOT_DONE_LINUX 0x87654321
-#define BOOT_CMD 1
-#define BOOT_CMD_MOVE 0x1
-#define BOOT_CMD_BOOT 0x2
-#define BOOT_DATA 2
-#define BOOT_PROTO 3
-#define BOOT_PROTO_READY 0x23456789
-#define BOOT_PROTO_CLEAR 0x00000000
-#define BOOT_STATUS 4
-
-/*
- * LED Definitions:
- */
-#define PN62_LED_BASE 0xff800300
-#define PN62_LED_MAX 12
-
-/*
- * LED0 - 7 mounted on top of board, D1 - D8
- * LED8 - 11 upper four LEDs on the front panel of the board.
- */
-#define LED_0 0x00 /* OFF */
-#define LED_1 0x01 /* ON */
-#define LED_SLOW_CLOCK 0x02 /* SLOW 1Hz ish */
-#define LED_nSLOW_CLOCK 0x03 /* inverse of above */
-#define LED_WATCHDOG_OUT 0x06 /* Reset Watchdog level */
-#define LED_WATCHDOG_CLOCK 0x07 /* clock to watchdog */
-
-/*
- * LED's currently setup in AMD79C973 device as the following:
- * LED0 100Mbit
- * LED1 LNKSE
- * LED2 TX Activity
- * LED3 RX Activity
- */
-#define LED_E0_LED0 0x08 /* Ethernet Port 0 LED 0 */
-#define LED_E0_LED1 0x09 /* Ethernet Port 0 LED 1 */
-#define LED_E0_LED2 0x0A /* Ethernet Port 0 LED 2 */
-#define LED_E0_LED3 0x0B /* Ethernet Port 0 LED 3 */
-#define LED_E1_LED0 0x0C /* Ethernet Port 1 LED 0 */
-#define LED_E1_LED1 0x0D /* Ethernet Port 1 LED 1 */
-#define LED_E1_LED2 0x0E /* Ethernet Port 1 LED 2 */
-#define LED_E1_LED3 0x0F /* Ethernet Port 1 LED 3 */
-#define LED_STROBE0 0x10 /* Processor Strobe 0 */
-#define LED_STROBE1 0x11 /* Processor Strobe 1 */
-#define LED_STROBE2 0x12 /* Processor Strobe 2 */
-#define LED_STROBE3 0x13 /* Processor Strobe 3 */
-#define LED_STROBE4 0x14 /* Processor Strobe 4 */
-#define LED_STROBE5 0x15 /* Processor Strobe 5 */
-#define LED_STROBE6 0x16 /* Processor Strobe 6 */
-#define LED_STROBE7 0x17 /* Processor Strobe 7 */
-#define LED_HOST_STROBE0 0x18 /* Host strobe 0 */
-#define LED_HOST_STROBE1 0x19 /* Host strobe 1 */
-#define LED_HOST_STROBE2 0x1A /* Host strobe 2 */
-#define LED_HOST_STROBE3 0x1B /* Host strobe 3 */
-#define LED_HOST_STROBE4 0x1C /* Host strobe 4 */
-#define LED_HOST_STROBE5 0x1D /* Host strobe 5 */
-#define LED_HOST_STROBE6 0x1E /* Host strobe 6 */
-#define LED_HOST_STROBE7 0x1F /* Host strobe 7 */
-#define LED_MPC_INT0 0x20 /* MPC8240 INT 0 */
-#define LED_MPC_INT1 0x21 /* MPC8240 INT 1 */
-#define LED_MPC_INT2 0x22 /* MPC8240 INT 2 */
-#define LED_MPC_INT3 0x23 /* MPC8240 INT 3 */
-#define LED_MPC_INT4 0x24 /* MPC8240 INT 4 */
-#define LED_UART0_CS 0x25 /* UART 0 Chip Select */
-#define LED_UART1_CS 0x26 /* UART 1 Chip Select */
-#define LED_SRAM_CS 0x27 /* SRAM Chip Select */
-#define LED_SRAM_WR 0x28 /* SRAM WR Signal */
-#define LED_SRAM_RD 0x29 /* SRAM RD Signal */
-#define LED_MPC_RCS0 0x2A /* MPC8240 RCS0 Signal */
-#define LED_S_PCI_FRAME 0x2B /* Secondary PCI Frame Signal */
-#define LED_MPC_CS0 0x2C /* MPC8240 CS0 Signal */
-#define LED_HOST_INT 0x2D /* MPC8240 to Host Interrupt signal */
-#define LED_LAST_FUNCTION LED_HOST_INT /* last function */
-
-/*
- * Forward declarations
- */
-int i2155x_init (void);
-void i2155x_write_scrapad(int idx, u32 val);
-u32 i2155x_read_scrapad (int idx);
-void i2155x_set_bar_base (int bar, u32 addr);
-int i2155x_read_vpd (int offset, int size, unsigned char *data);
-
-int am79c95x_init (void);
-
-void set_led (unsigned int number, unsigned int function);
-void fatal_error (unsigned int error_code);
-void show_startup_phase (int phase);
-
-
-#endif /* _PN62_H_ */
diff --git a/board/prodrive/p3mx/Makefile b/board/prodrive/p3mx/Makefile
index 43caffb..6ddda22 100644
--- a/board/prodrive/p3mx/Makefile
+++ b/board/prodrive/p3mx/Makefile
@@ -5,10 +5,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../../Marvell/common)
-endif
-
obj-y = misc.o
obj-y += p3mx.o mpsc.o mv_eth.o pci.o sdram_init.o serial.o \
../../Marvell/common/i2c.o ../../Marvell/common/memory.o
diff --git a/board/psyent/pci5441/Makefile b/board/psyent/pci5441/Makefile
index 9a66cfd..364f163 100644
--- a/board/psyent/pci5441/Makefile
+++ b/board/psyent/pci5441/Makefile
@@ -5,8 +5,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
obj-y := pci5441.o ../common/AMDLV065D.o
diff --git a/board/psyent/pci5441/config.mk b/board/psyent/pci5441/config.mk
index 00ff743..776fa8a 100644
--- a/board/psyent/pci5441/config.mk
+++ b/board/psyent/pci5441/config.mk
@@ -8,7 +8,6 @@
CONFIG_SYS_TEXT_BASE = 0x018e0000
PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul
-PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include
ifeq ($(debug),1)
PLATFORM_CPPFLAGS += -DDEBUG
diff --git a/board/psyent/pk1c20/Makefile b/board/psyent/pk1c20/Makefile
index 286db94..5450f93 100644
--- a/board/psyent/pk1c20/Makefile
+++ b/board/psyent/pk1c20/Makefile
@@ -5,8 +5,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
obj-y := pk1c20.o led.o ../common/AMDLV065D.o
diff --git a/board/psyent/pk1c20/config.mk b/board/psyent/pk1c20/config.mk
index 7b0810a..83cfadc 100644
--- a/board/psyent/pk1c20/config.mk
+++ b/board/psyent/pk1c20/config.mk
@@ -8,7 +8,6 @@
CONFIG_SYS_TEXT_BASE = 0x01fc0000
PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul
-PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include
ifeq ($(debug),1)
PLATFORM_CPPFLAGS += -DDEBUG
diff --git a/board/qemu-malta/lowlevel_init.S b/board/qemu-malta/lowlevel_init.S
deleted file mode 100644
index fa0b6a7..0000000
--- a/board/qemu-malta/lowlevel_init.S
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
- *
- * SPDX-License-Identifier: GPL-2.0
- */
-
-#include <config.h>
-#include <gt64120.h>
-
-#include <asm/addrspace.h>
-#include <asm/regdef.h>
-#include <asm/malta.h>
-
-#ifdef CONFIG_SYS_BIG_ENDIAN
-#define CPU_TO_GT32(_x) ((_x))
-#else
-#define CPU_TO_GT32(_x) ( \
- (((_x) & 0xff) << 24) | (((_x) & 0xff00) << 8) | \
- (((_x) & 0xff0000) >> 8) | (((_x) & 0xff000000) >> 24))
-#endif
-
- .text
- .set noreorder
- .set mips32
-
- .globl lowlevel_init
-lowlevel_init:
-
- /*
- * Load BAR registers of GT64120 as done by YAMON
- *
- * based on a patch sent by Antony Pavlov <antonynpavlov@gmail.com>
- * to the barebox mailing list.
- * The subject of the original patch:
- * 'MIPS: qemu-malta: add YAMON-style GT64120 memory map'
- * URL:
- * http://www.mail-archive.com/barebox@lists.infradead.org/msg06128.html
- *
- * based on write_bootloader() in qemu.git/hw/mips_malta.c
- * see GT64120 manual and qemu.git/hw/gt64xxx.c for details
- */
-
- /* move GT64120 registers from 0x14000000 to 0x1be00000 */
- li t1, KSEG1ADDR(GT_DEF_BASE)
- li t0, CPU_TO_GT32(0xdf000000)
- sw t0, GT_ISD_OFS(t1)
-
- /* setup MEM-to-PCI0 mapping */
- li t1, KSEG1ADDR(MALTA_GT_BASE)
-
- /* setup PCI0 io window to 0x18000000-0x181fffff */
- li t0, CPU_TO_GT32(0xc0000000)
- sw t0, GT_PCI0IOLD_OFS(t1)
- li t0, CPU_TO_GT32(0x40000000)
- sw t0, GT_PCI0IOHD_OFS(t1)
-
- /* setup PCI0 mem windows */
- li t0, CPU_TO_GT32(0x80000000)
- sw t0, GT_PCI0M0LD_OFS(t1)
- li t0, CPU_TO_GT32(0x3f000000)
- sw t0, GT_PCI0M0HD_OFS(t1)
-
- li t0, CPU_TO_GT32(0xc1000000)
- sw t0, GT_PCI0M1LD_OFS(t1)
- li t0, CPU_TO_GT32(0x5e000000)
- sw t0, GT_PCI0M1HD_OFS(t1)
-
- jr ra
- nop
diff --git a/board/qemu-malta/qemu-malta.c b/board/qemu-malta/qemu-malta.c
deleted file mode 100644
index 7eddf1c..0000000
--- a/board/qemu-malta/qemu-malta.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
- *
- * SPDX-License-Identifier: GPL-2.0
- */
-
-#include <common.h>
-#include <netdev.h>
-
-#include <asm/addrspace.h>
-#include <asm/io.h>
-#include <asm/malta.h>
-#include <pci_gt64120.h>
-
-phys_size_t initdram(int board_type)
-{
- return CONFIG_SYS_MEM_SIZE;
-}
-
-int checkboard(void)
-{
- puts("Board: MIPS Malta CoreLV (Qemu)\n");
- return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
- return pci_eth_init(bis);
-}
-
-void _machine_restart(void)
-{
- void __iomem *reset_base;
-
- reset_base = (void __iomem *)CKSEG1ADDR(MALTA_RESET_BASE);
- __raw_writel(GORESET, reset_base);
-}
-
-void pci_init_board(void)
-{
- set_io_port_base(CKSEG1ADDR(MALTA_IO_PORT_BASE));
-
- gt64120_pci_init((void *)CKSEG1ADDR(MALTA_GT_BASE),
- 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE,
- 0x10000000, 0x10000000, 128 * 1024 * 1024,
- 0x00000000, 0x00000000, 0x20000);
-}
diff --git a/board/rbc823/u-boot.lds b/board/rbc823/u-boot.lds
index 191f9eb..7676cf4 100644
--- a/board/rbc823/u-boot.lds
+++ b/board/rbc823/u-boot.lds
@@ -19,10 +19,10 @@
arch/powerpc/cpu/mpc8xx/start.o (.text*)
arch/powerpc/cpu/mpc8xx/traps.o (.text*)
- lib/libgeneric.o (.text*)
- net/libnet.o (.text*)
- arch/powerpc/cpu/mpc8xx/libmpc8xx.o (.text*)
- arch/powerpc/lib/libpowerpc.o (.text*)
+ lib/built-in.o (.text*)
+ net/built-in.o (.text*)
+ arch/powerpc/cpu/mpc8xx/built-in.o (.text*)
+ arch/powerpc/lib/built-in.o (.text*)
. = env_offset;
common/env_embedded.o (.text*)
diff --git a/board/renesas/ecovec/ecovec.c b/board/renesas/ecovec/ecovec.c
index e2d365a..fb4acf3 100644
--- a/board/renesas/ecovec/ecovec.c
+++ b/board/renesas/ecovec/ecovec.c
@@ -57,8 +57,7 @@
outl(inl(MSTPCR2) & ~0x10000000, MSTPCR2);
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
- i2c_set_bus_num(CONFIG_SYS_I2C_MODULE); /* Use I2C 1 */
+ i2c_set_bus_num(1); /* Use I2C 1 */
/* Read MAC address */
i2c_read(0x50, 0x10, 0, mac, 6);
diff --git a/board/sandburst/karef/Makefile b/board/sandburst/karef/Makefile
index 05c8187..f890008 100644
--- a/board/sandburst/karef/Makefile
+++ b/board/sandburst/karef/Makefile
@@ -9,10 +9,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
# TBS: add for debugging purposes
BUILDUSER := $(shell whoami)
FORCEBUILD := $(shell rm -f karef.o)
diff --git a/board/sandburst/metrobox/Makefile b/board/sandburst/metrobox/Makefile
index 76dfffc..37d91a5 100644
--- a/board/sandburst/metrobox/Makefile
+++ b/board/sandburst/metrobox/Makefile
@@ -8,10 +8,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
# TBS: add for debugging purposes
BUILDUSER := $(shell whoami)
FORCEBUILD := $(shell rm -f metrobox.o)
diff --git a/board/sbc8548/Makefile b/board/sbc8548/Makefile
index b1e32a6..4c9b6cd 100644
--- a/board/sbc8548/Makefile
+++ b/board/sbc8548/Makefile
@@ -11,4 +11,4 @@
obj-y += sbc8548.o
obj-y += law.o
obj-y += tlb.o
-obj-$(CONFIG_FSL_DDR2) += ddr.o
+obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o
diff --git a/board/sbc8548/ddr.c b/board/sbc8548/ddr.c
index 9508561..24cc776 100644
--- a/board/sbc8548/ddr.c
+++ b/board/sbc8548/ddr.c
@@ -9,8 +9,8 @@
#include <common.h>
#include <i2c.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
@@ -91,7 +91,8 @@
*/
phys_size_t fixed_sdram(void)
{
- volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR);
+ struct ccsr_ddr __iomem *ddr =
+ (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
out_be32(&ddr->cs0_bnds, 0x0000007f);
out_be32(&ddr->cs1_bnds, 0x008000ff);
diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c
index 3cd945f..d584276 100644
--- a/board/sbc8548/sbc8548.c
+++ b/board/sbc8548/sbc8548.c
@@ -15,7 +15,7 @@
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <spd_sdram.h>
#include <netdev.h>
diff --git a/board/sbc8641d/Makefile b/board/sbc8641d/Makefile
index 9626b06..a9b2026 100644
--- a/board/sbc8641d/Makefile
+++ b/board/sbc8641d/Makefile
@@ -7,4 +7,4 @@
obj-y += sbc8641d.o
obj-y += law.o
-obj-$(CONFIG_FSL_DDR2) += ddr.o
+obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o
diff --git a/board/sbc8641d/ddr.c b/board/sbc8641d/ddr.c
index 996ffe2..b31ea34 100644
--- a/board/sbc8641d/ddr.c
+++ b/board/sbc8641d/ddr.c
@@ -8,8 +8,8 @@
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
diff --git a/board/sbc8641d/sbc8641d.c b/board/sbc8641d/sbc8641d.c
index 0b5e8dc..4906be4 100644
--- a/board/sbc8641d/sbc8641d.c
+++ b/board/sbc8641d/sbc8641d.c
@@ -18,7 +18,7 @@
#include <asm/processor.h>
#include <asm/immap_86xx.h>
#include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <libfdt.h>
#include <fdt_support.h>
@@ -93,7 +93,7 @@
{
#if !defined(CONFIG_SYS_RAMBOOT)
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
+ volatile struct ccsr_ddr *ddr = &immap->im_ddr1;
ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS;
@@ -111,7 +111,7 @@
ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CFG_2;
ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
- ddr->sdram_mode_cntl = CONFIG_SYS_DDR_MODE_CTL;
+ ddr->sdram_md_cntl = CONFIG_SYS_DDR_MODE_CTL;
ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
@@ -142,7 +142,7 @@
ddr->sdram_cfg_2 = CONFIG_SYS_DDR2_CFG_2;
ddr->sdram_mode = CONFIG_SYS_DDR2_MODE_1;
ddr->sdram_mode_2 = CONFIG_SYS_DDR2_MODE_2;
- ddr->sdram_mode_cntl = CONFIG_SYS_DDR2_MODE_CTL;
+ ddr->sdram_md_cntl = CONFIG_SYS_DDR2_MODE_CTL;
ddr->sdram_interval = CONFIG_SYS_DDR2_INTERVAL;
ddr->sdram_data_init = CONFIG_SYS_DDR2_DATA_INIT;
ddr->sdram_clk_cntl = CONFIG_SYS_DDR2_CLK_CTRL;
diff --git a/board/siemens/common/board.c b/board/siemens/common/board.c
index 6279c32..32d2ee4 100644
--- a/board/siemens/common/board.c
+++ b/board/siemens/common/board.c
@@ -42,7 +42,7 @@
{
/* Initalize the board header */
enable_i2c0_pin_mux();
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+ i2c_set_bus_num(0);
if (read_eeprom() < 0)
puts("Could not get board ID.\n");
@@ -67,7 +67,7 @@
#if defined(CONFIG_HW_WATCHDOG)
hw_watchdog_init();
#endif /* defined(CONFIG_HW_WATCHDOG) */
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+ i2c_set_bus_num(0);
if (read_eeprom() < 0)
puts("Could not get board ID.\n");
diff --git a/board/siemens/dxr2/Makefile b/board/siemens/dxr2/Makefile
index 5129c6e..f159932 100644
--- a/board/siemens/dxr2/Makefile
+++ b/board/siemens/dxr2/Makefile
@@ -11,10 +11,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
ifdef CONFIG_SPL_BUILD
obj-y := mux.o
endif
diff --git a/board/siemens/pxm2/Makefile b/board/siemens/pxm2/Makefile
index 5129c6e..f159932 100644
--- a/board/siemens/pxm2/Makefile
+++ b/board/siemens/pxm2/Makefile
@@ -11,10 +11,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
ifdef CONFIG_SPL_BUILD
obj-y := mux.o
endif
diff --git a/board/siemens/rut/Makefile b/board/siemens/rut/Makefile
index 5129c6e..f159932 100644
--- a/board/siemens/rut/Makefile
+++ b/board/siemens/rut/Makefile
@@ -11,10 +11,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
ifdef CONFIG_SPL_BUILD
obj-y := mux.o
endif
diff --git a/board/socrates/Makefile b/board/socrates/Makefile
index 0a08810..79bda71 100644
--- a/board/socrates/Makefile
+++ b/board/socrates/Makefile
@@ -12,4 +12,4 @@
obj-y += tlb.o
obj-y += nand.o
obj-y += sdram.o
-obj-$(CONFIG_FSL_DDR2) += ddr.o
+obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o
diff --git a/board/socrates/ddr.c b/board/socrates/ddr.c
index e9db476..6bad4da 100644
--- a/board/socrates/ddr.c
+++ b/board/socrates/ddr.c
@@ -8,8 +8,8 @@
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
diff --git a/board/socrates/sdram.c b/board/socrates/sdram.c
index 313efae..aebd02f 100644
--- a/board/socrates/sdram.c
+++ b/board/socrates/sdram.c
@@ -8,7 +8,7 @@
#include <common.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <spd_sdram.h>
@@ -24,7 +24,8 @@
*/
phys_size_t fixed_sdram(void)
{
- volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR);
+ struct ccsr_ddr __iomem *ddr =
+ (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
/*
* Disable memory controller.
diff --git a/board/spd8xx/u-boot.lds b/board/spd8xx/u-boot.lds
index 2a68934..463af7e 100644
--- a/board/spd8xx/u-boot.lds
+++ b/board/spd8xx/u-boot.lds
@@ -18,8 +18,8 @@
arch/powerpc/cpu/mpc8xx/start.o (.text*)
arch/powerpc/cpu/mpc8xx/traps.o (.text*)
- net/libnet.o (.text*)
- arch/powerpc/cpu/mpc8xx/libmpc8xx.o (.text*)
+ net/built-in.o (.text*)
+ arch/powerpc/cpu/mpc8xx/built-in.o (.text*)
*(.text.v*printf)
. = DEFINED(env_offset) ? env_offset : .;
diff --git a/board/stx/stxgp3/Makefile b/board/stx/stxgp3/Makefile
index 9b72434..78e2d6c 100644
--- a/board/stx/stxgp3/Makefile
+++ b/board/stx/stxgp3/Makefile
@@ -9,4 +9,4 @@
obj-y += law.o
obj-y += tlb.o
obj-y += flash.o
-obj-$(CONFIG_FSL_DDR1) += ddr.o
+obj-$(CONFIG_SYS_FSL_DDR1) += ddr.o
diff --git a/board/stx/stxgp3/ddr.c b/board/stx/stxgp3/ddr.c
index 9e79815..41d4cfe 100644
--- a/board/stx/stxgp3/ddr.c
+++ b/board/stx/stxgp3/ddr.c
@@ -8,8 +8,8 @@
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
diff --git a/board/stx/stxgp3/stxgp3.c b/board/stx/stxgp3/stxgp3.c
index bd683f6..c80d525 100644
--- a/board/stx/stxgp3/stxgp3.c
+++ b/board/stx/stxgp3/stxgp3.c
@@ -18,7 +18,7 @@
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <ioports.h>
#include <asm/io.h>
#include <spd_sdram.h>
diff --git a/board/stx/stxssa/Makefile b/board/stx/stxssa/Makefile
index 17e0aae..b1d4b0a 100644
--- a/board/stx/stxssa/Makefile
+++ b/board/stx/stxssa/Makefile
@@ -8,4 +8,4 @@
obj-y += stxssa.o
obj-y += law.o
obj-y += tlb.o
-obj-$(CONFIG_FSL_DDR1) += ddr.o
+obj-$(CONFIG_SYS_FSL_DDR1) += ddr.o
diff --git a/board/stx/stxssa/ddr.c b/board/stx/stxssa/ddr.c
index 71be3bf..1ccd4c5 100644
--- a/board/stx/stxssa/ddr.c
+++ b/board/stx/stxssa/ddr.c
@@ -9,8 +9,8 @@
#include <common.h>
#include <i2c.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
diff --git a/board/stx/stxssa/stxssa.c b/board/stx/stxssa/stxssa.c
index c08a18b..f5c3d75 100644
--- a/board/stx/stxssa/stxssa.c
+++ b/board/stx/stxssa/stxssa.c
@@ -19,7 +19,7 @@
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <ioports.h>
#include <asm/io.h>
#include <spd_sdram.h>
diff --git a/board/svm_sc8xx/u-boot.lds b/board/svm_sc8xx/u-boot.lds
index 4922625..df564e9 100644
--- a/board/svm_sc8xx/u-boot.lds
+++ b/board/svm_sc8xx/u-boot.lds
@@ -17,11 +17,11 @@
/* the sector layout of our flash chips! XXX FIXME XXX */
arch/powerpc/cpu/mpc8xx/start.o (.text*)
arch/powerpc/cpu/mpc8xx/traps.o (.text*)
- lib/libgeneric.o (.text*)
- net/libnet.o (.text*)
- arch/powerpc/cpu/mpc8xx/libmpc8xx.o (.text*)
- arch/powerpc/lib/libpowerpc.o (.text*)
- board/svm_sc8xx/libsvm_sc8xx.o (.text*)
+ lib/built-in.o (.text*)
+ net/built-in.o (.text*)
+ arch/powerpc/cpu/mpc8xx/built-in.o (.text*)
+ arch/powerpc/lib/built-in.o (.text*)
+ board/svm_sc8xx/built-in.o (.text*)
*(.text.*printf)
*(.text.do_mem_*)
*(.text.flash*)
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index 1459fae..33693e4 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -380,7 +380,7 @@
struct am335x_baseboard_id header;
enable_i2c0_pin_mux();
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+ i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
if (read_eeprom(&header) < 0)
puts("Could not get board ID.\n");
@@ -464,26 +464,14 @@
*/
int board_init(void)
{
-#ifdef CONFIG_NOR
- const u32 gpmc_nor[GPMC_MAX_REG] = { STNOR_GPMC_CONFIG1,
- STNOR_GPMC_CONFIG2, STNOR_GPMC_CONFIG3, STNOR_GPMC_CONFIG4,
- STNOR_GPMC_CONFIG5, STNOR_GPMC_CONFIG6, STNOR_GPMC_CONFIG7 };
-#endif
-
#if defined(CONFIG_HW_WATCHDOG)
hw_watchdog_init();
#endif
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
+#if defined(CONFIG_NOR) || defined(CONFIG_NAND)
gpmc_init();
-
-#ifdef CONFIG_NOR
- /* Reconfigure CS0 for NOR instead of NAND. */
- enable_gpmc_cs_config(gpmc_nor, &gpmc_cfg->cs[0],
- CONFIG_SYS_FLASH_BASE, GPMC_SIZE_16M);
#endif
-
return 0;
}
diff --git a/board/ti/am335x/u-boot.lds b/board/ti/am335x/u-boot.lds
index 9f96a43..6a734b3 100644
--- a/board/ti/am335x/u-boot.lds
+++ b/board/ti/am335x/u-boot.lds
@@ -35,7 +35,7 @@
{
*(.__image_copy_start)
CPUDIR/start.o (.text*)
- board/ti/am335x/libam335x.o (.text*)
+ board/ti/am335x/built-in.o (.text*)
*(.text*)
}
diff --git a/board/ti/am3517crane/am3517crane.c b/board/ti/am3517crane/am3517crane.c
index 5eb97ff..a649697 100644
--- a/board/ti/am3517crane/am3517crane.c
+++ b/board/ti/am3517crane/am3517crane.c
@@ -43,8 +43,8 @@
*/
int misc_init_r(void)
{
-#ifdef CONFIG_DRIVER_OMAP34XX_I2C
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+#ifdef CONFIG_SYS_I2C_OMAP34XX
+ i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
#endif
dieid_num_r();
diff --git a/board/ti/beagle/Makefile b/board/ti/beagle/Makefile
index 9f55e8f..7a858be 100644
--- a/board/ti/beagle/Makefile
+++ b/board/ti/beagle/Makefile
@@ -5,5 +5,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y := $(BOARD).o
+obj-y := beagle.o
obj-$(CONFIG_STATUS_LED) += led.o
diff --git a/board/ti/evm/evm.c b/board/ti/evm/evm.c
index c71c218..81dd081 100644
--- a/board/ti/evm/evm.c
+++ b/board/ti/evm/evm.c
@@ -146,8 +146,8 @@
int misc_init_r(void)
{
-#ifdef CONFIG_DRIVER_OMAP34XX_I2C
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+#ifdef CONFIG_SYS_I2C_OMAP34XX
+ i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
#endif
#if defined(CONFIG_CMD_NET)
diff --git a/board/toradex/colibri_t20_iris/Makefile b/board/toradex/colibri_t20_iris/Makefile
index 7ca3fe5..ebeac70 100644
--- a/board/toradex/colibri_t20_iris/Makefile
+++ b/board/toradex/colibri_t20_iris/Makefile
@@ -4,9 +4,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-$(shell mkdir -p $(obj)../../nvidia/common)
-$(shell mkdir -p $(obj)../colibri_t20-common)
-
obj-y := ../../nvidia/common/board.o
obj-y += ../colibri_t20-common/colibri_t20-common.o
obj-y += colibri_t20_iris.o
diff --git a/board/tqc/tqm5200/Makefile b/board/tqc/tqm5200/Makefile
index 757f472..80c1eba 100644
--- a/board/tqc/tqm5200/Makefile
+++ b/board/tqc/tqm5200/Makefile
@@ -6,6 +6,3 @@
#
obj-y := tqm5200.o cmd_stk52xx.o cmd_tb5200.o cam5200_flash.o
-
-$(obj)cam5200_flash.o: cam5200_flash.c
- $(CC) $(CFLAGS) -c -o $@ $<
diff --git a/board/tqc/tqm8260/Makefile b/board/tqc/tqm8260/Makefile
index dc4a528..6b8573d 100644
--- a/board/tqc/tqm8260/Makefile
+++ b/board/tqc/tqm8260/Makefile
@@ -5,8 +5,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../tqm8xx/)
-endif
-
obj-y = tqm8260.o ../tqm8xx/load_sernum_ethaddr.o
diff --git a/board/tqc/tqm8272/Makefile b/board/tqc/tqm8272/Makefile
index 09af765..8bf0241 100644
--- a/board/tqc/tqm8272/Makefile
+++ b/board/tqc/tqm8272/Makefile
@@ -5,8 +5,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../tqm8xx/)
-endif
-
obj-y = tqm8272.o ../tqm8xx/load_sernum_ethaddr.o nand.o
diff --git a/board/tqc/tqm8xx/u-boot.lds b/board/tqc/tqm8xx/u-boot.lds
index cbfc94f..b77ae56 100644
--- a/board/tqc/tqm8xx/u-boot.lds
+++ b/board/tqc/tqm8xx/u-boot.lds
@@ -18,13 +18,13 @@
arch/powerpc/cpu/mpc8xx/start.o (.text*)
arch/powerpc/cpu/mpc8xx/traps.o (.text*)
- arch/powerpc/cpu/mpc8xx/libmpc8xx.o (.text*)
- arch/powerpc/lib/libpowerpc.o (.text*)
- board/tqc/tqm8xx/libtqm8xx.o (.text*)
- disk/libdisk.o (.text*)
- drivers/net/libnet.o (.text*)
- drivers/libdrivers.o (.text.pcmcia_on)
- drivers/libdrivers.o (.text.pcmcia_hardware_enable)
+ arch/powerpc/cpu/mpc8xx/built-in.o (.text*)
+ arch/powerpc/lib/built-in.o (.text*)
+ board/tqc/tqm8xx/built-in.o (.text*)
+ disk/built-in.o (.text*)
+ drivers/net/built-in.o (.text*)
+ drivers/built-in.o (.text.pcmcia_on)
+ drivers/built-in.o (.text.pcmcia_hardware_enable)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o (.ppcenv*)
diff --git a/board/vpac270/u-boot-spl.lds b/board/vpac270/u-boot-spl.lds
index 08c78b3..02d107c 100644
--- a/board/vpac270/u-boot-spl.lds
+++ b/board/vpac270/u-boot-spl.lds
@@ -20,8 +20,8 @@
.text.0 :
{
arch/arm/cpu/pxa/start.o (.text*)
- board/vpac270/libvpac270.o (.text*)
- drivers/mtd/onenand/libonenand.o (.text*)
+ board/vpac270/built-in.o (.text*)
+ drivers/mtd/onenand/built-in.o (.text*)
}
diff --git a/board/xes/xpedite517x/ddr.c b/board/xes/xpedite517x/ddr.c
index f48c02f..fd602ea 100644
--- a/board/xes/xpedite517x/ddr.c
+++ b/board/xes/xpedite517x/ddr.c
@@ -7,8 +7,8 @@
#include <common.h>
#include <i2c.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
void get_spd(ddr2_spd_eeprom_t *spd, u8 i2c_address)
{
diff --git a/board/xes/xpedite517x/xpedite517x.c b/board/xes/xpedite517x/xpedite517x.c
index 1782042..b7ad349 100644
--- a/board/xes/xpedite517x/xpedite517x.c
+++ b/board/xes/xpedite517x/xpedite517x.c
@@ -6,7 +6,7 @@
#include <common.h>
#include <asm/processor.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/mmu.h>
#include <asm/io.h>
#include <fdt_support.h>
diff --git a/board/xes/xpedite520x/ddr.c b/board/xes/xpedite520x/ddr.c
index 3671cb8..5c5eadc 100644
--- a/board/xes/xpedite520x/ddr.c
+++ b/board/xes/xpedite520x/ddr.c
@@ -9,8 +9,8 @@
#include <common.h>
#include <i2c.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
{
diff --git a/board/xes/xpedite537x/ddr.c b/board/xes/xpedite537x/ddr.c
index f41ae73..56b5a18 100644
--- a/board/xes/xpedite537x/ddr.c
+++ b/board/xes/xpedite537x/ddr.c
@@ -8,8 +8,8 @@
#include <common.h>
#include <i2c.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
void get_spd(ddr2_spd_eeprom_t *spd, u8 i2c_address)
{
diff --git a/board/xes/xpedite550x/ddr.c b/board/xes/xpedite550x/ddr.c
index 9fc6f04..0c0605e 100644
--- a/board/xes/xpedite550x/ddr.c
+++ b/board/xes/xpedite550x/ddr.c
@@ -8,8 +8,8 @@
#include <common.h>
#include <i2c.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
void get_spd(ddr3_spd_eeprom_t *spd, u8 i2c_address)
{
diff --git a/board/xilinx/ppc405-generic/Makefile b/board/xilinx/ppc405-generic/Makefile
index 1562f17..c9da870 100644
--- a/board/xilinx/ppc405-generic/Makefile
+++ b/board/xilinx/ppc405-generic/Makefile
@@ -9,8 +9,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../../xilinx/ppc405-generic)
-endif
-
obj-y += ../../xilinx/ppc405-generic/xilinx_ppc405_generic.o
diff --git a/board/xilinx/ppc440-generic/Makefile b/board/xilinx/ppc440-generic/Makefile
index b2227c5..0acd95d 100644
--- a/board/xilinx/ppc440-generic/Makefile
+++ b/board/xilinx/ppc440-generic/Makefile
@@ -9,9 +9,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../../xilinx/ppc440-generic)
-endif
-
obj-y += ../../xilinx/ppc440-generic/xilinx_ppc440_generic.o
extra-y += ../../xilinx/ppc440-generic/init.o
diff --git a/boards.cfg b/boards.cfg
index c97b41a..2128996 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -489,10 +489,10 @@
Active m68k mcf547x_8x - freescale m548xevb M5485GFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=4,SYS_DRAMSZ=64 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Active m68k mcf547x_8x - freescale m548xevb M5485HFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Active microblaze microblaze - xilinx microblaze-generic microblaze-generic - Michal Simek <monstr@monstr.eu>
-Active mips mips32 - - qemu-malta qemu_malta qemu-malta:MIPS32,SYS_BIG_ENDIAN -
-Active mips mips32 - - qemu-malta qemu_maltael qemu-malta:MIPS32,SYS_LITTLE_ENDIAN -
Active mips mips32 - - qemu-mips qemu_mips qemu-mips:SYS_BIG_ENDIAN Vlad Lungu <vlad.lungu@windriver.com>
Active mips mips32 - - qemu-mips qemu_mipsel qemu-mips:SYS_LITTLE_ENDIAN -
+Active mips mips32 - imgtec malta malta malta:MIPS32,SYS_BIG_ENDIAN Paul Burton <paul.burton@imgtec.com>
+Active mips mips32 - imgtec malta maltael malta:MIPS32,SYS_LITTLE_ENDIAN Paul Burton <paul.burton@imgtec.com>
Active mips mips32 - micronas vct vct_platinum vct:VCT_PLATINUM -
Active mips mips32 - micronas vct vct_platinum_onenand vct:VCT_PLATINUM,VCT_ONENAND -
Active mips mips32 - micronas vct vct_platinum_onenand_small vct:VCT_PLATINUM,VCT_ONENAND,VCT_SMALL_IMAGE -
@@ -639,7 +639,6 @@
Active powerpc mpc824x - - linkstation linkstation_HGLAN linkstation:HGLAN=1 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Active powerpc mpc824x - - musenki MUSENKI - Jim Thompson <jim@musenki.com>
Active powerpc mpc824x - - mvblue MVBLUE - -
-Active powerpc mpc824x - - pn62 PN62 - Wolfgang Grandegger <wg@denx.de>
Active powerpc mpc824x - - sandpoint Sandpoint8240 - Wolfgang Denk <wd@denx.de>
Active powerpc mpc824x - - sandpoint Sandpoint8245 - Jim Thompson <jim@musenki.com>
Active powerpc mpc824x - etin - debris - Sangmoon Kim <dogoil@etinsys.com>
@@ -970,7 +969,14 @@
Active powerpc mpc85xx - freescale t4qds T4240QDS_SDCARD T4240QDS:PPC_T4240,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 -
Active powerpc mpc85xx - freescale t4qds T4240QDS_SPIFLASH T4240QDS:PPC_T4240,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 -
Active powerpc mpc85xx - freescale t4qds T4240QDS_SRIO_PCIE_BOOT T4240QDS:PPC_T4240,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 -
-Active powerpc mpc85xx - freescale t1040qds T1040QDS T1040QDS:PPC_T1040 Naveen Burmi <NaveenBurmi@freescale.com>
+Active powerpc mpc85xx - freescale t1040qds T1040QDS T1040QDS:PPC_T1040 Poonam Aggrwal <poonam.aggrwal@freescale.com>
+Active powerpc mpc85xx - freescale t104xrdb T1040RDB T1040RDB:PPC_T1040 Poonam Aggrwal <poonam.aggrwal@freescale.com>
+Active powerpc mpc85xx - freescale t104xrdb T1042RDB_PI T1042RDB_PI:PPC_T1042 Poonam Aggrwal <poonam.aggrwal@freescale.com>
+Active powerpc mpc85xx - freescale t2080qds T2080QDS T2080QDS:PPC_T2080
+Active powerpc mpc85xx - freescale t2080qds T2080QDS_SDCARD T2080QDS:PPC_T2080,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000
+Active powerpc mpc85xx - freescale t2080qds T2080QDS_SPIFLASH T2080QDS:PPC_T2080,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
+Active powerpc mpc85xx - freescale t2080qds T2080QDS_NAND T2080QDS:PPC_T2080,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000
+Active powerpc mpc85xx - freescale t2080qds T2080QDS_SRIO_PCIE_BOOT T2080QDS:PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000
Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD controlcenterd:36BIT,SDCARD Dirk Eibach <eibach@gdsys.de>
Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD_DEVELOP controlcenterd:36BIT,SDCARD,DEVELOP Dirk Eibach <eibach@gdsys.de>
Active powerpc mpc85xx - gdsys p1022 controlcenterd_TRAILBLAZER controlcenterd:TRAILBLAZER,SPIFLASH Dirk Eibach <eibach@gdsys.de>
diff --git a/common/Makefile b/common/Makefile
index 32acbf9..74404be 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -232,14 +232,11 @@
CPPFLAGS += -I..
-$(obj)env_embedded.o: $(src)env_embedded.c $(obj)../tools/envcrc
+$(obj)env_embedded.o: $(src)env_embedded.c
$(CC) $(AFLAGS) -Wa,--no-warn \
-DENV_CRC=$(shell $(obj)../tools/envcrc) \
-c -o $@ $(src)env_embedded.c
-$(obj)../tools/envcrc:
- $(MAKE) -C ../tools
-
# SEE README.arm-unaligned-accesses
$(obj)hush.o: CFLAGS += $(PLATFORM_NO_UNALIGNED)
$(obj)fdt_support.o: CFLAGS += $(PLATFORM_NO_UNALIGNED)
diff --git a/common/cmd_eeprom.c b/common/cmd_eeprom.c
index ef694d8..02539c4 100644
--- a/common/cmd_eeprom.c
+++ b/common/cmd_eeprom.c
@@ -161,7 +161,7 @@
#if defined(CONFIG_SPI) && !defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
spi_read (addr, alen, buffer, len);
#else
- if (i2c_read (addr[0], offset, alen-1, buffer, len) != 0)
+ if (i2c_read (addr[0], addr[1], alen-1, buffer, len) != 0)
rcode = 1;
#endif
buffer += len;
@@ -339,7 +339,7 @@
/* Write is enabled ... now write eeprom value.
*/
#endif
- if (i2c_write (addr[0], offset, alen-1, buffer, len) != 0)
+ if (i2c_write (addr[0], addr[1], alen-1, buffer, len) != 0)
rcode = 1;
#endif
diff --git a/common/cmd_mdio.c b/common/cmd_mdio.c
index 65a1f10..fb13d05 100644
--- a/common/cmd_mdio.c
+++ b/common/cmd_mdio.c
@@ -41,9 +41,11 @@
return 0;
}
-static int mdio_write_ranges(struct mii_dev *bus, int addrlo,
+static int mdio_write_ranges(struct phy_device *phydev, struct mii_dev *bus,
+ int addrlo,
int addrhi, int devadlo, int devadhi,
- int reglo, int reghi, unsigned short data)
+ int reglo, int reghi, unsigned short data,
+ int extended)
{
int addr, devad, reg;
int err = 0;
@@ -51,7 +53,12 @@
for (addr = addrlo; addr <= addrhi; addr++) {
for (devad = devadlo; devad <= devadhi; devad++) {
for (reg = reglo; reg <= reghi; reg++) {
- err = bus->write(bus, addr, devad, reg, data);
+ if (!extended)
+ err = bus->write(bus, addr, devad,
+ reg, data);
+ else
+ err = phydev->drv->writeext(phydev,
+ addr, devad, reg, data);
if (err)
goto err_out;
@@ -63,9 +70,10 @@
return err;
}
-static int mdio_read_ranges(struct mii_dev *bus, int addrlo,
+static int mdio_read_ranges(struct phy_device *phydev, struct mii_dev *bus,
+ int addrlo,
int addrhi, int devadlo, int devadhi,
- int reglo, int reghi)
+ int reglo, int reghi, int extended)
{
int addr, devad, reg;
@@ -77,7 +85,12 @@
for (reg = reglo; reg <= reghi; reg++) {
int val;
- val = bus->read(bus, addr, devad, reg);
+ if (!extended)
+ val = bus->read(bus, addr, devad, reg);
+ else
+ val = phydev->drv->readext(phydev, addr,
+ devad, reg);
+
if (val < 0) {
printf("Error\n");
@@ -126,9 +139,10 @@
}
static int extract_phy_range(char *const argv[], int argc, struct mii_dev **bus,
+ struct phy_device **phydev,
int *addrlo, int *addrhi)
{
- struct phy_device *phydev;
+ struct phy_device *dev = *phydev;
if ((argc < 1) || (argc > 2))
return -1;
@@ -154,11 +168,11 @@
* device by the given name. If none are found, we call
* extract_range() on the string, and see if it's an address range.
*/
- phydev = mdio_phydev_for_ethname(argv[0]);
+ dev = mdio_phydev_for_ethname(argv[0]);
- if (phydev) {
- *addrlo = *addrhi = phydev->addr;
- *bus = phydev->bus;
+ if (dev) {
+ *addrlo = *addrhi = dev->addr;
+ *bus = dev->bus;
return 0;
}
@@ -175,6 +189,8 @@
unsigned short data;
int pos = argc - 1;
struct mii_dev *bus;
+ struct phy_device *phydev = NULL;
+ int extended = 0;
if (argc < 2)
return CMD_RET_USAGE;
@@ -197,6 +213,29 @@
if (flag & CMD_FLAG_REPEAT)
op[0] = last_op[0];
+ if (strlen(argv[1]) > 1) {
+ op[1] = argv[1][1];
+ if (op[1] == 'x') {
+ phydev = mdio_phydev_for_ethname(argv[2]);
+
+ if (phydev) {
+ addrlo = phydev->addr;
+ addrhi = addrlo;
+ bus = phydev->bus;
+ extended = 1;
+ } else {
+ return -1;
+ }
+
+ if (!phydev->drv ||
+ (!phydev->drv->writeext && (op[0] == 'w')) ||
+ (!phydev->drv->readext && (op[0] == 'r'))) {
+ puts("PHY does not have extended functions\n");
+ return -1;
+ }
+ }
+ }
+
switch (op[0]) {
case 'w':
if (pos > 1)
@@ -210,7 +249,7 @@
default:
if (pos > 1)
if (extract_phy_range(&(argv[2]), pos - 1, &bus,
- &addrlo, &addrhi))
+ &phydev, &addrlo, &addrhi))
return -1;
break;
@@ -227,13 +266,13 @@
switch (op[0]) {
case 'w':
- mdio_write_ranges(bus, addrlo, addrhi, devadlo, devadhi,
- reglo, reghi, data);
+ mdio_write_ranges(phydev, bus, addrlo, addrhi, devadlo, devadhi,
+ reglo, reghi, data, extended);
break;
case 'r':
- mdio_read_ranges(bus, addrlo, addrhi, devadlo, devadhi,
- reglo, reghi);
+ mdio_read_ranges(phydev, bus, addrlo, addrhi, devadlo, devadhi,
+ reglo, reghi, extended);
break;
}
@@ -262,6 +301,10 @@
"read PHY's register at <devad>.<reg>\n"
"mdio write <phydev> [<devad>.]<reg> <data> - "
"write PHY's register at <devad>.<reg>\n"
+ "mdio rx <phydev> [<devad>.]<reg> - "
+ "read PHY's extended register at <devad>.<reg>\n"
+ "mdio wx <phydev> [<devad>.]<reg> <data> - "
+ "write PHY's extended register at <devad>.<reg>\n"
"<phydev> may be:\n"
" <busname> <addr>\n"
" <addr>\n"
diff --git a/common/cmd_mii.c b/common/cmd_mii.c
index d3dd6b1..b82a7ce 100644
--- a/common/cmd_mii.c
+++ b/common/cmd_mii.c
@@ -78,9 +78,9 @@
static const MII_field_desc_t reg_4_desc_tbl[] = {
{ 15, 15, 0x01, "next page able" },
- { 14, 14, 0x01, "reserved" },
+ { 14, 14, 0x01, "(reserved)" },
{ 13, 13, 0x01, "remote fault" },
- { 12, 12, 0x01, "reserved" },
+ { 12, 12, 0x01, "(reserved)" },
{ 11, 11, 0x01, "asymmetric pause" },
{ 10, 10, 0x01, "pause enable" },
{ 9, 9, 0x01, "100BASE-T4 able" },
diff --git a/common/hash.c b/common/hash.c
index 722c40b..872cd85 100644
--- a/common/hash.c
+++ b/common/hash.c
@@ -325,8 +325,8 @@
printf("CRC32 for %08lx ... %08lx ==> %08lx\n",
addr, addr + len - 1, crc);
- if (argc > 3) {
- ptr = (ulong *)simple_strtoul(argv[3], NULL, 16);
+ if (argc >= 3) {
+ ptr = (ulong *)simple_strtoul(argv[0], NULL, 16);
*ptr = crc;
}
}
diff --git a/common/lcd.c b/common/lcd.c
index 5dd7948..56bf067 100644
--- a/common/lcd.c
+++ b/common/lcd.c
@@ -386,8 +386,13 @@
/************************************************************************/
/* ** GENERIC Initialization Routines */
/************************************************************************/
-
-int lcd_get_size(int *line_length)
+/*
+ * With most lcd drivers the line length is set up
+ * by calculating it from panel_info parameters. Some
+ * drivers need to calculate the line length differently,
+ * so make the function weak to allow overriding it.
+ */
+__weak int lcd_get_size(int *line_length)
{
*line_length = (panel_info.vl_col * NBITS(panel_info.vl_bpix)) / 8;
return *line_length * panel_info.vl_row;
@@ -495,7 +500,6 @@
debug("[LCD] Using LCD frambuffer at %p\n", lcd_base);
lcd_get_size(&lcd_line_length);
- lcd_line_length = (panel_info.vl_col * NBITS(panel_info.vl_bpix)) / 8;
lcd_is_enabled = 1;
lcd_clear();
lcd_enable();
diff --git a/config.mk b/config.mk
index 3441387..d5b09a0 100644
--- a/config.mk
+++ b/config.mk
@@ -13,12 +13,6 @@
export SHELL
-ifeq ($(CONFIG_TPL_BUILD),y)
-SPL_BIN := u-boot-tpl
-else
-SPL_BIN := u-boot-spl
-endif
-
ifeq ($(CURDIR),$(SRCTREE))
dir :=
else
@@ -256,11 +250,16 @@
endif
endif
+# Sandbox needs the base flags and includes, so keep them around
+BASE_CPPFLAGS := $(CPPFLAGS)
+
ifneq ($(OBJTREE),$(SRCTREE))
-CPPFLAGS += -I$(OBJTREE)/include
+BASE_INCLUDE_DIRS := $(OBJTREE)/include
endif
-CPPFLAGS += -I$(TOPDIR)/include -I$(SRCTREE)/arch/$(ARCH)/include
+BASE_INCLUDE_DIRS += $(TOPDIR)/include $(SRCTREE)/arch/$(ARCH)/include
+
+CPPFLAGS += $(patsubst %, -I%, $(BASE_INCLUDE_DIRS))
CPPFLAGS += -fno-builtin -ffreestanding -nostdinc \
-isystem $(gccincdir) -pipe $(PLATFORM_CPPFLAGS)
diff --git a/doc/README.malta b/doc/README.malta
new file mode 100644
index 0000000..a495d02
--- /dev/null
+++ b/doc/README.malta
@@ -0,0 +1,16 @@
+MIPS Malta board
+
+How to flash using a MIPS Navigator Probe:
+
+ - Ensure that your Malta has jumper JP1 fitted. Without this jumper you will
+ be unable to flash your Malta using a Navigator Probe.
+
+ - Connect Navigator Console to your probe and Malta as usual.
+
+ - Within Navigator Console run the following commands:
+
+ source /path/to/u-boot/board/malta/flash-malta-boot.tcl
+ reset
+ flash-boot /path/to/u-boot/u-boot.bin
+
+ - You should now be able to reboot your Malta to a U-boot shell.
diff --git a/doc/README.nand b/doc/README.nand
index 913e9b5..b91f198 100644
--- a/doc/README.nand
+++ b/doc/README.nand
@@ -104,6 +104,16 @@
CONFIG_SYS_MAX_NAND_DEVICE
The maximum number of NAND devices you want to support.
+ CONFIG_SYS_NAND_MAX_ECCPOS
+ If specified, overrides the maximum number of ECC bytes
+ supported. Useful for reducing image size, especially with SPL.
+ This must be at least 48 if nand_base.c is used.
+
+ CONFIG_SYS_NAND_MAX_OOBFREE
+ If specified, overrides the maximum number of free OOB regions
+ supported. Useful for reducing image size, especially with SPL.
+ This must be at least 2 if nand_base.c is used.
+
CONFIG_SYS_NAND_MAX_CHIPS
The maximum number of NAND chips per device to be supported.
@@ -169,6 +179,59 @@
Please convert your driver even if you don't need the extra
flexibility, so that one day we can eliminate the old mechanism.
+
+ CONFIG_SYS_NAND_ONFI_DETECTION
+ Enables detection of ONFI compliant devices during probe.
+ And fetching device parameters flashed on device, by parsing
+ ONFI parameter page.
+
+ CONFIG_BCH
+ Enables software based BCH ECC algorithm present in lib/bch.c
+ This is used by SoC platforms which do not have built-in ELM
+ hardware engine required for BCH ECC correction.
+
+
+Platform specific options
+=========================
+ CONFIG_NAND_OMAP_GPMC
+ Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms.
+ GPMC controller is used for parallel NAND flash devices, and can
+ do ECC calculation (not ECC error detection) for HAM1, BCH4, BCH8
+ and BCH16 ECC algorithms.
+
+ CONFIG_NAND_OMAP_ELM
+ Enables omap_elm.c driver for OMAPx and AMxxxx platforms.
+ ELM controller is used for ECC error detection (not ECC calculation)
+ of BCH4, BCH8 and BCH16 ECC algorithms.
+ Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
+ thus such SoC platforms need to depend on software library for ECC error
+ detection. However ECC calculation on such plaforms would still be
+ done by GPMC controller.
+
+ CONFIG_NAND_OMAP_ECCSCHEME
+ On OMAP platforms, this CONFIG specifies NAND ECC scheme.
+ It can take following values:
+ OMAP_ECC_HAM1_CODE_SW
+ 1-bit Hamming code using software lib.
+ (for legacy devices only)
+ OMAP_ECC_HAM1_CODE_HW
+ 1-bit Hamming code using GPMC hardware.
+ (for legacy devices only)
+ OMAP_ECC_BCH4_CODE_HW_DETECTION_SW
+ 4-bit BCH code (unsupported)
+ OMAP_ECC_BCH4_CODE_HW
+ 4-bit BCH code (unsupported)
+ OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
+ 8-bit BCH code with
+ - ecc calculation using GPMC hardware engine,
+ - error detection using software library.
+ - requires CONFIG_BCH to enable software BCH library
+ (For legacy device which do not have ELM h/w engine)
+ OMAP_ECC_BCH8_CODE_HW
+ 8-bit BCH code with
+ - ecc calculation using GPMC hardware engine,
+ - error detection using ELM hardware engine.
+
NOTE:
=====
diff --git a/doc/README.omap3 b/doc/README.omap3
index 1fbe79d..a62c357 100644
--- a/doc/README.omap3
+++ b/doc/README.omap3
@@ -161,8 +161,7 @@
To enable hardware assisted BCH8 (8-bit BCH [Bose, Chaudhuri, Hocquenghem]) on
OMAP3 devices we can use the BCH library in lib/bch.c. To do so add CONFIG_BCH
-to enable the library and CONFIG_NAND_OMAP_BCH8 to to enable hardware assisted
-syndrom generation to your board config.
+and set CONFIG_NAND_OMAP_ECCSCHEME=5 (refer README.nand) for selecting BCH8_SW.
The NAND OOB layout is the same as in linux kernel, if the linux kernel BCH8
implementation for OMAP3 works for you so the u-boot version should also.
When you require the SPL to read with BCH8 there are two more configs to
diff --git a/doc/README.p1010rdb b/doc/README.p1010rdb
deleted file mode 100644
index 6b2b5ff..0000000
--- a/doc/README.p1010rdb
+++ /dev/null
@@ -1,198 +0,0 @@
-Overview
-=========
-The P1010RDB is a Freescale reference design board that hosts the P1010 SoC.
-
-The P1010 is a cost-effective, low-power, highly integrated host processor
-based on a Power Architecture e500v2 core (maximum core frequency 800/1000 MHz),
-that addresses the requirements of several routing, gateways, storage, consumer,
-and industrial applications. Applications of interest include the main CPUs and
-I/O processors in network attached storage (NAS), the voice over IP (VoIP)
-router/gateway, and wireless LAN (WLAN) and industrial controllers.
-
-The P1010RDB board features are as follows:
-Memory subsystem:
- - 1Gbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus)
- - 32 Mbyte NOR flash single-chip memory
- - 32 Mbyte NAND flash memory
- - 256 Kbit M24256 I2C EEPROM
- - 16 Mbyte SPI memory
- - I2C Board EEPROM 128x8 bit memory
- - SD/MMC connector to interface with the SD memory card
-Interfaces:
- - PCIe:
- - Lane0: x1 mini-PCIe slot
- - Lane1: x1 PCIe standard slot
- - SATA:
- - 1 internal SATA connector to 2.5" 160G SATA2 HDD
- - 1 eSATA connector to rear panel
- - 10/100/1000 BaseT Ethernet ports:
- - eTSEC1, RGMII: one 10/100/1000 port using Vitesse VSC8641XKO
- - eTSEC2, SGMII: one 10/100/1000 port using Vitesse VSC8221
- - eTSEC3, SGMII: one 10/100/1000 port using Vitesse VSC8221
- - USB 2.0 port:
- - x1 USB2.0 port: via an ULPI PHY to micro-AB connector
- - x1 USB2.0 poort via an internal PHY to micro-AB connector
- - FlexCAN ports:
- - x2 DB-9 female connectors for FlexCAN bus(revision 2.0B)
- interface;
- - DUART interface:
- - DUART interface: supports two UARTs up to 115200 bps for
- console display
- - J45 connectors are used for these 2 UART ports.
- - TDM
- - 2 FXS ports connected via an external SLIC to the TDM
- interface. SLIC is controllled via SPI.
- - 1 FXO port connected via a relay to FXS for switchover to
- POTS
-Board connectors:
- - Mini-ITX power supply connector
- - JTAG/COP for debugging
-IEEE Std. 1588 signals for test and measurement
-Real-time clock on I2C bus
-POR
- - support critical POR setting changed via switch on board
-PCB
- - 6-layer routing (4-layer signals, 2-layer power and ground)
-
-
-Serial Port Configuration on P1010RDB
-=====================================
-Configure the serial port of the attached computer with the following values:
- -Data rate: 115200 bps
- -Number of data bits: 8
- -Parity: None
- -Number of Stop bits: 1
- -Flow Control: Hardware/None
-
-
-Settings of DIP-switch
-======================
- SW4[1:4]= 1111 and SW6[4]=0 for boot from 16bit NOR flash
- SW4[1:4]= 1000 and SW6[4]=1 for boot from 8bit NAND flash
- SW4[1:4]= 0110 and SW6[4]=0 for boot from SPI flash
-Note: 1 stands for 'on', 0 stands for 'off'
-
-
-Setting of hwconfig
-===================
-If FlexCAN or TDM is needed, please set "fsl_p1010mux:tdm_can=can" or
-"fsl_p1010mux:tdm_can=tdm" explicitly in u-booot prompt as below for example:
-setenv hwconfig "fsl_p1010mux:tdm_can=tdm;usb1:dr_mode=host,phy_type=utmi"
-By default, don't set fsl_p1010mux:tdm_can, in this case, spi chip selection
-is set to spi-flash instead of to SLIC/TDM/DAC and tdm_can_sel is set to TDM
-instead of to CAN/UART1.
-
-
-Build and burn u-boot to NOR flash
-==================================
-1. Build u-boot.bin image
- export ARCH=powerpc
- export CROSS_COMPILE=/your_path/powerpc-linux-gnu-
- make P1010RDB_NOR
-
-2. Burn u-boot.bin into NOR flash
- => tftp $loadaddr $uboot
- => protect off eff80000 +$filesize
- => erase eff80000 +$filesize
- => cp.b $loadaddr eff80000 $filesize
-
-3. Check SW4[1:4]= 1111 and SW6[4]=0, then power on.
-
-
-Alternate NOR bank
-============================
-1. Burn u-boot.bin into alternate NOR bank
- => tftp $loadaddr $uboot
- => protect off eef80000 +$filesize
- => erase eef80000 +$filesize
- => cp.b $loadaddr eef80000 $filesize
-
-2. Switch to alternate NOR bank
- => mw.b ffb00009 1
- => reset
- or set SW1[8]= ON
-
-SW1[8]= OFF: Upper bank used for booting start
-SW1[8]= ON: Lower bank used for booting start
-CPLD NOR bank selection register address 0xFFB00009 Bit[0]:
-0 - boot from upper 4 sectors
-1 - boot from lower 4 sectors
-
-
-Build and burn u-boot to NAND flash
-===================================
-1. Build u-boot.bin image
- export ARCH=powerpc
- export CROSS_COMPILE=/your_path/powerpc-linux-gnu-
- make P1010RDB_NAND
-
-2. Burn u-boot-nand.bin into NAND flash
- => tftp $loadaddr $uboot-nand
- => nand erase 0 $filesize
- => nand write $loadaddr 0 $filesize
-
-3. Check SW4[1:4]= 1000 and SW6[4]=1, then power on.
-
-
-
-Build and burn u-boot to SPI flash
-==================================
-1. Build u-boot-spi.bin image
- make P1010RDB_SPIFLASH_config; make
- Boot up kernel with rootfs.ext2.gz.uboot.p1010rdb
- Download u-boot.bin to linux and you can find some config files
- under /usr/share such as config_xx.dat. Do below command:
- boot_format config_ddr3_1gb_p1010rdb_800M.dat u-boot.bin -spi \
- u-boot-spi.bin
- to generate u-boot-spi.bin.
-
-2. Burn u-boot-spi.bin into SPI flash
- => tftp $loadaddr $uboot-spi
- => sf erase 0 100000
- => sf write $loadaddr 0 $filesize
-
-3. Check SW4[1:4]= 0110 and SW6[4]=0, then power on.
-
-
-
-CPLD POR setting registers
-==========================
-1. Set POR switch selection register (addr 0xFFB00011) to 0.
-2. Write CPLD POR registers (BCSR0~BCSR3, addr 0xFFB00014~0xFFB00017) with
- proper values.
- If change boot ROM location to NOR or NAND flash, need write the IFC_CS0
- switch command by I2C.
-3. Send reset command.
- After reset, the new POR setting will be implemented.
-
-Two examples are given in below:
-Switch from NOR to NAND boot with default frequency:
- => i2c dev 0
- => i2c mw 18 1 f9
- => i2c mw 18 3 f0
- => mw.b ffb00011 0
- => mw.b ffb00017 1
- => reset
-Switch from NAND to NOR boot with Core/CCB/DDR (800/400/667 MHz):
- => i2c dev 0
- => i2c mw 18 1 f1
- => i2c mw 18 3 f0
- => mw.b ffb00011 0
- => mw.b ffb00014 2
- => mw.b ffb00015 5
- => mw.b ffb00016 3
- => mw.b ffb00017 f
- => reset
-
-
-Boot Linux from network using TFTP on P1010RDB
-==============================================
-Place uImage, p1010rdb.dtb and rootfs files in the TFTP disk area.
- => tftp 1000000 uImage
- => tftp 2000000 p1010rdb.dtb
- => tftp 3000000 rootfs.ext2.gz.uboot.p1010rdb
- => bootm 1000000 3000000 2000000
-
-
-Please contact your local field applications engineer or sales representative
-to obtain related documents, such as P1010-RDB User Guide for details.
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index a48ce7c..604de0c 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,6 +12,7 @@
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
omap730p2 arm arm926ejs - 2013-11-11
+pn62 powerpc mpc824x - 2013-11-11 Wolfgang Grandegger <wg@grandegger.com>
pdnb3 arm ixp 304db0b 2013-09-24 Stefan Roese <sr@denx.de>
scpu arm ixp 304db0b 2013-09-24 Stefan Roese <sr@denx.de>
omap1510inn arm arm925t 0610a16 2013-09-23 Kshitij Gupta <kshitij@ti.com>
@@ -103,3 +104,4 @@
PCIPPC2 powerpc MPC740/MPC750 7c9e89b 2013-02-07 Wolfgang Denk <wd@denx.de>
PCIPPC6 powerpc MPC740/MPC750 - - Wolfgang Denk <wd@denx.de>
omap2420h4 arm omap24xx - 2013-06-04 Richard Woodruff <r-woodruff2@ti.com>
+eNET x86 x86 7e8c53d 2013-02-14 Graeme Russ <graeme.russ@gmail.com>
diff --git a/drivers/Makefile b/drivers/Makefile
index 9cec2ba..5d03f37 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -1,8 +1,8 @@
-obj-y += bios_emulator/
+obj-$(CONFIG_BIOSEMU) += bios_emulator/
obj-y += block/
obj-$(CONFIG_BOOTCOUNT_LIMIT) += bootcount/
obj-y += crypto/
-obj-y += fpga/
+obj-$(CONFIG_FPGA) += fpga/
obj-y += hwmon/
obj-y += misc/
obj-y += pcmcia/
@@ -13,3 +13,4 @@
obj-y += twserial/
obj-y += video/
obj-y += watchdog/
+obj-$(CONFIG_QE) += qe/
diff --git a/drivers/bios_emulator/Makefile b/drivers/bios_emulator/Makefile
index dd42e0f..52a2ceb 100644
--- a/drivers/bios_emulator/Makefile
+++ b/drivers/bios_emulator/Makefile
@@ -1,8 +1,6 @@
X86DIR = x86emu
-$(shell mkdir -p $(obj)$(X86DIR))
-
-obj-$(CONFIG_BIOSEMU) = atibios.o biosemu.o besys.o bios.o \
+obj-y = atibios.o biosemu.o besys.o bios.o \
$(X86DIR)/decode.o \
$(X86DIR)/ops2.o \
$(X86DIR)/ops.o \
@@ -10,9 +8,8 @@
$(X86DIR)/sys.o \
$(X86DIR)/debug.o
-EXTRA_CFLAGS += -I. -I./include -I$(TOPDIR)/include \
+EXTRA_CFLAGS += -I. -I./include \
-D__PPC__ -D__BIG_ENDIAN__
CFLAGS += $(EXTRA_CFLAGS)
-HOSTCFLAGS += $(EXTRA_CFLAGS)
CPPFLAGS += $(EXTRA_CFLAGS)
diff --git a/drivers/ddr/fsl/Makefile b/drivers/ddr/fsl/Makefile
new file mode 100644
index 0000000..265204f
--- /dev/null
+++ b/drivers/ddr/fsl/Makefile
@@ -0,0 +1,34 @@
+#
+# Copyright 2008-2011 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License
+# Version 2 as published by the Free Software Foundation.
+#
+
+obj-$(CONFIG_SYS_FSL_DDR1) += main.o util.o ctrl_regs.o options.o \
+ lc_common_dimm_params.o
+
+obj-$(CONFIG_SYS_FSL_DDR2) += main.o util.o ctrl_regs.o options.o \
+ lc_common_dimm_params.o
+
+obj-$(CONFIG_SYS_FSL_DDR3) += main.o util.o ctrl_regs.o options.o \
+ lc_common_dimm_params.o
+ifdef CONFIG_DDR_SPD
+SPD := y
+endif
+ifdef CONFIG_SPD_EEPROM
+SPD := y
+endif
+ifdef SPD
+obj-$(CONFIG_SYS_FSL_DDR1) += ddr1_dimm_params.o
+obj-$(CONFIG_SYS_FSL_DDR2) += ddr2_dimm_params.o
+obj-$(CONFIG_SYS_FSL_DDR3) += ddr3_dimm_params.o
+endif
+
+obj-$(CONFIG_FSL_DDR_INTERACTIVE) += interactive.o
+obj-$(CONFIG_SYS_FSL_DDRC_GEN1) += mpc85xx_ddr_gen1.o
+obj-$(CONFIG_SYS_FSL_DDRC_GEN2) += mpc85xx_ddr_gen2.o
+obj-$(CONFIG_SYS_FSL_DDRC_GEN3) += mpc85xx_ddr_gen3.o
+obj-$(CONFIG_SYS_FSL_DDR_86XX) += mpc86xx_ddr.o
+obj-$(CONFIG_SYS_FSL_DDRC_ARM_GEN3) += arm_ddr_gen3.o
diff --git a/drivers/ddr/fsl/arm_ddr_gen3.c b/drivers/ddr/fsl/arm_ddr_gen3.c
new file mode 100644
index 0000000..bf11390
--- /dev/null
+++ b/drivers/ddr/fsl/arm_ddr_gen3.c
@@ -0,0 +1,213 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Derived from mpc85xx_ddr_gen3.c, removed all workarounds
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <fsl_ddr_sdram.h>
+#include <asm/processor.h>
+#include <fsl_immap.h>
+
+#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
+#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
+#endif
+
+
+/*
+ * regs has the to-be-set values for DDR controller registers
+ * ctrl_num is the DDR controller number
+ * step: 0 goes through the initialization in one pass
+ * 1 sets registers and returns before enabling controller
+ * 2 resumes from step 1 and continues to initialize
+ * Dividing the initialization to two steps to deassert DDR reset signal
+ * to comply with JEDEC specs for RDIMMs.
+ */
+void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
+ unsigned int ctrl_num, int step)
+{
+ unsigned int i, bus_width;
+ struct ccsr_ddr __iomem *ddr;
+ u32 temp_sdram_cfg;
+ u32 total_gb_size_per_controller;
+ int timeout;
+
+ switch (ctrl_num) {
+ case 0:
+ ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+ break;
+#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
+ case 1:
+ ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
+ break;
+#endif
+#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
+ case 2:
+ ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
+ break;
+#endif
+#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
+ case 3:
+ ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
+ break;
+#endif
+ default:
+ printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num);
+ return;
+ }
+
+ if (step == 2)
+ goto step2;
+
+ if (regs->ddr_eor)
+ out_be32(&ddr->eor, regs->ddr_eor);
+ for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+ if (i == 0) {
+ out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
+ out_be32(&ddr->cs0_config, regs->cs[i].config);
+ out_be32(&ddr->cs0_config_2, regs->cs[i].config_2);
+
+ } else if (i == 1) {
+ out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
+ out_be32(&ddr->cs1_config, regs->cs[i].config);
+ out_be32(&ddr->cs1_config_2, regs->cs[i].config_2);
+
+ } else if (i == 2) {
+ out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
+ out_be32(&ddr->cs2_config, regs->cs[i].config);
+ out_be32(&ddr->cs2_config_2, regs->cs[i].config_2);
+
+ } else if (i == 3) {
+ out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
+ out_be32(&ddr->cs3_config, regs->cs[i].config);
+ out_be32(&ddr->cs3_config_2, regs->cs[i].config_2);
+ }
+ }
+
+ out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3);
+ out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
+ out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
+ out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
+ out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
+ out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
+ out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
+ out_be32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3);
+ out_be32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4);
+ out_be32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5);
+ out_be32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6);
+ out_be32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7);
+ out_be32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8);
+ out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
+ out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
+ out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
+ out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
+ out_be32(&ddr->init_addr, regs->ddr_init_addr);
+ out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
+
+ out_be32(&ddr->timing_cfg_4, regs->timing_cfg_4);
+ out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5);
+ out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
+ out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
+#ifndef CONFIG_SYS_FSL_DDR_EMU
+ /*
+ * Skip these two registers if running on emulator
+ * because emulator doesn't have skew between bytes.
+ */
+
+ if (regs->ddr_wrlvl_cntl_2)
+ out_be32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2);
+ if (regs->ddr_wrlvl_cntl_3)
+ out_be32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3);
+#endif
+
+ out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
+ out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
+ out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
+ out_be32(&ddr->ddr_cdr1, regs->ddr_cdr1);
+ out_be32(&ddr->ddr_cdr2, regs->ddr_cdr2);
+ out_be32(&ddr->err_disable, regs->err_disable);
+ out_be32(&ddr->err_int_en, regs->err_int_en);
+ for (i = 0; i < 32; i++) {
+ if (regs->debug[i]) {
+ debug("Write to debug_%d as %08x\n", i + 1,
+ regs->debug[i]);
+ out_be32(&ddr->debug[i], regs->debug[i]);
+ }
+ }
+
+ /*
+ * For RDIMMs, JEDEC spec requires clocks to be stable before reset is
+ * deasserted. Clocks start when any chip select is enabled and clock
+ * control register is set. Because all DDR components are connected to
+ * one reset signal, this needs to be done in two steps. Step 1 is to
+ * get the clocks started. Step 2 resumes after reset signal is
+ * deasserted.
+ */
+ if (step == 1) {
+ udelay(200);
+ return;
+ }
+
+step2:
+ /* Set, but do not enable the memory */
+ temp_sdram_cfg = regs->ddr_sdram_cfg;
+ temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN);
+ out_be32(&ddr->sdram_cfg, temp_sdram_cfg);
+
+ /*
+ * 500 painful micro-seconds must elapse between
+ * the DDR clock setup and the DDR config enable.
+ * DDR2 need 200 us, and DDR3 need 500 us from spec,
+ * we choose the max, that is 500 us for all of case.
+ */
+ udelay(500);
+ asm volatile("dsb sy;isb");
+
+ /* Let the controller go */
+ temp_sdram_cfg = in_be32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
+ out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
+ asm volatile("dsb sy;isb");
+
+ total_gb_size_per_controller = 0;
+ for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+ if (!(regs->cs[i].config & 0x80000000))
+ continue;
+ total_gb_size_per_controller += 1 << (
+ ((regs->cs[i].config >> 14) & 0x3) + 2 +
+ ((regs->cs[i].config >> 8) & 0x7) + 12 +
+ ((regs->cs[i].config >> 0) & 0x7) + 8 +
+ 3 - ((regs->ddr_sdram_cfg >> 19) & 0x3) -
+ 26); /* minus 26 (count of 64M) */
+ }
+ if (regs->cs[0].config & 0x20000000) {
+ /* 2-way interleaving */
+ total_gb_size_per_controller <<= 1;
+ }
+ /*
+ * total memory / bus width = transactions needed
+ * transactions needed / data rate = seconds
+ * to add plenty of buffer, double the time
+ * For example, 2GB on 666MT/s 64-bit bus takes about 402ms
+ * Let's wait for 800ms
+ */
+ bus_width = 3 - ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK)
+ >> SDRAM_CFG_DBW_SHIFT);
+ timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
+ (get_ddr_freq(0) >> 20)) << 1;
+ total_gb_size_per_controller >>= 4; /* shift down to gb size */
+ debug("total %d GB\n", total_gb_size_per_controller);
+ debug("Need to wait up to %d * 10ms\n", timeout);
+
+ /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */
+ while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) &&
+ (timeout >= 0)) {
+ udelay(10000); /* throttle polling rate */
+ timeout--;
+ }
+
+ if (timeout <= 0)
+ printf("Waiting for D_INIT timeout. Memory may not work.\n");
+}
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
similarity index 96%
rename from arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
rename to drivers/ddr/fsl/ctrl_regs.c
index dcfc48a..6bf22cf 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -11,15 +11,17 @@
*/
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
-#include "ddr.h"
+#include <fsl_ddr.h>
+#include <fsl_immap.h>
+#include <asm/io.h>
-#define _DDR_ADDR CONFIG_SYS_MPC8xxx_DDR_ADDR
+#define _DDR_ADDR CONFIG_SYS_FSL_DDR_ADDR
static u32 fsl_ddr_get_version(void)
{
- ccsr_ddr_t *ddr;
+ struct ccsr_ddr __iomem *ddr;
u32 ver_major_minor_errata;
ddr = (void *)_DDR_ADDR;
@@ -68,9 +70,9 @@
{
int rtt;
-#if defined(CONFIG_FSL_DDR1)
+#if defined(CONFIG_SYS_FSL_DDR1)
rtt = 0;
-#elif defined(CONFIG_FSL_DDR2)
+#elif defined(CONFIG_SYS_FSL_DDR2)
rtt = 3;
#else
rtt = 0;
@@ -217,7 +219,7 @@
/* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */
-#if !defined(CONFIG_FSL_DDR1)
+#if !defined(CONFIG_SYS_FSL_DDR1)
static inline int avoid_odt_overlap(const dimm_params_t *dimm_params)
{
#if CONFIG_DIMM_SLOTS_PER_CTLR == 1
@@ -263,7 +265,7 @@
/* Mode register set cycle time (tMRD). */
unsigned char tmrd_mclk;
-#ifdef CONFIG_FSL_DDR3
+#ifdef CONFIG_SYS_FSL_DDR3
/*
* (tXARD and tXARDS). Empirical?
* The DDR3 spec has not tXARD,
@@ -302,7 +304,7 @@
pre_pd_exit_mclk = act_pd_exit_mclk;
taxpd_mclk = 1;
}
-#else /* CONFIG_FSL_DDR2 */
+#else /* CONFIG_SYS_FSL_DDR2 */
/*
* (tXARD and tXARDS). Empirical?
* tXARD = 2 for DDR2
@@ -323,20 +325,21 @@
| ((twrt_mclk & 0x3) << 28) /* WRT */
| ((trrt_mclk & 0x3) << 26) /* RRT */
| ((twwt_mclk & 0x3) << 24) /* WWT */
- | ((act_pd_exit_mclk & 0x7) << 20) /* ACT_PD_EXIT */
+ | ((act_pd_exit_mclk & 0xf) << 20) /* ACT_PD_EXIT */
| ((pre_pd_exit_mclk & 0xF) << 16) /* PRE_PD_EXIT */
| ((taxpd_mclk & 0xf) << 8) /* ODT_PD_EXIT */
- | ((tmrd_mclk & 0xf) << 0) /* MRS_CYC */
+ | ((tmrd_mclk & 0x1f) << 0) /* MRS_CYC */
);
debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
}
-#endif /* defined(CONFIG_FSL_DDR2) */
+#endif /* defined(CONFIG_SYS_FSL_DDR2) */
/* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */
static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr,
const memctl_options_t *popts,
const common_timing_params_t *common_dimm,
- unsigned int cas_latency)
+ unsigned int cas_latency,
+ unsigned int additive_latency)
{
/* Extended precharge to activate interval (tRP) */
unsigned int ext_pretoact = 0;
@@ -348,6 +351,8 @@
unsigned int ext_refrec;
/* Extended MCAS latency from READ cmd */
unsigned int ext_caslat = 0;
+ /* Extended additive latency */
+ unsigned int ext_add_lat = 0;
/* Extended last data to precharge interval (tWR) */
unsigned int ext_wrrec = 0;
/* Control Adjust */
@@ -357,6 +362,7 @@
ext_acttopre = picos_to_mclk(common_dimm->tras_ps) >> 4;
ext_acttorw = picos_to_mclk(common_dimm->trcd_ps) >> 4;
ext_caslat = (2 * cas_latency - 1) >> 4;
+ ext_add_lat = additive_latency >> 4;
ext_refrec = (picos_to_mclk(common_dimm->trfc_ps) - 8) >> 4;
/* ext_wrrec only deals with 16 clock and above, or 14 with OTF */
ext_wrrec = (picos_to_mclk(common_dimm->twr_ps) +
@@ -368,6 +374,7 @@
| ((ext_acttorw & 0x1) << 22)
| ((ext_refrec & 0x1F) << 16)
| ((ext_caslat & 0x3) << 12)
+ | ((ext_add_lat & 0x1) << 10)
| ((ext_wrrec & 0x1) << 8)
| ((cntl_adj & 0x7) << 0)
);
@@ -420,9 +427,9 @@
* 4.5 1000
* 5.0 5 1001
*/
-#if defined(CONFIG_FSL_DDR1)
+#if defined(CONFIG_SYS_FSL_DDR1)
caslat_ctrl = (cas_latency + 1) & 0x07;
-#elif defined(CONFIG_FSL_DDR2)
+#elif defined(CONFIG_SYS_FSL_DDR2)
caslat_ctrl = 2 * cas_latency - 1;
#else
/*
@@ -447,7 +454,7 @@
/*
* JEDEC has min requirement for tRRD
*/
-#if defined(CONFIG_FSL_DDR3)
+#if defined(CONFIG_SYS_FSL_DDR3)
if (acttoact_mclk < 4)
acttoact_mclk = 4;
#endif
@@ -455,10 +462,10 @@
/*
* JEDEC has some min requirements for tWTR
*/
-#if defined(CONFIG_FSL_DDR2)
+#if defined(CONFIG_SYS_FSL_DDR2)
if (wrtord_mclk < 2)
wrtord_mclk = 2;
-#elif defined(CONFIG_FSL_DDR3)
+#elif defined(CONFIG_SYS_FSL_DDR3)
if (wrtord_mclk < 4)
wrtord_mclk = 4;
#endif
@@ -504,7 +511,7 @@
add_lat_mclk = additive_latency;
cpo = popts->cpo_override;
-#if defined(CONFIG_FSL_DDR1)
+#if defined(CONFIG_SYS_FSL_DDR1)
/*
* This is a lie. It should really be 1, but if it is
* set to 1, bits overlap into the old controller's
@@ -512,7 +519,7 @@
* the HW will magically treat it as 1 for DDR 1. Oh Yea.
*/
wr_lat = 0;
-#elif defined(CONFIG_FSL_DDR2)
+#elif defined(CONFIG_SYS_FSL_DDR2)
wr_lat = cas_latency - 1;
#else
wr_lat = compute_cas_write_latency();
@@ -522,15 +529,13 @@
/*
* JEDEC has some min requirements for tRTP
*/
-#if defined(CONFIG_FSL_DDR2)
+#if defined(CONFIG_SYS_FSL_DDR2)
if (rd_to_pre < 2)
rd_to_pre = 2;
-#elif defined(CONFIG_FSL_DDR3)
+#elif defined(CONFIG_SYS_FSL_DDR3)
if (rd_to_pre < 4)
rd_to_pre = 4;
#endif
- if (additive_latency)
- rd_to_pre += additive_latency;
if (popts->otf_burst_chop_en)
rd_to_pre += 2; /* according to UM */
@@ -709,7 +714,7 @@
* * ({EXT_REFREC || REFREC} + 8 + 2)]}
* << DDR_SDRAM_INTERVAL[REFINT]
*/
-#if defined(CONFIG_FSL_DDR3)
+#if defined(CONFIG_SYS_FSL_DDR3)
obc_cfg = popts->otf_burst_chop_en;
#else
obc_cfg = 0;
@@ -738,7 +743,7 @@
d_init = 0;
#endif
-#if defined(CONFIG_FSL_DDR3)
+#if defined(CONFIG_SYS_FSL_DDR3)
md_en = popts->mirrored_dimm;
#endif
qd_en = popts->quad_rank_present ? 1 : 0;
@@ -771,7 +776,7 @@
unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */
unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */
-#if defined(CONFIG_FSL_DDR3)
+#if defined(CONFIG_SYS_FSL_DDR3)
int i;
unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */
unsigned int srt = 0; /* self-refresh temerature, normal range */
@@ -800,7 +805,7 @@
);
debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
-#ifdef CONFIG_FSL_DDR3
+#ifdef CONFIG_SYS_FSL_DDR3
if (unq_mrs_en) { /* unique mode registers are supported */
for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
if (popts->rtt_override)
@@ -861,7 +866,7 @@
debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval);
}
-#if defined(CONFIG_FSL_DDR3)
+#if defined(CONFIG_SYS_FSL_DDR3)
/* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
const memctl_options_t *popts,
@@ -1057,7 +1062,7 @@
}
}
-#else /* !CONFIG_FSL_DDR3 */
+#else /* !CONFIG_SYS_FSL_DDR3 */
/* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
@@ -1103,7 +1108,7 @@
unsigned int bt;
unsigned int bl; /* BL: Burst Length */
-#if defined(CONFIG_FSL_DDR2)
+#if defined(CONFIG_SYS_FSL_DDR2)
const unsigned int mclk_ps = get_memory_clk_period_ps();
#endif
dqs_en = !popts->dqs_config;
@@ -1132,15 +1137,15 @@
*/
pd = 0;
-#if defined(CONFIG_FSL_DDR1)
+#if defined(CONFIG_SYS_FSL_DDR1)
wr = 0; /* Historical */
-#elif defined(CONFIG_FSL_DDR2)
+#elif defined(CONFIG_SYS_FSL_DDR2)
wr = (common_dimm->twr_ps + mclk_ps - 1) / mclk_ps - 1;
#endif
dll_res = 0;
mode = 0;
-#if defined(CONFIG_FSL_DDR1)
+#if defined(CONFIG_SYS_FSL_DDR1)
if (1 <= cas_latency && cas_latency <= 4) {
unsigned char mode_caslat_table[4] = {
0x5, /* 1.5 clocks */
@@ -1152,7 +1157,7 @@
} else {
printf("Warning: unknown cas_latency %d\n", cas_latency);
}
-#elif defined(CONFIG_FSL_DDR2)
+#elif defined(CONFIG_SYS_FSL_DDR2)
caslat = cas_latency;
#endif
bt = 0;
@@ -1249,7 +1254,7 @@
unsigned int wwt = 0; /* Write-to-write turnaround for same CS */
unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */
-#if defined(CONFIG_FSL_DDR3)
+#if defined(CONFIG_SYS_FSL_DDR3)
if (popts->burst_length == DDR_BL8) {
/* We set BL/2 for fixed BL8 */
rrt = 0; /* BL/2 clocks */
@@ -1279,7 +1284,7 @@
unsigned int wodt_on = 0; /* Write to ODT on */
unsigned int wodt_off = 0; /* Write to ODT off */
-#if defined(CONFIG_FSL_DDR3)
+#if defined(CONFIG_SYS_FSL_DDR3)
/* rodt_on = timing_cfg_1[caslat] - timing_cfg_2[wrlat] + 1 */
rodt_on = cas_latency - ((ddr->timing_cfg_2 & 0x00780000) >> 19) + 1;
rodt_off = 4; /* 4 clocks */
@@ -1590,8 +1595,8 @@
if (cs_en) {
ddr->cs[i].bnds = (0
- | ((sa & 0xFFF) << 16)/* starting address MSB */
- | ((ea & 0xFFF) << 0) /* ending address MSB */
+ | ((sa & 0xffff) << 16) /* starting address */
+ | ((ea & 0xffff) << 0) /* ending address */
);
} else {
/* setting bnds to 0xffffffff for inactive CS */
@@ -1612,11 +1617,12 @@
set_ddr_eor(ddr, popts);
-#if !defined(CONFIG_FSL_DDR1)
+#if !defined(CONFIG_SYS_FSL_DDR1)
set_timing_cfg_0(ddr, popts, dimm_params);
#endif
- set_timing_cfg_3(ddr, popts, common_dimm, cas_latency);
+ set_timing_cfg_3(ddr, popts, common_dimm, cas_latency,
+ additive_latency);
set_timing_cfg_1(ddr, popts, common_dimm, cas_latency);
set_timing_cfg_2(ddr, popts, common_dimm,
cas_latency, additive_latency);
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr1_dimm_params.c b/drivers/ddr/fsl/ddr1_dimm_params.c
similarity index 98%
rename from arch/powerpc/cpu/mpc8xxx/ddr/ddr1_dimm_params.c
rename to drivers/ddr/fsl/ddr1_dimm_params.c
index f137fce..7df27b9 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr1_dimm_params.c
+++ b/drivers/ddr/fsl/ddr1_dimm_params.c
@@ -7,9 +7,9 @@
*/
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
-#include "ddr.h"
+#include <fsl_ddr.h>
/*
* Calculate the Density of each Physical Rank.
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c b/drivers/ddr/fsl/ddr2_dimm_params.c
similarity index 99%
rename from arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c
rename to drivers/ddr/fsl/ddr2_dimm_params.c
index e4d02e8..d865df7 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c
+++ b/drivers/ddr/fsl/ddr2_dimm_params.c
@@ -7,9 +7,9 @@
*/
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
-#include "ddr.h"
+#include <fsl_ddr.h>
/*
* Calculate the Density of each Physical Rank.
* Returned size is in bytes.
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c b/drivers/ddr/fsl/ddr3_dimm_params.c
similarity index 98%
rename from arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c
rename to drivers/ddr/fsl/ddr3_dimm_params.c
index 4c8645d..a4b8c10 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c
+++ b/drivers/ddr/fsl/ddr3_dimm_params.c
@@ -12,9 +12,9 @@
*/
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
-#include "ddr.h"
+#include <fsl_ddr.h>
/*
* Calculate the Density of each Physical Rank.
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c b/drivers/ddr/fsl/interactive.c
similarity index 98%
rename from arch/powerpc/cpu/mpc8xxx/ddr/interactive.c
rename to drivers/ddr/fsl/interactive.c
index 3b66112..ebf3ed6 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c
+++ b/drivers/ddr/fsl/interactive.c
@@ -14,9 +14,10 @@
#include <common.h>
#include <linux/ctype.h>
#include <asm/types.h>
+#include <asm/io.h>
-#include <asm/fsl_ddr_sdram.h>
-#include "ddr.h"
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr.h>
/* Option parameter Structures */
struct options_string {
@@ -402,7 +403,7 @@
CTRL_OPTIONS_CS(3, odt_rd_cfg),
CTRL_OPTIONS_CS(3, odt_wr_cfg),
#endif
-#if defined(CONFIG_FSL_DDR3)
+#if defined(CONFIG_SYS_FSL_DDR3)
CTRL_OPTIONS_CS(0, odt_rtt_norm),
CTRL_OPTIONS_CS(0, odt_rtt_wr),
#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
@@ -647,7 +648,7 @@
CTRL_OPTIONS_CS(3, odt_rd_cfg),
CTRL_OPTIONS_CS(3, odt_wr_cfg),
#endif
-#if defined(CONFIG_FSL_DDR3)
+#if defined(CONFIG_SYS_FSL_DDR3)
CTRL_OPTIONS_CS(0, odt_rtt_norm),
CTRL_OPTIONS_CS(0, odt_rtt_wr),
#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
@@ -710,7 +711,7 @@
print_option_table(options, n_opts, popts);
}
-#ifdef CONFIG_FSL_DDR1
+#ifdef CONFIG_SYS_FSL_DDR1
void ddr1_spd_dump(const ddr1_spd_eeprom_t *spd)
{
unsigned int i;
@@ -859,7 +860,7 @@
}
#endif
-#ifdef CONFIG_FSL_DDR2
+#ifdef CONFIG_SYS_FSL_DDR2
void ddr2_spd_dump(const ddr2_spd_eeprom_t *spd)
{
unsigned int i;
@@ -1051,7 +1052,7 @@
}
#endif
-#ifdef CONFIG_FSL_DDR3
+#ifdef CONFIG_SYS_FSL_DDR3
void ddr3_spd_dump(const ddr3_spd_eeprom_t *spd)
{
unsigned int i;
@@ -1246,11 +1247,11 @@
static inline void generic_spd_dump(const generic_spd_eeprom_t *spd)
{
-#if defined(CONFIG_FSL_DDR1)
+#if defined(CONFIG_SYS_FSL_DDR1)
ddr1_spd_dump(spd);
-#elif defined(CONFIG_FSL_DDR2)
+#elif defined(CONFIG_SYS_FSL_DDR2)
ddr2_spd_dump(spd);
-#elif defined(CONFIG_FSL_DDR3)
+#elif defined(CONFIG_SYS_FSL_DDR3)
ddr3_spd_dump(spd);
#endif
}
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c b/drivers/ddr/fsl/lc_common_dimm_params.c
similarity index 97%
rename from arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
rename to drivers/ddr/fsl/lc_common_dimm_params.c
index 332fe25..610318a 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
+++ b/drivers/ddr/fsl/lc_common_dimm_params.c
@@ -7,11 +7,11 @@
*/
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
-#include "ddr.h"
+#include <fsl_ddr.h>
-#if defined(CONFIG_FSL_DDR3)
+#if defined(CONFIG_SYS_FSL_DDR3)
static unsigned int
compute_cas_latency_ddr3(const dimm_params_t *dimm_params,
common_timing_params_t *outpdimm,
@@ -103,7 +103,7 @@
unsigned int temp1, temp2;
unsigned int additive_latency = 0;
-#if !defined(CONFIG_FSL_DDR3)
+#if !defined(CONFIG_SYS_FSL_DDR3)
const unsigned int mclk_ps = get_memory_clk_period_ps();
unsigned int lowest_good_caslat;
unsigned int not_ok;
@@ -265,7 +265,7 @@
if (temp1 != 0)
printf("ERROR: Mix different RDIMM detected!\n");
-#if defined(CONFIG_FSL_DDR3)
+#if defined(CONFIG_SYS_FSL_DDR3)
if (compute_cas_latency_ddr3(dimm_params, outpdimm, number_of_dimms))
return 1;
#else
@@ -386,7 +386,7 @@
}
outpdimm->highest_common_derated_caslat = temp1;
debug("highest common dereated CAS latency = %u\n", temp1);
-#endif /* #if defined(CONFIG_FSL_DDR3) */
+#endif /* #if defined(CONFIG_SYS_FSL_DDR3) */
/* Determine if all DIMMs ECC capable. */
temp1 = 1;
@@ -404,7 +404,7 @@
}
outpdimm->all_dimms_ecc_capable = temp1;
-#ifndef CONFIG_FSL_DDR3
+#ifndef CONFIG_SYS_FSL_DDR3
/* FIXME: move to somewhere else to validate. */
if (mclk_ps > tckmax_max_ps) {
printf("Warning: some of the installed DIMMs "
@@ -467,7 +467,7 @@
additive_latency = 0;
-#if defined(CONFIG_FSL_DDR2)
+#if defined(CONFIG_SYS_FSL_DDR2)
if (lowest_good_caslat < 4) {
additive_latency = (picos_to_mclk(trcd_ps) > lowest_good_caslat)
? picos_to_mclk(trcd_ps) - lowest_good_caslat : 0;
@@ -478,7 +478,7 @@
}
}
-#elif defined(CONFIG_FSL_DDR3)
+#elif defined(CONFIG_SYS_FSL_DDR3)
/*
* The system will not use the global auto-precharge mode.
* However, it uses the page mode, so we set AL=0
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c b/drivers/ddr/fsl/main.c
similarity index 98%
rename from arch/powerpc/cpu/mpc8xxx/ddr/main.c
rename to drivers/ddr/fsl/main.c
index 34d8bc3a..d0cd589 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/main.c
+++ b/drivers/ddr/fsl/main.c
@@ -14,17 +14,19 @@
#include <common.h>
#include <i2c.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_law.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr.h>
-#include "ddr.h"
+#ifdef CONFIG_PPC
+#include <asm/fsl_law.h>
void fsl_ddr_set_lawbar(
const common_timing_params_t *memctl_common_params,
unsigned int memctl_interleaved,
unsigned int ctrl_num);
-void fsl_ddr_set_intl3r(const unsigned int granule_size);
+#endif
+void fsl_ddr_set_intl3r(const unsigned int granule_size);
#if defined(SPD_EEPROM_ADDRESS) || \
defined(SPD_EEPROM_ADDRESS1) || defined(SPD_EEPROM_ADDRESS2) || \
defined(SPD_EEPROM_ADDRESS3) || defined(SPD_EEPROM_ADDRESS4)
@@ -253,7 +255,7 @@
debug("dbw_cap_adj[%d]=%d\n", i, dbw_cap_adj[i]);
}
- current_mem_base = 0ull;
+ current_mem_base = CONFIG_SYS_DDR_SDRAM_BASE;
total_mem = 0;
if (pinfo->memctl_opts[0].memctl_interleaving) {
rank_density = pinfo->dimm_params[0][0].rank_density >>
@@ -533,8 +535,8 @@
}
}
- total_mem = 1 + (((unsigned long long)max_end << 24ULL)
- | 0xFFFFFFULL);
+ total_mem = 1 + (((unsigned long long)max_end << 24ULL) |
+ 0xFFFFFFULL) - CONFIG_SYS_DDR_SDRAM_BASE;
}
return total_mem;
@@ -549,7 +551,9 @@
phys_size_t fsl_ddr_sdram(void)
{
unsigned int i;
+#ifdef CONFIG_PPC
unsigned int law_memctl = LAW_TRGT_IF_DDR_1;
+#endif
unsigned long long total_memory;
fsl_ddr_info_t info;
int deassert_reset;
@@ -621,6 +625,7 @@
}
}
+#ifdef CONFIG_PPC
/* program LAWs */
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
if (info.memctl_opts[i].memctl_interleaving) {
@@ -681,6 +686,7 @@
law_memctl, i);
}
}
+#endif
debug("total_memory by %s = %llu\n", __func__, total_memory);
diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen1.c b/drivers/ddr/fsl/mpc85xx_ddr_gen1.c
similarity index 91%
rename from arch/powerpc/cpu/mpc85xx/ddr-gen1.c
rename to drivers/ddr/fsl/mpc85xx_ddr_gen1.c
index 4dd8c0b..8dd4a91 100644
--- a/arch/powerpc/cpu/mpc85xx/ddr-gen1.c
+++ b/drivers/ddr/fsl/mpc85xx_ddr_gen1.c
@@ -8,7 +8,7 @@
#include <common.h>
#include <asm/io.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
@@ -18,7 +18,8 @@
unsigned int ctrl_num, int step)
{
unsigned int i;
- volatile ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
+ struct ccsr_ddr __iomem *ddr =
+ (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
if (ctrl_num != 0) {
printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
@@ -73,7 +74,8 @@
void
ddr_enable_ecc(unsigned int dram_size)
{
- volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR);
+ struct ccsr_ddr __iomem *ddr =
+ (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
dma_meminit(CONFIG_MEM_INIT_VALUE, dram_size);
diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen2.c b/drivers/ddr/fsl/mpc85xx_ddr_gen2.c
similarity index 95%
rename from arch/powerpc/cpu/mpc85xx/ddr-gen2.c
rename to drivers/ddr/fsl/mpc85xx_ddr_gen2.c
index 542bc84..988b4a4 100644
--- a/arch/powerpc/cpu/mpc85xx/ddr-gen2.c
+++ b/drivers/ddr/fsl/mpc85xx_ddr_gen2.c
@@ -9,7 +9,7 @@
#include <common.h>
#include <asm/io.h>
#include <asm/processor.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
@@ -19,7 +19,8 @@
unsigned int ctrl_num, int step)
{
unsigned int i;
- ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
+ struct ccsr_ddr __iomem *ddr =
+ (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
#if defined(CONFIG_SYS_FSL_ERRATUM_NMG_DDR120) && defined(CONFIG_MPC85xx)
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
similarity index 96%
rename from arch/powerpc/cpu/mpc85xx/ddr-gen3.c
rename to drivers/ddr/fsl/mpc85xx_ddr_gen3.c
index 1be51d3..9f04133 100644
--- a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
+++ b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
@@ -8,7 +8,7 @@
#include <common.h>
#include <asm/io.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/processor.h>
#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
@@ -29,7 +29,7 @@
unsigned int ctrl_num, int step)
{
unsigned int i, bus_width;
- volatile ccsr_ddr_t *ddr;
+ struct ccsr_ddr __iomem *ddr;
u32 temp_sdram_cfg;
u32 total_gb_size_per_controller;
int timeout;
@@ -42,21 +42,21 @@
switch (ctrl_num) {
case 0:
- ddr = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
+ ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
break;
-#if defined(CONFIG_SYS_MPC8xxx_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
+#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
case 1:
- ddr = (void *)CONFIG_SYS_MPC8xxx_DDR2_ADDR;
+ ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
break;
#endif
-#if defined(CONFIG_SYS_MPC8xxx_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
+#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
case 2:
- ddr = (void *)CONFIG_SYS_MPC8xxx_DDR3_ADDR;
+ ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
break;
#endif
-#if defined(CONFIG_SYS_MPC8xxx_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
+#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
case 3:
- ddr = (void *)CONFIG_SYS_MPC8xxx_DDR4_ADDR;
+ ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
break;
#endif
default:
diff --git a/arch/powerpc/cpu/mpc86xx/ddr-8641.c b/drivers/ddr/fsl/mpc86xx_ddr.c
similarity index 90%
rename from arch/powerpc/cpu/mpc86xx/ddr-8641.c
rename to drivers/ddr/fsl/mpc86xx_ddr.c
index 33a91f9..4551ed8 100644
--- a/arch/powerpc/cpu/mpc86xx/ddr-8641.c
+++ b/drivers/ddr/fsl/mpc86xx_ddr.c
@@ -8,7 +8,7 @@
#include <common.h>
#include <asm/io.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
@@ -18,14 +18,14 @@
unsigned int ctrl_num, int step)
{
unsigned int i;
- volatile ccsr_ddr_t *ddr;
+ struct ccsr_ddr __iomem *ddr;
switch (ctrl_num) {
case 0:
- ddr = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
+ ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
break;
case 1:
- ddr = (void *)CONFIG_SYS_MPC8xxx_DDR2_ADDR;
+ ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
break;
default:
printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
@@ -58,7 +58,7 @@
out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
- out_be32(&ddr->sdram_mode_cntl, regs->ddr_sdram_md_cntl);
+ out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/options.c b/drivers/ddr/fsl/options.c
similarity index 97%
rename from arch/powerpc/cpu/mpc8xxx/ddr/options.c
rename to drivers/ddr/fsl/options.c
index 1297845..4aafcce 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/options.c
+++ b/drivers/ddr/fsl/options.c
@@ -6,9 +6,9 @@
#include <common.h>
#include <hwconfig.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
-#include "ddr.h"
+#include <fsl_ddr.h>
/*
* Use our own stack based buffer before relocation to allow accessing longer
@@ -29,7 +29,7 @@
unsigned int odt_rtt_wr;
};
-#ifdef CONFIG_FSL_DDR3
+#ifdef CONFIG_SYS_FSL_DDR3
static const struct dynamic_odt single_Q[4] = {
{ /* cs0 */
FSL_DDR_ODT_NEVER,
@@ -259,7 +259,7 @@
DDR3_RTT_OFF
}
};
-#else /* CONFIG_FSL_DDR3 */
+#else /* CONFIG_SYS_FSL_DDR3 */
static const struct dynamic_odt single_Q[4] = {
{0, 0, 0, 0},
{0, 0, 0, 0},
@@ -507,7 +507,7 @@
unsigned int i;
char buffer[HWCONFIG_BUFFER_SIZE];
char *buf = NULL;
-#if defined(CONFIG_FSL_DDR3) || defined(CONFIG_FSL_DDR2)
+#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR2)
const struct dynamic_odt *pdodt = odt_unknown;
#endif
ulong ddr_freq;
@@ -519,7 +519,7 @@
if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
buf = buffer;
-#if defined(CONFIG_FSL_DDR3) || defined(CONFIG_FSL_DDR2)
+#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR2)
/* Chip select options. */
if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) {
switch (pdimm[0].n_ranks) {
@@ -585,7 +585,7 @@
/* Pick chip-select local options. */
for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
-#if defined(CONFIG_FSL_DDR3) || defined(CONFIG_FSL_DDR2)
+#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR2)
popts->cs_local_opts[i].odt_rd_cfg = pdodt[i].odt_rd_cfg;
popts->cs_local_opts[i].odt_wr_cfg = pdodt[i].odt_wr_cfg;
popts->cs_local_opts[i].odt_rtt_norm = pdodt[i].odt_rtt_norm;
@@ -655,9 +655,9 @@
* 0 for DDR1
* 1 for DDR2
*/
-#if defined(CONFIG_FSL_DDR1)
+#if defined(CONFIG_SYS_FSL_DDR1)
popts->dqs_config = 0;
-#elif defined(CONFIG_FSL_DDR2) || defined(CONFIG_FSL_DDR3)
+#elif defined(CONFIG_SYS_FSL_DDR2) || defined(CONFIG_SYS_FSL_DDR3)
popts->dqs_config = 1;
#endif
@@ -672,7 +672,7 @@
* presuming all dimms are similar
* 0 = 64-bit, 1 = 32-bit, 2 = 16-bit
*/
-#if defined(CONFIG_FSL_DDR1) || defined(CONFIG_FSL_DDR2)
+#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
if (pdimm[0].n_ranks != 0) {
if ((pdimm[0].data_width >= 64) && \
(pdimm[0].data_width <= 72))
@@ -703,7 +703,7 @@
popts->x4_en = (pdimm[0].device_width == 4) ? 1 : 0;
/* Choose burst length. */
-#if defined(CONFIG_FSL_DDR3)
+#if defined(CONFIG_SYS_FSL_DDR3)
#if defined(CONFIG_E500MC)
popts->otf_burst_chop_en = 0; /* on-the-fly burst chop disable */
popts->burst_length = DDR_BL8; /* Fixed 8-beat burst len */
@@ -722,7 +722,7 @@
#endif
/* Choose ddr controller address mirror mode */
-#if defined(CONFIG_FSL_DDR3)
+#if defined(CONFIG_SYS_FSL_DDR3)
popts->mirrored_dimm = pdimm[0].mirrored_dimm;
#endif
@@ -785,22 +785,22 @@
* FIXME: varies depending upon number of column addresses or data
* FIXME: width, was considering looking at pdimm->primary_sdram_width
*/
-#if defined(CONFIG_FSL_DDR1)
+#if defined(CONFIG_SYS_FSL_DDR1)
popts->tfaw_window_four_activates_ps = mclk_to_picos(1);
-#elif defined(CONFIG_FSL_DDR2)
+#elif defined(CONFIG_SYS_FSL_DDR2)
/*
* x4/x8; some datasheets have 35000
* x16 wide columns only? Use 50000?
*/
popts->tfaw_window_four_activates_ps = 37500;
-#elif defined(CONFIG_FSL_DDR3)
+#elif defined(CONFIG_SYS_FSL_DDR3)
popts->tfaw_window_four_activates_ps = pdimm[0].tfaw_ps;
#endif
popts->zq_en = 0;
popts->wrlvl_en = 0;
-#if defined(CONFIG_FSL_DDR3)
+#if defined(CONFIG_SYS_FSL_DDR3)
/*
* due to ddr3 dimm is fly-by topology
* we suggest to enable write leveling to
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/util.c b/drivers/ddr/fsl/util.c
similarity index 94%
rename from arch/powerpc/cpu/mpc8xxx/ddr/util.c
rename to drivers/ddr/fsl/util.c
index acfe1f0..0658261 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/util.c
+++ b/drivers/ddr/fsl/util.c
@@ -7,10 +7,14 @@
*/
#include <common.h>
+#ifdef CONFIG_PPC
#include <asm/fsl_law.h>
+#endif
#include <div64.h>
-#include "ddr.h"
+#include <fsl_ddr.h>
+#include <fsl_immap.h>
+#include <asm/io.h>
/* To avoid 64-bit full-divides, we factor this here */
#define ULL_2E12 2000000000000ULL
@@ -77,6 +81,7 @@
return get_memory_clk_period_ps() * mclk;
}
+#ifdef CONFIG_PPC
void
__fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params,
unsigned int law_memctl,
@@ -111,6 +116,7 @@
fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params,
unsigned int memctl_interleaved,
unsigned int ctrl_num);
+#endif
void fsl_ddr_set_intl3r(const unsigned int granule_size)
{
@@ -133,7 +139,8 @@
void board_add_ram_info(int use_default)
{
- ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR);
+ struct ccsr_ddr __iomem *ddr =
+ (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
#if defined(CONFIG_E6500) && (CONFIG_NUM_DDR_CONTROLLERS == 3)
u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004);
@@ -146,13 +153,13 @@
#if CONFIG_NUM_DDR_CONTROLLERS >= 2
if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) {
- ddr = (void __iomem *)CONFIG_SYS_MPC8xxx_DDR2_ADDR;
+ ddr = (void __iomem *)CONFIG_SYS_FSL_DDR2_ADDR;
sdram_cfg = in_be32(&ddr->sdram_cfg);
}
#endif
#if CONFIG_NUM_DDR_CONTROLLERS >= 3
if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) {
- ddr = (void __iomem *)CONFIG_SYS_MPC8xxx_DDR3_ADDR;
+ ddr = (void __iomem *)CONFIG_SYS_FSL_DDR3_ADDR;
sdram_cfg = in_be32(&ddr->sdram_cfg);
}
#endif
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index 4fcdf40..dfb2e7f 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -5,7 +5,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifdef CONFIG_FPGA
obj-y += fpga.o
obj-$(CONFIG_FPGA_SPARTAN2) += spartan2.o
obj-$(CONFIG_FPGA_SPARTAN3) += spartan3.o
@@ -19,4 +18,3 @@
obj-$(CONFIG_FPGA_CYCLON2) += cyclon2.o
obj-$(CONFIG_FPGA_STRATIX_II) += stratixII.o
endif
-endif
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index 5280bb3..553b519 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -11,21 +11,20 @@
obj-$(CONFIG_I2C_MVTWSI) += mvtwsi.o
obj-$(CONFIG_I2C_MV) += mv_i2c.o
obj-$(CONFIG_I2C_MXS) += mxs_i2c.o
-obj-$(CONFIG_DRIVER_OMAP1510_I2C) += omap1510_i2c.o
-obj-$(CONFIG_DRIVER_OMAP24XX_I2C) += omap24xx_i2c.o
-obj-$(CONFIG_DRIVER_OMAP34XX_I2C) += omap24xx_i2c.o
obj-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o
obj-$(CONFIG_DRIVER_S3C24X0_I2C) += s3c24x0_i2c.o
obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
obj-$(CONFIG_U8500_I2C) += u8500_i2c.o
-obj-$(CONFIG_SH_I2C) += sh_i2c.o
obj-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o
obj-$(CONFIG_SYS_I2C) += i2c_core.o
obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o
obj-$(CONFIG_SYS_I2C_FTI2C010) += fti2c010.o
obj-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o
+obj-$(CONFIG_SYS_I2C_OMAP24XX) += omap24xx_i2c.o
+obj-$(CONFIG_SYS_I2C_OMAP34XX) += omap24xx_i2c.o
obj-$(CONFIG_SYS_I2C_PPC4XX) += ppc4xx_i2c.o
obj-$(CONFIG_SYS_I2C_RCAR) += rcar_i2c.o
+obj-$(CONFIG_SYS_I2C_SH) += sh_i2c.o
obj-$(CONFIG_SYS_I2C_SOFT) += soft_i2c.o
obj-$(CONFIG_SYS_I2C_TEGRA) += tegra_i2c.o
-obj-$(CONFIG_ZYNQ_I2C) += zynq_i2c.o
+obj-$(CONFIG_SYS_I2C_ZYNQ) += zynq_i2c.o
diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c
index c2f0662..cb2ac04 100644
--- a/drivers/i2c/designware_i2c.c
+++ b/drivers/i2c/designware_i2c.c
@@ -151,7 +151,19 @@
*/
static void i2c_setaddress(unsigned int i2c_addr)
{
+ unsigned int enbl;
+
+ /* Disable i2c */
+ enbl = readl(&i2c_regs_p->ic_enable);
+ enbl &= ~IC_ENABLE_0B;
+ writel(enbl, &i2c_regs_p->ic_enable);
+
writel(i2c_addr, &i2c_regs_p->ic_tar);
+
+ /* Enable i2c */
+ enbl = readl(&i2c_regs_p->ic_enable);
+ enbl |= IC_ENABLE_0B;
+ writel(enbl, &i2c_regs_p->ic_enable);
}
/*
@@ -237,9 +249,6 @@
i2c_flush_rxfifo();
- /* Wait for read/write operation to complete on actual memory */
- udelay(10000);
-
return 0;
}
diff --git a/drivers/i2c/mxs_i2c.c b/drivers/i2c/mxs_i2c.c
index 46106b7..a298c95 100644
--- a/drivers/i2c/mxs_i2c.c
+++ b/drivers/i2c/mxs_i2c.c
@@ -150,6 +150,7 @@
{
struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
uint32_t tmp = 0;
+ int timeout = MXS_I2C_MAX_TIMEOUT;
int ret;
int i;
@@ -169,9 +170,17 @@
for (i = 0; i < len; i++) {
if (!(i & 3)) {
- while (readl(&i2c_regs->hw_i2c_queuestat) &
- I2C_QUEUESTAT_RD_QUEUE_EMPTY)
- ;
+ while (--timeout) {
+ tmp = readl(&i2c_regs->hw_i2c_queuestat);
+ if (!(tmp & I2C_QUEUESTAT_RD_QUEUE_EMPTY))
+ break;
+ }
+
+ if (!timeout) {
+ debug("MXS I2C: Failed receiving data!\n");
+ return -ETIMEDOUT;
+ }
+
tmp = readl(&i2c_regs->hw_i2c_queuedata);
}
buffer[i] = tmp & 0xff;
diff --git a/drivers/i2c/omap1510_i2c.c b/drivers/i2c/omap1510_i2c.c
deleted file mode 100644
index f91ee88..0000000
--- a/drivers/i2c/omap1510_i2c.c
+++ /dev/null
@@ -1,277 +0,0 @@
-/*
- * Basic I2C functions
- *
- * Copyright (c) 2003 Texas Instruments
- *
- * This package is free software; you can redistribute it and/or
- * modify it under the terms of the license found in the file
- * named COPYING that should have accompanied this file.
- *
- * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
- * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
- *
- * Author: Jian Zhang jzhang@ti.com, Texas Instruments
- *
- * Copyright (c) 2003 Wolfgang Denk, wd@denx.de
- * Rewritten to fit into the current U-Boot framework
- *
- */
-
-#include <common.h>
-
-static void wait_for_bb (void);
-static u16 wait_for_pin (void);
-
-void i2c_init (int speed, int slaveadd)
-{
- u16 scl;
-
- if (inw (I2C_CON) & I2C_CON_EN) {
- outw (0, I2C_CON);
- udelay (5000);
- }
-
- /* 12MHz I2C module clock */
- outw (0, I2C_PSC);
- outw (I2C_CON_EN, I2C_CON);
- outw (0, I2C_SYSTEST);
- /* have to enable intrrupts or OMAP i2c module doesn't work */
- outw (I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE |
- I2C_IE_NACK_IE | I2C_IE_AL_IE, I2C_IE);
- scl = (12000000 / 2) / speed - 6;
- outw (scl, I2C_SCLL);
- outw (scl, I2C_SCLH);
- /* own address */
- outw (slaveadd, I2C_OA);
- outw (0, I2C_CNT);
- udelay (1000);
-}
-
-static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value)
-{
- int i2c_error = 0;
- u16 status;
-
- /* wait until bus not busy */
- wait_for_bb ();
-
- /* one byte only */
- outw (1, I2C_CNT);
- /* set slave address */
- outw (devaddr, I2C_SA);
- /* no stop bit needed here */
- outw (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX, I2C_CON);
-
- status = wait_for_pin ();
-
- if (status & I2C_STAT_XRDY) {
- /* Important: have to use byte access */
- *(volatile u8 *) (I2C_DATA) = regoffset;
- udelay (20000);
- if (inw (I2C_STAT) & I2C_STAT_NACK) {
- i2c_error = 1;
- }
- } else {
- i2c_error = 1;
- }
-
- if (!i2c_error) {
- /* free bus, otherwise we can't use a combined transction */
- outw (0, I2C_CON);
- while (inw (I2C_STAT) || (inw (I2C_CON) & I2C_CON_MST)) {
- udelay (10000);
- /* Have to clear pending interrupt to clear I2C_STAT */
- inw (I2C_IV);
- }
-
- wait_for_bb ();
- /* set slave address */
- outw (devaddr, I2C_SA);
- /* read one byte from slave */
- outw (1, I2C_CNT);
- /* need stop bit here */
- outw (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP,
- I2C_CON);
-
- status = wait_for_pin ();
- if (status & I2C_STAT_RRDY) {
- *value = inw (I2C_DATA);
- udelay (20000);
- } else {
- i2c_error = 1;
- }
-
- if (!i2c_error) {
- outw (I2C_CON_EN, I2C_CON);
- while (inw (I2C_STAT)
- || (inw (I2C_CON) & I2C_CON_MST)) {
- udelay (10000);
- inw (I2C_IV);
- }
- }
- }
-
- return i2c_error;
-}
-
-static int i2c_write_byte (u8 devaddr, u8 regoffset, u8 value)
-{
- int i2c_error = 0;
- u16 status;
-
- /* wait until bus not busy */
- wait_for_bb ();
-
- /* two bytes */
- outw (2, I2C_CNT);
- /* set slave address */
- outw (devaddr, I2C_SA);
- /* stop bit needed here */
- outw (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
- I2C_CON_STP, I2C_CON);
-
- /* wait until state change */
- status = wait_for_pin ();
-
- if (status & I2C_STAT_XRDY) {
- /* send out two bytes */
- outw ((value << 8) + regoffset, I2C_DATA);
- /* must have enough delay to allow BB bit to go low */
- udelay (30000);
- if (inw (I2C_STAT) & I2C_STAT_NACK) {
- i2c_error = 1;
- }
- } else {
- i2c_error = 1;
- }
-
- if (!i2c_error) {
- outw (I2C_CON_EN, I2C_CON);
- while (inw (I2C_STAT) || (inw (I2C_CON) & I2C_CON_MST)) {
- udelay (1000);
- /* have to read to clear intrrupt */
- inw (I2C_IV);
- }
- }
-
- return i2c_error;
-}
-
-int i2c_probe (uchar chip)
-{
- int res = 1;
-
- if (chip == inw (I2C_OA)) {
- return res;
- }
-
- /* wait until bus not busy */
- wait_for_bb ();
-
- /* try to read one byte */
- outw (1, I2C_CNT);
- /* set slave address */
- outw (chip, I2C_SA);
- /* stop bit needed here */
- outw (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, I2C_CON);
- /* enough delay for the NACK bit set */
- udelay (2000);
- if (!(inw (I2C_STAT) & I2C_STAT_NACK)) {
- res = 0;
- } else {
- outw (inw (I2C_CON) | I2C_CON_STP, I2C_CON);
- udelay (20);
- wait_for_bb ();
- }
-
- return res;
-}
-
-int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len)
-{
- int i;
-
- if (alen > 1) {
- printf ("I2C read: addr len %d not supported\n", alen);
- return 1;
- }
-
- if (addr + len > 256) {
- printf ("I2C read: address out of range\n");
- return 1;
- }
-
- for (i = 0; i < len; i++) {
- if (i2c_read_byte (chip, addr + i, &buffer[i])) {
- printf ("I2C read: I/O error\n");
- i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
- return 1;
- }
- }
-
- return 0;
-}
-
-int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len)
-{
- int i;
-
- if (alen > 1) {
- printf ("I2C read: addr len %d not supported\n", alen);
- return 1;
- }
-
- if (addr + len > 256) {
- printf ("I2C read: address out of range\n");
- return 1;
- }
-
- for (i = 0; i < len; i++) {
- if (i2c_write_byte (chip, addr + i, buffer[i])) {
- printf ("I2C read: I/O error\n");
- i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
- return 1;
- }
- }
-
- return 0;
-}
-
-static void wait_for_bb (void)
-{
- int timeout = 10;
-
- while ((inw (I2C_STAT) & I2C_STAT_BB) && timeout--) {
- inw (I2C_IV);
- udelay (1000);
- }
-
- if (timeout <= 0) {
- printf ("timed out in wait_for_bb: I2C_STAT=%x\n",
- inw (I2C_STAT));
- }
-}
-
-static u16 wait_for_pin (void)
-{
- u16 status, iv;
- int timeout = 10;
-
- do {
- udelay (1000);
- status = inw (I2C_STAT);
- iv = inw (I2C_IV);
- } while (!iv &&
- !(status &
- (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY |
- I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK |
- I2C_STAT_AL)) && timeout--);
-
- if (timeout <= 0) {
- printf ("timed out in wait_for_pin: I2C_STAT=%x\n",
- inw (I2C_STAT));
- }
-
- return status;
-}
diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c
index ef38d71..3d38c03 100644
--- a/drivers/i2c/omap24xx_i2c.c
+++ b/drivers/i2c/omap24xx_i2c.c
@@ -35,6 +35,7 @@
*/
#include <common.h>
+#include <i2c.h>
#include <asm/arch/i2c.h>
#include <asm/io.h>
@@ -48,22 +49,14 @@
/* Absolutely safe for status update at 100 kHz I2C: */
#define I2C_WAIT 200
-static int wait_for_bb(void);
-static u16 wait_for_event(void);
-static void flush_fifo(void);
+static int wait_for_bb(struct i2c_adapter *adap);
+static struct i2c *omap24_get_base(struct i2c_adapter *adap);
+static u16 wait_for_event(struct i2c_adapter *adap);
+static void flush_fifo(struct i2c_adapter *adap);
-/*
- * For SPL boot some boards need i2c before SDRAM is initialised so force
- * variables to live in SRAM
- */
-static struct i2c __attribute__((section (".data"))) *i2c_base =
- (struct i2c *)I2C_DEFAULT_BASE;
-static unsigned int __attribute__((section (".data"))) bus_initialized[I2C_BUS_MAX] =
- { [0 ... (I2C_BUS_MAX-1)] = 0 };
-static unsigned int __attribute__((section (".data"))) current_bus = 0;
-
-void i2c_init(int speed, int slaveadd)
+static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
{
+ struct i2c *i2c_base = omap24_get_base(adap);
int psc, fsscll, fssclh;
int hsscll = 0, hssclh = 0;
u32 scll, sclh;
@@ -163,16 +156,15 @@
I2C_IE_NACK_IE | I2C_IE_AL_IE, &i2c_base->ie);
#endif
udelay(1000);
- flush_fifo();
+ flush_fifo(adap);
writew(0xFFFF, &i2c_base->stat);
writew(0, &i2c_base->cnt);
-
- if (gd->flags & GD_FLG_RELOC)
- bus_initialized[current_bus] = 1;
}
-static void flush_fifo(void)
-{ u16 stat;
+static void flush_fifo(struct i2c_adapter *adap)
+{
+ struct i2c *i2c_base = omap24_get_base(adap);
+ u16 stat;
/* note: if you try and read data when its not there or ready
* you get a bus error
@@ -192,8 +184,9 @@
* i2c_probe: Use write access. Allows to identify addresses that are
* write-only (like the config register of dual-port EEPROMs)
*/
-int i2c_probe(uchar chip)
+static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip)
{
+ struct i2c *i2c_base = omap24_get_base(adap);
u16 status;
int res = 1; /* default = fail */
@@ -201,7 +194,7 @@
return res;
/* Wait until bus is free */
- if (wait_for_bb())
+ if (wait_for_bb(adap))
return res;
/* No data transfer, slave addr only */
@@ -212,7 +205,7 @@
writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
I2C_CON_STP, &i2c_base->con);
- status = wait_for_event();
+ status = wait_for_event(adap);
if ((status & ~I2C_STAT_XRDY) == 0 || (status & I2C_STAT_AL)) {
/*
@@ -223,7 +216,7 @@
*/
if (status == I2C_STAT_XRDY)
printf("i2c_probe: pads on bus %d probably not configured (status=0x%x)\n",
- current_bus, status);
+ adap->hwadapnr, status);
goto pr_exit;
}
@@ -239,7 +232,7 @@
I2C_CON_STP, &i2c_base->con); /* STP */
}
pr_exit:
- flush_fifo();
+ flush_fifo(adap);
writew(0xFFFF, &i2c_base->stat);
writew(0, &i2c_base->cnt);
return res;
@@ -258,8 +251,10 @@
* or that do not need a register address at all (such as some clock
* distributors).
*/
-int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
+static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
+ int alen, uchar *buffer, int len)
{
+ struct i2c *i2c_base = omap24_get_base(adap);
int i2c_error = 0;
u16 status;
@@ -287,7 +282,7 @@
}
/* Wait until bus not busy */
- if (wait_for_bb())
+ if (wait_for_bb(adap))
return 1;
/* Zero, one or two bytes reg address (offset) */
@@ -308,12 +303,12 @@
#endif
/* Send register offset */
while (1) {
- status = wait_for_event();
+ status = wait_for_event(adap);
/* Try to identify bus that is not padconf'd for I2C */
if (status == I2C_STAT_XRDY) {
i2c_error = 2;
printf("i2c_read (addr phase): pads on bus %d probably not configured (status=0x%x)\n",
- current_bus, status);
+ adap->hwadapnr, status);
goto rd_exit;
}
if (status == 0 || status & I2C_STAT_NACK) {
@@ -348,7 +343,7 @@
/* Receive data */
while (1) {
- status = wait_for_event();
+ status = wait_for_event(adap);
/*
* Try to identify bus that is not padconf'd for I2C. This
* state could be left over from previous transactions if
@@ -357,7 +352,7 @@
if (status == I2C_STAT_XRDY) {
i2c_error = 2;
printf("i2c_read (data phase): pads on bus %d probably not configured (status=0x%x)\n",
- current_bus, status);
+ adap->hwadapnr, status);
goto rd_exit;
}
if (status == 0 || status & I2C_STAT_NACK) {
@@ -375,15 +370,17 @@
}
rd_exit:
- flush_fifo();
+ flush_fifo(adap);
writew(0xFFFF, &i2c_base->stat);
writew(0, &i2c_base->cnt);
return i2c_error;
}
/* i2c_write: Address (reg offset) may be 0, 1 or 2 bytes long. */
-int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
+static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
+ int alen, uchar *buffer, int len)
{
+ struct i2c *i2c_base = omap24_get_base(adap);
int i;
u16 status;
int i2c_error = 0;
@@ -415,7 +412,7 @@
}
/* Wait until bus not busy */
- if (wait_for_bb())
+ if (wait_for_bb(adap))
return 1;
/* Start address phase - will write regoffset + len bytes data */
@@ -428,12 +425,12 @@
while (alen) {
/* Must write reg offset (one or two bytes) */
- status = wait_for_event();
+ status = wait_for_event(adap);
/* Try to identify bus that is not padconf'd for I2C */
if (status == I2C_STAT_XRDY) {
i2c_error = 2;
printf("i2c_write: pads on bus %d probably not configured (status=0x%x)\n",
- current_bus, status);
+ adap->hwadapnr, status);
goto wr_exit;
}
if (status == 0 || status & I2C_STAT_NACK) {
@@ -455,7 +452,7 @@
}
/* Address phase is over, now write data */
for (i = 0; i < len; i++) {
- status = wait_for_event();
+ status = wait_for_event(adap);
if (status == 0 || status & I2C_STAT_NACK) {
i2c_error = 1;
printf("i2c_write: error waiting for data ACK (status=0x%x)\n",
@@ -474,7 +471,7 @@
}
wr_exit:
- flush_fifo();
+ flush_fifo(adap);
writew(0xFFFF, &i2c_base->stat);
writew(0, &i2c_base->cnt);
return i2c_error;
@@ -484,8 +481,9 @@
* Wait for the bus to be free by checking the Bus Busy (BB)
* bit to become clear
*/
-static int wait_for_bb(void)
+static int wait_for_bb(struct i2c_adapter *adap)
{
+ struct i2c *i2c_base = omap24_get_base(adap);
int timeout = I2C_TIMEOUT;
u16 stat;
@@ -514,8 +512,9 @@
* Wait for the I2C controller to complete current action
* and update status
*/
-static u16 wait_for_event(void)
+static u16 wait_for_event(struct i2c_adapter *adap)
{
+ struct i2c *i2c_base = omap24_get_base(adap);
u16 status;
int timeout = I2C_TIMEOUT;
@@ -540,7 +539,7 @@
* not been configured for I2C, and/or pull-ups are missing.
*/
printf("Check if pads/pull-ups of bus %d are properly configured\n",
- current_bus);
+ adap->hwadapnr);
writew(0xFFFF, &i2c_base->stat);
status = 0;
}
@@ -548,48 +547,93 @@
return status;
}
-int i2c_set_bus_num(unsigned int bus)
+static struct i2c *omap24_get_base(struct i2c_adapter *adap)
{
- if (bus >= I2C_BUS_MAX) {
- printf("Bad bus: %x\n", bus);
- return -1;
- }
-
- switch (bus) {
- default:
- bus = 0; /* Fall through */
+ switch (adap->hwadapnr) {
case 0:
- i2c_base = (struct i2c *)I2C_BASE1;
+ return (struct i2c *)I2C_BASE1;
break;
case 1:
- i2c_base = (struct i2c *)I2C_BASE2;
+ return (struct i2c *)I2C_BASE2;
break;
#if (I2C_BUS_MAX > 2)
case 2:
- i2c_base = (struct i2c *)I2C_BASE3;
+ return (struct i2c *)I2C_BASE3;
break;
#if (I2C_BUS_MAX > 3)
case 3:
- i2c_base = (struct i2c *)I2C_BASE4;
+ return (struct i2c *)I2C_BASE4;
break;
#if (I2C_BUS_MAX > 4)
case 4:
- i2c_base = (struct i2c *)I2C_BASE5;
+ return (struct i2c *)I2C_BASE5;
break;
#endif
#endif
#endif
+ default:
+ printf("wrong hwadapnr: %d\n", adap->hwadapnr);
+ break;
}
-
- current_bus = bus;
-
- if (!bus_initialized[current_bus])
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-
- return 0;
+ return NULL;
}
-int i2c_get_bus_num(void)
-{
- return (int) current_bus;
-}
+#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED1)
+#define CONFIG_SYS_OMAP24_I2C_SPEED1 CONFIG_SYS_OMAP24_I2C_SPEED
+#endif
+#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE1)
+#define CONFIG_SYS_OMAP24_I2C_SLAVE1 CONFIG_SYS_OMAP24_I2C_SLAVE
+#endif
+
+U_BOOT_I2C_ADAP_COMPLETE(omap24_0, omap24_i2c_init, omap24_i2c_probe,
+ omap24_i2c_read, omap24_i2c_write, NULL,
+ CONFIG_SYS_OMAP24_I2C_SPEED,
+ CONFIG_SYS_OMAP24_I2C_SLAVE,
+ 0)
+U_BOOT_I2C_ADAP_COMPLETE(omap24_1, omap24_i2c_init, omap24_i2c_probe,
+ omap24_i2c_read, omap24_i2c_write, NULL,
+ CONFIG_SYS_OMAP24_I2C_SPEED1,
+ CONFIG_SYS_OMAP24_I2C_SLAVE1,
+ 1)
+#if (I2C_BUS_MAX > 2)
+#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED2)
+#define CONFIG_SYS_OMAP24_I2C_SPEED2 CONFIG_SYS_OMAP24_I2C_SPEED
+#endif
+#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE2)
+#define CONFIG_SYS_OMAP24_I2C_SLAVE2 CONFIG_SYS_OMAP24_I2C_SLAVE
+#endif
+
+U_BOOT_I2C_ADAP_COMPLETE(omap24_2, omap24_i2c_init, omap24_i2c_probe,
+ omap24_i2c_read, omap24_i2c_write, NULL,
+ CONFIG_SYS_OMAP24_I2C_SPEED2,
+ CONFIG_SYS_OMAP24_I2C_SLAVE2,
+ 2)
+#if (I2C_BUS_MAX > 3)
+#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED3)
+#define CONFIG_SYS_OMAP24_I2C_SPEED3 CONFIG_SYS_OMAP24_I2C_SPEED
+#endif
+#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE3)
+#define CONFIG_SYS_OMAP24_I2C_SLAVE3 CONFIG_SYS_OMAP24_I2C_SLAVE
+#endif
+
+U_BOOT_I2C_ADAP_COMPLETE(omap24_3, omap24_i2c_init, omap24_i2c_probe,
+ omap24_i2c_read, omap24_i2c_write, NULL,
+ CONFIG_SYS_OMAP24_I2C_SPEED3,
+ CONFIG_SYS_OMAP24_I2C_SLAVE3,
+ 3)
+#if (I2C_BUS_MAX > 4)
+#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED4)
+#define CONFIG_SYS_OMAP24_I2C_SPEED4 CONFIG_SYS_OMAP24_I2C_SPEED
+#endif
+#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE4)
+#define CONFIG_SYS_OMAP24_I2C_SLAVE4 CONFIG_SYS_OMAP24_I2C_SLAVE
+#endif
+
+U_BOOT_I2C_ADAP_COMPLETE(omap24_4, omap24_i2c_init, omap24_i2c_probe,
+ omap24_i2c_read, omap24_i2c_write, NULL,
+ CONFIG_SYS_OMAP24_I2C_SPEED4,
+ CONFIG_SYS_OMAP24_I2C_SLAVE4,
+ 4)
+#endif
+#endif
+#endif
diff --git a/drivers/i2c/sh_i2c.c b/drivers/i2c/sh_i2c.c
index 808202c..cc19100 100644
--- a/drivers/i2c/sh_i2c.c
+++ b/drivers/i2c/sh_i2c.c
@@ -6,6 +6,7 @@
*/
#include <common.h>
+#include <i2c.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -22,8 +23,6 @@
};
#undef ureg
-static struct sh_i2c *base;
-
/* ICCR */
#define SH_I2C_ICCR_ICE (1 << 7)
#define SH_I2C_ICCR_RACK (1 << 6)
@@ -43,202 +42,165 @@
#define SH_I2C_ICIC_ICCHB8 (1 << 6)
#endif
+static const struct sh_i2c *i2c_dev[CONFIG_SYS_I2C_SH_NUM_CONTROLLERS] = {
+ (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE0,
+#ifdef CONFIG_SYS_I2C_SH_BASE1
+ (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE1,
+#endif
+#ifdef CONFIG_SYS_I2C_SH_BASE2
+ (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE2,
+#endif
+#ifdef CONFIG_SYS_I2C_SH_BASE3
+ (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE3,
+#endif
+#ifdef CONFIG_SYS_I2C_SH_BASE4
+ (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE4,
+#endif
+};
+
static u16 iccl, icch;
#define IRQ_WAIT 1000
-static void irq_dte(struct sh_i2c *base)
+static void sh_irq_dte(struct sh_i2c *dev)
{
int i;
- for (i = 0 ; i < IRQ_WAIT ; i++) {
- if (SH_IC_DTE & readb(&base->icsr))
+ for (i = 0; i < IRQ_WAIT; i++) {
+ if (SH_IC_DTE & readb(&dev->icsr))
break;
udelay(10);
}
}
-static int irq_dte_with_tack(struct sh_i2c *base)
+static int sh_irq_dte_with_tack(struct sh_i2c *dev)
{
int i;
- for (i = 0 ; i < IRQ_WAIT ; i++) {
- if (SH_IC_DTE & readb(&base->icsr))
+ for (i = 0; i < IRQ_WAIT; i++) {
+ if (SH_IC_DTE & readb(&dev->icsr))
break;
- if (SH_IC_TACK & readb(&base->icsr))
+ if (SH_IC_TACK & readb(&dev->icsr))
return -1;
udelay(10);
}
return 0;
}
-static void irq_busy(struct sh_i2c *base)
+static void sh_irq_busy(struct sh_i2c *dev)
{
int i;
- for (i = 0 ; i < IRQ_WAIT ; i++) {
- if (!(SH_IC_BUSY & readb(&base->icsr)))
+ for (i = 0; i < IRQ_WAIT; i++) {
+ if (!(SH_IC_BUSY & readb(&dev->icsr)))
break;
udelay(10);
}
}
-static int i2c_set_addr(struct sh_i2c *base, u8 id, u8 reg, int stop)
+static int sh_i2c_set_addr(struct sh_i2c *dev, u8 chip, u8 addr, int stop)
{
u8 icic = SH_IC_TACK;
- clrbits_8(&base->iccr, SH_I2C_ICCR_ICE);
- setbits_8(&base->iccr, SH_I2C_ICCR_ICE);
+ debug("%s: chip: %x, addr: %x iccl: %x, icch %x\n",
+ __func__, chip, addr, iccl, icch);
+ clrbits_8(&dev->iccr, SH_I2C_ICCR_ICE);
+ setbits_8(&dev->iccr, SH_I2C_ICCR_ICE);
- writeb(iccl & 0xff, &base->iccl);
- writeb(icch & 0xff, &base->icch);
+ writeb(iccl & 0xff, &dev->iccl);
+ writeb(icch & 0xff, &dev->icch);
#ifdef CONFIG_SH_I2C_8BIT
if (iccl > 0xff)
icic |= SH_I2C_ICIC_ICCLB8;
if (icch > 0xff)
icic |= SH_I2C_ICIC_ICCHB8;
#endif
- writeb(icic, &base->icic);
+ writeb(icic, &dev->icic);
- writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &base->iccr);
- irq_dte(base);
+ writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &dev->iccr);
+ sh_irq_dte(dev);
- clrbits_8(&base->icsr, SH_IC_TACK);
- writeb(id << 1, &base->icdr);
- if (irq_dte_with_tack(base) != 0)
+ clrbits_8(&dev->icsr, SH_IC_TACK);
+ writeb(chip << 1, &dev->icdr);
+ if (sh_irq_dte_with_tack(dev) != 0)
return -1;
- writeb(reg, &base->icdr);
+ writeb(addr, &dev->icdr);
if (stop)
- writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS), &base->iccr);
+ writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS), &dev->iccr);
- if (irq_dte_with_tack(base) != 0)
+ if (sh_irq_dte_with_tack(dev) != 0)
return -1;
return 0;
}
-static void i2c_finish(struct sh_i2c *base)
+static void sh_i2c_finish(struct sh_i2c *dev)
{
- writeb(0, &base->icsr);
- clrbits_8(&base->iccr, SH_I2C_ICCR_ICE);
+ writeb(0, &dev->icsr);
+ clrbits_8(&dev->iccr, SH_I2C_ICCR_ICE);
}
-static int i2c_raw_write(struct sh_i2c *base, u8 id, u8 reg, u8 val)
+static int
+sh_i2c_raw_write(struct sh_i2c *dev, u8 chip, uint addr, u8 val)
{
int ret = -1;
- if (i2c_set_addr(base, id, reg, 0) != 0)
+ if (sh_i2c_set_addr(dev, chip, addr, 0) != 0)
goto exit0;
udelay(10);
- writeb(val, &base->icdr);
- if (irq_dte_with_tack(base) != 0)
+ writeb(val, &dev->icdr);
+ if (sh_irq_dte_with_tack(dev) != 0)
goto exit0;
- writeb((SH_I2C_ICCR_ICE | SH_I2C_ICCR_RTS), &base->iccr);
- if (irq_dte_with_tack(base) != 0)
+ writeb((SH_I2C_ICCR_ICE | SH_I2C_ICCR_RTS), &dev->iccr);
+ if (sh_irq_dte_with_tack(dev) != 0)
goto exit0;
- irq_busy(base);
+ sh_irq_busy(dev);
ret = 0;
+
exit0:
- i2c_finish(base);
+ sh_i2c_finish(dev);
return ret;
}
-static int i2c_raw_read(struct sh_i2c *base, u8 id, u8 reg)
+static int sh_i2c_raw_read(struct sh_i2c *dev, u8 chip, u8 addr)
{
int ret = -1;
#if defined(CONFIG_SH73A0)
- if (i2c_set_addr(base, id, reg, 0) != 0)
+ if (sh_i2c_set_addr(dev, chip, addr, 0) != 0)
goto exit0;
#else
- if (i2c_set_addr(base, id, reg, 1) != 0)
+ if (sh_i2c_set_addr(dev, chip, addr, 1) != 0)
goto exit0;
udelay(100);
#endif
- writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &base->iccr);
- irq_dte(base);
+ writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &dev->iccr);
+ sh_irq_dte(dev);
- writeb(id << 1 | 0x01, &base->icdr);
- if (irq_dte_with_tack(base) != 0)
+ writeb(chip << 1 | 0x01, &dev->icdr);
+ if (sh_irq_dte_with_tack(dev) != 0)
goto exit0;
- writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_SCP), &base->iccr);
- if (irq_dte_with_tack(base) != 0)
+ writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_SCP), &dev->iccr);
+ if (sh_irq_dte_with_tack(dev) != 0)
goto exit0;
- ret = readb(&base->icdr) & 0xff;
+ ret = readb(&dev->icdr) & 0xff;
- writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RACK), &base->iccr);
- readb(&base->icdr); /* Dummy read */
- irq_busy(base);
+ writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RACK), &dev->iccr);
+ readb(&dev->icdr); /* Dummy read */
+ sh_irq_busy(dev);
+
exit0:
- i2c_finish(base);
+ sh_i2c_finish(dev);
return ret;
}
-#ifdef CONFIG_I2C_MULTI_BUS
-static unsigned int current_bus;
-
-/**
- * i2c_set_bus_num - change active I2C bus
- * @bus: bus index, zero based
- * @returns: 0 on success, non-0 on failure
- */
-int i2c_set_bus_num(unsigned int bus)
-{
- if ((bus < 0) || (bus >= CONFIG_SYS_MAX_I2C_BUS)) {
- printf("Bad bus: %d\n", bus);
- return -1;
- }
-
- switch (bus) {
- case 0:
- base = (void *)CONFIG_SH_I2C_BASE0;
- break;
- case 1:
- base = (void *)CONFIG_SH_I2C_BASE1;
- break;
-#ifdef CONFIG_SH_I2C_BASE2
- case 2:
- base = (void *)CONFIG_SH_I2C_BASE2;
- break;
-#endif
-#ifdef CONFIG_SH_I2C_BASE3
- case 3:
- base = (void *)CONFIG_SH_I2C_BASE3;
- break;
-#endif
-#ifdef CONFIG_SH_I2C_BASE4
- case 4:
- base = (void *)CONFIG_SH_I2C_BASE4;
- break;
-#endif
- default:
- return -1;
- }
- current_bus = bus;
-
- return 0;
-}
-
-/**
- * i2c_get_bus_num - returns index of active I2C bus
- */
-unsigned int i2c_get_bus_num(void)
-{
- return current_bus;
-}
-#endif
-
-#define SH_I2C_ICCL_CALC(clk, date, t_low, t_high) \
- ((clk / rate) * (t_low / t_low + t_high))
-#define SH_I2C_ICCH_CALC(clk, date, t_low, t_high) \
- ((clk / rate) * (t_high / t_low + t_high))
-
-void i2c_init(int speed, int slaveaddr)
+static void
+sh_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
{
int num, denom, tmp;
@@ -246,11 +208,6 @@
if (!(gd->flags & GD_FLG_RELOC))
return;
-#ifdef CONFIG_I2C_MULTI_BUS
- current_bus = 0;
-#endif
- base = (struct sh_i2c *)CONFIG_SH_I2C_BASE0;
-
/*
* Calculate the value for iccl. From the data sheet:
* iccl = (p-clock / transfer-rate) * (L / (L + H))
@@ -272,67 +229,78 @@
icch = (u16)((num/denom) + 1);
else
icch = (u16)(num/denom);
+
+ debug("clock: %d, speed %d, iccl: %x, icch: %x\n",
+ CONFIG_SH_I2C_CLOCK, speed, iccl, icch);
}
-/*
- * i2c_read: - Read multiple bytes from an i2c device
- *
- * The higher level routines take into account that this function is only
- * called with len < page length of the device (see configuration file)
- *
- * @chip: address of the chip which is to be read
- * @addr: i2c data address within the chip
- * @alen: length of the i2c data address (1..2 bytes)
- * @buffer: where to write the data
- * @len: how much byte do we want to read
- * @return: 0 in case of success
- */
-int i2c_read(u8 chip, u32 addr, int alen, u8 *buffer, int len)
+static int sh_i2c_read(struct i2c_adapter *adap, uint8_t chip,
+ uint addr, int alen, u8 *data, int len)
{
- int ret;
- int i = 0;
- for (i = 0 ; i < len ; i++) {
- ret = i2c_raw_read(base, chip, addr + i);
+ int ret, i;
+ struct sh_i2c *dev = (struct sh_i2c *)i2c_dev[adap->hwadapnr];
+
+ for (i = 0; i < len; i++) {
+ ret = sh_i2c_raw_read(dev, chip, addr + i);
if (ret < 0)
return -1;
- buffer[i] = ret & 0xff;
+
+ data[i] = ret & 0xff;
+ debug("%s: data[%d]: %02x\n", __func__, i, data[i]);
+ }
+
+ return 0;
+}
+
+static int sh_i2c_write(struct i2c_adapter *adap, uint8_t chip, uint addr,
+ int alen, u8 *data, int len)
+{
+ struct sh_i2c *dev = (struct sh_i2c *)i2c_dev[adap->hwadapnr];
+ int i;
+
+ for (i = 0; i < len; i++) {
+ debug("%s: data[%d]: %02x\n", __func__, i, data[i]);
+ if (sh_i2c_raw_write(dev, chip, addr + i, data[i]) != 0)
+ return -1;
}
return 0;
}
-/*
- * i2c_write: - Write multiple bytes to an i2c device
- *
- * The higher level routines take into account that this function is only
- * called with len < page length of the device (see configuration file)
- *
- * @chip: address of the chip which is to be written
- * @addr: i2c data address within the chip
- * @alen: length of the i2c data address (1..2 bytes)
- * @buffer: where to find the data to be written
- * @len: how much byte do we want to read
- * @return: 0 in case of success
- */
-int i2c_write(u8 chip, u32 addr, int alen, u8 *buffer, int len)
+static int
+sh_i2c_probe(struct i2c_adapter *adap, u8 dev)
{
- int i = 0;
- for (i = 0; i < len ; i++)
- if (i2c_raw_write(base, chip, addr + i, buffer[i]) != 0)
- return -1;
+ return sh_i2c_read(adap, dev, 0, 0, NULL, 0);
+}
+
+static unsigned int sh_i2c_set_bus_speed(struct i2c_adapter *adap,
+ unsigned int speed)
+{
+ struct sh_i2c *dev = (struct sh_i2c *)i2c_dev[adap->hwadapnr];
+
+ sh_i2c_finish(dev);
+ sh_i2c_init(adap, speed, 0);
+
return 0;
}
/*
- * i2c_probe: - Test if a chip answers for a given i2c address
- *
- * @chip: address of the chip which is searched for
- * @return: 0 if a chip was found, -1 otherwhise
+ * Register RCAR i2c adapters
*/
-int i2c_probe(u8 chip)
-{
- int ret;
-
- ret = i2c_set_addr(base, chip, 0, 1);
- i2c_finish(base);
- return ret;
-}
+U_BOOT_I2C_ADAP_COMPLETE(sh_0, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
+ sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED0, 0, 0)
+#ifdef CONFIG_SYS_I2C_SH_BASE1
+U_BOOT_I2C_ADAP_COMPLETE(sh_1, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
+ sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED1, 0, 1)
+#endif
+#ifdef CONFIG_SYS_I2C_SH_BASE2
+U_BOOT_I2C_ADAP_COMPLETE(sh_2, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
+ sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED2, 0, 2)
+#endif
+#ifdef CONFIG_SYS_I2C_SH_BASE3
+U_BOOT_I2C_ADAP_COMPLETE(sh_3, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
+ sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED3, 0, 3)
+#endif
+#ifdef CONFIG_SYS_I2C_SH_BASE4
+U_BOOT_I2C_ADAP_COMPLETE(sh_4, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
+ sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED4, 0, 4)
+#endif
diff --git a/drivers/i2c/zynq_i2c.c b/drivers/i2c/zynq_i2c.c
index ce2d23f..70a9aea 100644
--- a/drivers/i2c/zynq_i2c.c
+++ b/drivers/i2c/zynq_i2c.c
@@ -74,7 +74,8 @@
(struct zynq_i2c_registers *)ZYNQ_I2C_BASE;
/* I2C init called by cmd_i2c when doing 'i2c reset'. */
-void i2c_init(int requested_speed, int slaveadd)
+static void zynq_i2c_init(struct i2c_adapter *adap, int requested_speed,
+ int slaveadd)
{
/* 111MHz / ( (3 * 17) * 22 ) = ~100KHz */
writel((16 << ZYNQ_I2C_CONTROL_DIV_B_SHIFT) |
@@ -151,7 +152,7 @@
* I2C probe called by cmd_i2c when doing 'i2c probe'.
* Begin read, nak data byte, end.
*/
-int i2c_probe(u8 dev)
+static int zynq_i2c_probe(struct i2c_adapter *adap, u8 dev)
{
/* Attempt to read a byte */
setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO |
@@ -170,7 +171,8 @@
* I2C read called by cmd_i2c when doing 'i2c read' and by cmd_eeprom.c
* Begin write, send address byte(s), begin read, receive data bytes, end.
*/
-int i2c_read(u8 dev, uint addr, int alen, u8 *data, int length)
+static int zynq_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
+ int alen, u8 *data, int length)
{
u32 status;
u32 i = 0;
@@ -235,7 +237,8 @@
* I2C write called by cmd_i2c when doing 'i2c write' and by cmd_eeprom.c
* Begin write, send address byte(s), send data bytes, end.
*/
-int i2c_write(u8 dev, uint addr, int alen, u8 *data, int length)
+static int zynq_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
+ int alen, u8 *data, int length)
{
u8 *cur_data = data;
@@ -275,16 +278,16 @@
return 0;
}
-int i2c_set_bus_num(unsigned int bus)
+static unsigned int zynq_i2c_set_bus_speed(struct i2c_adapter *adap,
+ unsigned int speed)
{
- /* Only support bus 0 */
- if (bus > 0)
- return -1;
+ if (speed != 1000000)
+ return -EINVAL;
+
return 0;
}
-unsigned int i2c_get_bus_num(void)
-{
- /* Only support bus 0 */
- return 0;
-}
+U_BOOT_I2C_ADAP_COMPLETE(zynq_0, zynq_i2c_init, zynq_i2c_probe, zynq_i2c_read,
+ zynq_i2c_write, zynq_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_ZYNQ_SPEED, CONFIG_SYS_I2C_ZYNQ_SLAVE,
+ 0)
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index d8ff9c6..c77e40a 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -20,3 +20,4 @@
obj-$(CONFIG_PDSP188x) += pdsp188x.o
obj-$(CONFIG_STATUS_LED) += status_led.o
obj-$(CONFIG_TWL4030_LED) += twl4030_led.o
+obj-$(CONFIG_FSL_IFC) += fsl_ifc.o
diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c b/drivers/misc/fsl_ifc.c
similarity index 86%
rename from arch/powerpc/cpu/mpc8xxx/fsl_ifc.c
rename to drivers/misc/fsl_ifc.c
index 2d0fb43..be61973 100644
--- a/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c
+++ b/drivers/misc/fsl_ifc.c
@@ -6,7 +6,7 @@
*/
#include <common.h>
-#include <asm/fsl_ifc.h>
+#include <fsl_ifc.h>
void print_ifc_regs(void)
{
@@ -34,6 +34,9 @@
#ifdef CONFIG_SYS_CSPR0_EXT
set_ifc_cspr_ext(IFC_CS0, CONFIG_SYS_CSPR0_EXT);
#endif
+#ifdef CONFIG_SYS_CSOR0_EXT
+ set_ifc_csor_ext(IFC_CS0, CONFIG_SYS_CSOR0_EXT);
+#endif
set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0);
set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0);
set_ifc_csor(IFC_CS0, CONFIG_SYS_CSOR0);
@@ -43,6 +46,9 @@
#ifdef CONFIG_SYS_CSPR1_EXT
set_ifc_cspr_ext(IFC_CS1, CONFIG_SYS_CSPR1_EXT);
#endif
+#ifdef CONFIG_SYS_CSOR1_EXT
+ set_ifc_csor_ext(IFC_CS1, CONFIG_SYS_CSOR1_EXT);
+#endif
#if defined(CONFIG_SYS_CSPR1) && defined(CONFIG_SYS_CSOR1)
set_ifc_ftim(IFC_CS1, IFC_FTIM0, CONFIG_SYS_CS1_FTIM0);
set_ifc_ftim(IFC_CS1, IFC_FTIM1, CONFIG_SYS_CS1_FTIM1);
@@ -57,6 +63,9 @@
#ifdef CONFIG_SYS_CSPR2_EXT
set_ifc_cspr_ext(IFC_CS2, CONFIG_SYS_CSPR2_EXT);
#endif
+#ifdef CONFIG_SYS_CSOR2_EXT
+ set_ifc_csor_ext(IFC_CS2, CONFIG_SYS_CSOR2_EXT);
+#endif
#if defined(CONFIG_SYS_CSPR2) && defined(CONFIG_SYS_CSOR2)
set_ifc_ftim(IFC_CS2, IFC_FTIM0, CONFIG_SYS_CS2_FTIM0);
set_ifc_ftim(IFC_CS2, IFC_FTIM1, CONFIG_SYS_CS2_FTIM1);
@@ -71,6 +80,9 @@
#ifdef CONFIG_SYS_CSPR3_EXT
set_ifc_cspr_ext(IFC_CS3, CONFIG_SYS_CSPR3_EXT);
#endif
+#ifdef CONFIG_SYS_CSOR3_EXT
+ set_ifc_csor_ext(IFC_CS3, CONFIG_SYS_CSOR3_EXT);
+#endif
#if defined(CONFIG_SYS_CSPR3) && defined(CONFIG_SYS_CSOR3)
set_ifc_ftim(IFC_CS3, IFC_FTIM0, CONFIG_SYS_CS3_FTIM0);
set_ifc_ftim(IFC_CS3, IFC_FTIM1, CONFIG_SYS_CS3_FTIM1);
@@ -85,6 +97,9 @@
#ifdef CONFIG_SYS_CSPR4_EXT
set_ifc_cspr_ext(IFC_CS4, CONFIG_SYS_CSPR4_EXT);
#endif
+#ifdef CONFIG_SYS_CSOR4_EXT
+ set_ifc_csor_ext(IFC_CS4, CONFIG_SYS_CSOR4_EXT);
+#endif
#if defined(CONFIG_SYS_CSPR4) && defined(CONFIG_SYS_CSOR4)
set_ifc_ftim(IFC_CS4, IFC_FTIM0, CONFIG_SYS_CS4_FTIM0);
set_ifc_ftim(IFC_CS4, IFC_FTIM1, CONFIG_SYS_CS4_FTIM1);
@@ -99,6 +114,9 @@
#ifdef CONFIG_SYS_CSPR5_EXT
set_ifc_cspr_ext(IFC_CS5, CONFIG_SYS_CSPR5_EXT);
#endif
+#ifdef CONFIG_SYS_CSOR5_EXT
+ set_ifc_csor_ext(IFC_CS5, CONFIG_SYS_CSOR5_EXT);
+#endif
#if defined(CONFIG_SYS_CSPR5) && defined(CONFIG_SYS_CSOR5)
set_ifc_ftim(IFC_CS5, IFC_FTIM0, CONFIG_SYS_CS5_FTIM0);
set_ifc_ftim(IFC_CS5, IFC_FTIM1, CONFIG_SYS_CS5_FTIM1);
@@ -113,6 +131,9 @@
#ifdef CONFIG_SYS_CSPR6_EXT
set_ifc_cspr_ext(IFC_CS6, CONFIG_SYS_CSPR6_EXT);
#endif
+#ifdef CONFIG_SYS_CSOR6_EXT
+ set_ifc_csor_ext(IFC_CS6, CONFIG_SYS_CSOR6_EXT);
+#endif
#if defined(CONFIG_SYS_CSPR6) && defined(CONFIG_SYS_CSOR6)
set_ifc_ftim(IFC_CS6, IFC_FTIM0, CONFIG_SYS_CS6_FTIM0);
set_ifc_ftim(IFC_CS6, IFC_FTIM1, CONFIG_SYS_CS6_FTIM1);
@@ -127,6 +148,9 @@
#ifdef CONFIG_SYS_CSPR7_EXT
set_ifc_cspr_ext(IFC_CS7, CONFIG_SYS_CSPR7_EXT);
#endif
+#ifdef CONFIG_SYS_CSOR7_EXT
+ set_ifc_csor_ext(IFC_CS7, CONFIG_SYS_CSOR7_EXT);
+#endif
#if defined(CONFIG_SYS_CSPR7) && defined(CONFIG_SYS_CSOR7)
set_ifc_ftim(IFC_CS7, IFC_FTIM0, CONFIG_SYS_CS7_FTIM0);
set_ifc_ftim(IFC_CS7, IFC_FTIM1, CONFIG_SYS_CS7_FTIM1);
diff --git a/drivers/misc/gpio_led.c b/drivers/misc/gpio_led.c
index 3fedddc..3e95727 100644
--- a/drivers/misc/gpio_led.c
+++ b/drivers/misc/gpio_led.c
@@ -9,15 +9,42 @@
#include <status_led.h>
#include <asm/gpio.h>
+#ifndef CONFIG_GPIO_LED_INVERTED_TABLE
+#define CONFIG_GPIO_LED_INVERTED_TABLE {}
+#endif
+
+static led_id_t gpio_led_inv[] = CONFIG_GPIO_LED_INVERTED_TABLE;
+
+static int gpio_led_gpio_value(led_id_t mask, int state)
+{
+ int i, gpio_value = (state == STATUS_LED_ON);
+
+ for (i = 0; i < ARRAY_SIZE(gpio_led_inv); i++) {
+ if (gpio_led_inv[i] == mask)
+ gpio_value = !gpio_value;
+ }
+
+ return gpio_value;
+}
+
void __led_init(led_id_t mask, int state)
{
- gpio_request(mask, "gpio_led");
- gpio_direction_output(mask, state == STATUS_LED_ON);
+ int gpio_value;
+
+ if (gpio_request(mask, "gpio_led") != 0) {
+ printf("%s: failed requesting GPIO%lu!\n", __func__, mask);
+ return;
+ }
+
+ gpio_value = gpio_led_gpio_value(mask, state);
+ gpio_direction_output(mask, gpio_value);
}
void __led_set(led_id_t mask, int state)
{
- gpio_set_value(mask, state == STATUS_LED_ON);
+ int gpio_value = gpio_led_gpio_value(mask, state);
+
+ gpio_set_value(mask, gpio_value);
}
void __led_toggle(led_id_t mask)
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index eb1eafa..e145cd1 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -58,6 +58,7 @@
obj-$(CONFIG_NAND_SPEAR) += spr_nand.o
obj-$(CONFIG_TEGRA_NAND) += tegra_nand.o
obj-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o
+obj-$(CONFIG_NAND_OMAP_ELM) += omap_elm.o
obj-$(CONFIG_NAND_PLAT) += nand_plat.o
obj-$(CONFIG_NAND_DOCG4) += docg4.o
diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index 99fc86c..05ddfbb 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -411,7 +411,7 @@
}
if (!timeout) {
- printk(KERN_ERR "atmel_nand : Timeout to calculate PMECC error location\n");
+ dev_err(host->dev, "atmel_nand : Timeout to calculate PMECC error location\n");
return -1;
}
@@ -451,7 +451,7 @@
*(buf + byte_pos) ^= (1 << bit_pos);
pos = sector_num * host->pmecc_sector_size + byte_pos;
- printk(KERN_INFO "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
+ dev_dbg(host->dev, "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
pos, bit_pos, err_byte, *(buf + byte_pos));
} else {
/* Bit flip in OOB area */
@@ -461,7 +461,7 @@
ecc[tmp] ^= (1 << bit_pos);
pos = tmp + nand_chip->ecc.layout->eccpos[0];
- printk(KERN_INFO "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
+ dev_dbg(host->dev, "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
pos, bit_pos, err_byte, ecc[tmp]);
}
@@ -499,7 +499,7 @@
err_nbr = pmecc_err_location(mtd);
if (err_nbr == -1) {
- printk(KERN_ERR "PMECC: Too many errors\n");
+ dev_err(host->dev, "PMECC: Too many errors\n");
mtd->ecc_stats.failed++;
return -EIO;
} else {
@@ -543,7 +543,7 @@
}
if (!timeout) {
- printk(KERN_ERR "atmel_nand : Timeout to read PMECC page\n");
+ dev_err(host->dev, "atmel_nand : Timeout to read PMECC page\n");
return -1;
}
@@ -583,7 +583,7 @@
}
if (!timeout) {
- printk(KERN_ERR "atmel_nand : Timeout to read PMECC status, fail to write PMECC in oob\n");
+ dev_err(host->dev, "atmel_nand : Timeout to read PMECC status, fail to write PMECC in oob\n");
goto out;
}
@@ -826,6 +826,7 @@
switch (mtd->writesize) {
case 2048:
case 4096:
+ case 8192:
host->pmecc_degree = (sector_size == 512) ?
PMECC_GF_DIMENSION_13 : PMECC_GF_DIMENSION_14;
host->pmecc_cw_len = (1 << host->pmecc_degree) - 1;
@@ -839,8 +840,15 @@
nand->ecc.steps = 1;
nand->ecc.bytes = host->pmecc_bytes_per_sector *
host->pmecc_sector_number;
+
+ if (nand->ecc.bytes > MTD_MAX_ECCPOS_ENTRIES_LARGE) {
+ dev_err(host->dev, "too large eccpos entries. max support ecc.bytes is %d\n",
+ MTD_MAX_ECCPOS_ENTRIES_LARGE);
+ return -EINVAL;
+ }
+
if (nand->ecc.bytes > mtd->oobsize - 2) {
- printk(KERN_ERR "No room for ECC bytes\n");
+ dev_err(host->dev, "No room for ECC bytes\n");
return -EINVAL;
}
pmecc_config_ecc_layout(&atmel_pmecc_oobinfo,
@@ -851,7 +859,7 @@
case 512:
case 1024:
/* TODO */
- printk(KERN_ERR "Unsupported page size for PMECC, use Software ECC\n");
+ dev_err(host->dev, "Unsupported page size for PMECC, use Software ECC\n");
default:
/* page size not handled by HW ECC */
/* switching back to soft ECC */
@@ -1034,7 +1042,7 @@
/* it doesn't seems to be a freshly
* erased block.
* We can't correct so many errors */
- printk(KERN_WARNING "atmel_nand : multiple errors detected."
+ dev_warn(host->dev, "atmel_nand : multiple errors detected."
" Unable to correct.\n");
return -EIO;
}
@@ -1044,12 +1052,12 @@
/* there's nothing much to do here.
* the bit error is on the ECC itself.
*/
- printk(KERN_WARNING "atmel_nand : one bit error on ECC code."
+ dev_warn(host->dev, "atmel_nand : one bit error on ECC code."
" Nothing to correct\n");
return 0;
}
- printk(KERN_WARNING "atmel_nand : one bit error on data."
+ dev_warn(host->dev, "atmel_nand : one bit error on data."
" (word offset in the page :"
" 0x%x bit offset : 0x%x)\n",
ecc_word, ecc_bit);
@@ -1061,7 +1069,7 @@
/* 8 bits words */
dat[ecc_word] ^= (1 << ecc_bit);
}
- printk(KERN_WARNING "atmel_nand : error corrected\n");
+ dev_warn(host->dev, "atmel_nand : error corrected\n");
return 1;
}
@@ -1176,7 +1184,11 @@
mtd->priv = nand;
nand->IO_ADDR_R = nand->IO_ADDR_W = (void __iomem *)base_addr;
+#ifdef CONFIG_NAND_ECC_BCH
+ nand->ecc.mode = NAND_ECC_SOFT_BCH;
+#else
nand->ecc.mode = NAND_ECC_SOFT;
+#endif
#ifdef CONFIG_SYS_NAND_DBW_16
nand->options = NAND_BUSWIDTH_16;
#endif
@@ -1184,7 +1196,7 @@
#ifdef CONFIG_SYS_NAND_READY_PIN
nand->dev_ready = at91_nand_ready;
#endif
- nand->chip_delay = 20;
+ nand->chip_delay = 75;
ret = nand_scan_ident(mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL);
if (ret)
@@ -1212,6 +1224,6 @@
int i;
for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
if (atmel_nand_chip_init(i, base_addr[i]))
- printk(KERN_ERR "atmel_nand: Fail to initialize #%d chip",
+ dev_err(host->dev, "atmel_nand: Fail to initialize #%d chip",
i);
}
diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c
index 98a09c0..1808a7f 100644
--- a/drivers/mtd/nand/fsl_ifc_nand.c
+++ b/drivers/mtd/nand/fsl_ifc_nand.c
@@ -17,7 +17,7 @@
#include <asm/io.h>
#include <asm/errno.h>
-#include <asm/fsl_ifc.h>
+#include <fsl_ifc.h>
#define FSL_IFC_V1_1_0 0x01010000
#define MAX_BANKS 4
@@ -125,6 +125,69 @@
.oobfree = { {2, 6}, {136, 82} },
};
+/* 8192-byte page size with 4-bit ECC */
+static struct nand_ecclayout oob_8192_ecc4 = {
+ .eccbytes = 128,
+ .eccpos = {
+ 8, 9, 10, 11, 12, 13, 14, 15,
+ 16, 17, 18, 19, 20, 21, 22, 23,
+ 24, 25, 26, 27, 28, 29, 30, 31,
+ 32, 33, 34, 35, 36, 37, 38, 39,
+ 40, 41, 42, 43, 44, 45, 46, 47,
+ 48, 49, 50, 51, 52, 53, 54, 55,
+ 56, 57, 58, 59, 60, 61, 62, 63,
+ 64, 65, 66, 67, 68, 69, 70, 71,
+ 72, 73, 74, 75, 76, 77, 78, 79,
+ 80, 81, 82, 83, 84, 85, 86, 87,
+ 88, 89, 90, 91, 92, 93, 94, 95,
+ 96, 97, 98, 99, 100, 101, 102, 103,
+ 104, 105, 106, 107, 108, 109, 110, 111,
+ 112, 113, 114, 115, 116, 117, 118, 119,
+ 120, 121, 122, 123, 124, 125, 126, 127,
+ 128, 129, 130, 131, 132, 133, 134, 135,
+ },
+ .oobfree = { {2, 6}, {136, 208} },
+};
+
+/* 8192-byte page size with 8-bit ECC -- requires 218-byte OOB */
+static struct nand_ecclayout oob_8192_ecc8 = {
+ .eccbytes = 256,
+ .eccpos = {
+ 8, 9, 10, 11, 12, 13, 14, 15,
+ 16, 17, 18, 19, 20, 21, 22, 23,
+ 24, 25, 26, 27, 28, 29, 30, 31,
+ 32, 33, 34, 35, 36, 37, 38, 39,
+ 40, 41, 42, 43, 44, 45, 46, 47,
+ 48, 49, 50, 51, 52, 53, 54, 55,
+ 56, 57, 58, 59, 60, 61, 62, 63,
+ 64, 65, 66, 67, 68, 69, 70, 71,
+ 72, 73, 74, 75, 76, 77, 78, 79,
+ 80, 81, 82, 83, 84, 85, 86, 87,
+ 88, 89, 90, 91, 92, 93, 94, 95,
+ 96, 97, 98, 99, 100, 101, 102, 103,
+ 104, 105, 106, 107, 108, 109, 110, 111,
+ 112, 113, 114, 115, 116, 117, 118, 119,
+ 120, 121, 122, 123, 124, 125, 126, 127,
+ 128, 129, 130, 131, 132, 133, 134, 135,
+ 136, 137, 138, 139, 140, 141, 142, 143,
+ 144, 145, 146, 147, 148, 149, 150, 151,
+ 152, 153, 154, 155, 156, 157, 158, 159,
+ 160, 161, 162, 163, 164, 165, 166, 167,
+ 168, 169, 170, 171, 172, 173, 174, 175,
+ 176, 177, 178, 179, 180, 181, 182, 183,
+ 184, 185, 186, 187, 188, 189, 190, 191,
+ 192, 193, 194, 195, 196, 197, 198, 199,
+ 200, 201, 202, 203, 204, 205, 206, 207,
+ 208, 209, 210, 211, 212, 213, 214, 215,
+ 216, 217, 218, 219, 220, 221, 222, 223,
+ 224, 225, 226, 227, 228, 229, 230, 231,
+ 232, 233, 234, 235, 236, 237, 238, 239,
+ 240, 241, 242, 243, 244, 245, 246, 247,
+ 248, 249, 250, 251, 252, 253, 254, 255,
+ 256, 257, 258, 259, 260, 261, 262, 263,
+ },
+ .oobfree = { {2, 6}, {264, 80} },
+};
/*
* Generic flash bbt descriptors
@@ -428,20 +491,27 @@
if (mtd->writesize > 512) {
nand_fcr0 =
(NAND_CMD_SEQIN << IFC_NAND_FCR0_CMD0_SHIFT) |
- (NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD1_SHIFT);
+ (NAND_CMD_STATUS << IFC_NAND_FCR0_CMD1_SHIFT) |
+ (NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD2_SHIFT);
out_be32(&ifc->ifc_nand.nand_fir0,
(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
(IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
(IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
(IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP3_SHIFT) |
- (IFC_FIR_OP_CW1 << IFC_NAND_FIR0_OP4_SHIFT));
- out_be32(&ifc->ifc_nand.nand_fir1, 0);
+ (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP4_SHIFT));
+ out_be32(&ifc->ifc_nand.nand_fir1,
+ (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT) |
+ (IFC_FIR_OP_RDSTAT <<
+ IFC_NAND_FIR1_OP6_SHIFT) |
+ (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP7_SHIFT));
} else {
nand_fcr0 = ((NAND_CMD_PAGEPROG <<
IFC_NAND_FCR0_CMD1_SHIFT) |
(NAND_CMD_SEQIN <<
- IFC_NAND_FCR0_CMD2_SHIFT));
+ IFC_NAND_FCR0_CMD2_SHIFT) |
+ (NAND_CMD_STATUS <<
+ IFC_NAND_FCR0_CMD3_SHIFT));
out_be32(&ifc->ifc_nand.nand_fir0,
(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
@@ -450,7 +520,11 @@
(IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) |
(IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT));
out_be32(&ifc->ifc_nand.nand_fir1,
- (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT));
+ (IFC_FIR_OP_CMD1 << IFC_NAND_FIR1_OP5_SHIFT) |
+ (IFC_FIR_OP_CW3 << IFC_NAND_FIR1_OP6_SHIFT) |
+ (IFC_FIR_OP_RDSTAT <<
+ IFC_NAND_FIR1_OP7_SHIFT) |
+ (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP8_SHIFT));
if (column >= mtd->writesize)
nand_fcr0 |=
@@ -902,6 +976,21 @@
priv->bufnum_mask = 1;
break;
+ case CSOR_NAND_PGS_8K:
+ if ((csor & CSOR_NAND_ECC_MODE_MASK) ==
+ CSOR_NAND_ECC_MODE_4) {
+ layout = &oob_8192_ecc4;
+ nand->ecc.strength = 4;
+ } else {
+ layout = &oob_8192_ecc8;
+ nand->ecc.strength = 8;
+ nand->ecc.bytes = 16;
+ }
+
+ priv->bufnum_mask = 0;
+ break;
+
+
default:
printf("ifc nand: bad csor %#x: bad page size\n", csor);
return -ENODEV;
diff --git a/drivers/mtd/nand/fsl_ifc_spl.c b/drivers/mtd/nand/fsl_ifc_spl.c
index d462265..9de327b 100644
--- a/drivers/mtd/nand/fsl_ifc_spl.c
+++ b/drivers/mtd/nand/fsl_ifc_spl.c
@@ -9,7 +9,7 @@
#include <common.h>
#include <asm/io.h>
-#include <asm/fsl_ifc.h>
+#include <fsl_ifc.h>
#include <linux/mtd/nand.h>
static inline int is_blank(uchar *addr, int page_size)
@@ -112,10 +112,13 @@
port_size = (cspr & CSPR_PORT_SIZE_16) ? 16 : 8;
- if (csor & CSOR_NAND_PGS_4K) {
+ if ((csor & CSOR_NAND_PGS_MASK) == CSOR_NAND_PGS_8K) {
+ page_size = 8192;
+ bufnum_mask = 0x0;
+ } else if ((csor & CSOR_NAND_PGS_MASK) == CSOR_NAND_PGS_4K) {
page_size = 4096;
bufnum_mask = 0x1;
- } else if (csor & CSOR_NAND_PGS_2K) {
+ } else if ((csor & CSOR_NAND_PGS_MASK) == CSOR_NAND_PGS_2K) {
page_size = 2048;
bufnum_mask = 0x3;
} else {
diff --git a/arch/arm/cpu/armv7/am33xx/elm.c b/drivers/mtd/nand/omap_elm.c
similarity index 97%
rename from arch/arm/cpu/armv7/am33xx/elm.c
rename to drivers/mtd/nand/omap_elm.c
index 8f1d6af..2aa7807 100644
--- a/arch/arm/cpu/armv7/am33xx/elm.c
+++ b/drivers/mtd/nand/omap_elm.c
@@ -18,7 +18,7 @@
#include <asm/errno.h>
#include <asm/arch/cpu.h>
#include <asm/omap_gpmc.h>
-#include <asm/arch/elm.h>
+#include <asm/omap_elm.h>
#define ELM_DEFAULT_POLY (0)
@@ -127,7 +127,7 @@
for (i = 0; i < *error_count; i++) {
error_locations[i] =
- readl(&elm_cfg->error_location[poly].error_location_x[i]);
+ readl(&elm_cfg->error_location[poly].error_location_x[i]);
}
return 0;
@@ -175,7 +175,7 @@
{
/* initiate reset */
writel((readl(&elm_cfg->sysconfig) | ELM_SYSCONFIG_SOFTRESET),
- &elm_cfg->sysconfig);
+ &elm_cfg->sysconfig);
/* wait for reset complete and normal operation */
while ((readl(&elm_cfg->sysstatus) & ELM_SYSSTATUS_RESETDONE) !=
diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c
index ec1787f..5e7e6b3 100644
--- a/drivers/mtd/nand/omap_gpmc.c
+++ b/drivers/mtd/nand/omap_gpmc.c
@@ -15,15 +15,13 @@
#include <linux/bch.h>
#include <linux/compiler.h>
#include <nand.h>
-#ifdef CONFIG_AM33XX
-#include <asm/arch/elm.h>
-#endif
+#include <asm/omap_elm.h>
+
+#define BADBLOCK_MARKER_LENGTH 2
+#define SECTOR_BYTES 512
static uint8_t cs;
-static __maybe_unused struct nand_ecclayout hw_nand_oob =
- GPMC_NAND_HW_ECC_LAYOUT;
-static __maybe_unused struct nand_ecclayout hw_bch8_nand_oob =
- GPMC_NAND_HW_BCH8_ECC_LAYOUT;
+static __maybe_unused struct nand_ecclayout omap_ecclayout;
/*
* omap_nand_hwcontrol - Set the address pointers corretly for the
@@ -233,6 +231,7 @@
uint8_t type;
uint8_t nibbles;
struct bch_control *control;
+ enum omap_ecc ecc_scheme;
};
/* bch types */
@@ -274,17 +273,15 @@
{
uint32_t val;
uint32_t dev_width = (chip->options & NAND_BUSWIDTH_16) >> 1;
-#ifdef CONFIG_AM33XX
uint32_t unused_length = 0;
-#endif
uint32_t wr_mode = BCH_WRAPMODE_6;
struct nand_bch_priv *bch = chip->priv;
/* Clear the ecc result registers, select ecc reg as 1 */
writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
-#ifdef CONFIG_AM33XX
- wr_mode = BCH_WRAPMODE_1;
+ if (bch->ecc_scheme == OMAP_ECC_BCH8_CODE_HW) {
+ wr_mode = BCH_WRAPMODE_1;
switch (bch->nibbles) {
case ECC_BCH4_NIBBLES:
@@ -320,7 +317,7 @@
val |= (unused_length << 22);
break;
}
-#else
+ } else {
/*
* This ecc_size_config setting is for BCH sw library.
*
@@ -333,7 +330,7 @@
* size1 = 32 (skip 32 nibbles = 16 bytes per sector in spare area)
*/
val = (32 << 22) | (0 << 12);
-#endif
+ }
/* ecc size configuration */
writel(val, &gpmc_cfg->ecc_size_config);
@@ -376,9 +373,9 @@
}
/*
- * BCH8 support (needs ELM and thus AM33xx-only)
+ * BCH support using ELM module
*/
-#ifdef CONFIG_AM33XX
+#ifdef CONFIG_NAND_OMAP_ELM
/*
* omap_read_bch8_result - Read BCH result for BCH8 level
*
@@ -631,20 +628,20 @@
}
return 0;
}
-#endif /* CONFIG_AM33XX */
+#endif /* CONFIG_NAND_OMAP_ELM */
/*
* OMAP3 BCH8 support (with BCH library)
*/
-#ifdef CONFIG_NAND_OMAP_BCH8
+#ifdef CONFIG_BCH
/*
- * omap_calculate_ecc_bch - Read BCH ECC result
+ * omap_calculate_ecc_bch_sw - Read BCH ECC result
*
* @mtd: MTD device structure
* @dat: The pointer to data on which ecc is computed (unused here)
* @ecc: The ECC output buffer
*/
-static int omap_calculate_ecc_bch(struct mtd_info *mtd, const uint8_t *dat,
+static int omap_calculate_ecc_bch_sw(struct mtd_info *mtd, const uint8_t *dat,
uint8_t *ecc)
{
int ret = 0;
@@ -689,13 +686,13 @@
}
/**
- * omap_correct_data_bch - Decode received data and correct errors
+ * omap_correct_data_bch_sw - Decode received data and correct errors
* @mtd: MTD device structure
* @data: page data
* @read_ecc: ecc read from nand flash
* @calc_ecc: ecc read from HW ECC registers
*/
-static int omap_correct_data_bch(struct mtd_info *mtd, u_char *data,
+static int omap_correct_data_bch_sw(struct mtd_info *mtd, u_char *data,
u_char *read_ecc, u_char *calc_ecc)
{
int i, count;
@@ -752,7 +749,150 @@
chip_priv->control = NULL;
}
}
-#endif /* CONFIG_NAND_OMAP_BCH8 */
+#endif /* CONFIG_BCH */
+
+/**
+ * omap_select_ecc_scheme - configures driver for particular ecc-scheme
+ * @nand: NAND chip device structure
+ * @ecc_scheme: ecc scheme to configure
+ * @pagesize: number of main-area bytes per page of NAND device
+ * @oobsize: number of OOB/spare bytes per page of NAND device
+ */
+static int omap_select_ecc_scheme(struct nand_chip *nand,
+ enum omap_ecc ecc_scheme, unsigned int pagesize, unsigned int oobsize) {
+ struct nand_bch_priv *bch = nand->priv;
+ struct nand_ecclayout *ecclayout = nand->ecc.layout;
+ int eccsteps = pagesize / SECTOR_BYTES;
+ int i;
+
+ switch (ecc_scheme) {
+ case OMAP_ECC_HAM1_CODE_SW:
+ debug("nand: selected OMAP_ECC_HAM1_CODE_SW\n");
+ /* For this ecc-scheme, ecc.bytes, ecc.layout, ... are
+ * initialized in nand_scan_tail(), so just set ecc.mode */
+ bch_priv.control = NULL;
+ bch_priv.type = 0;
+ nand->ecc.mode = NAND_ECC_SOFT;
+ nand->ecc.layout = NULL;
+ nand->ecc.size = pagesize;
+ bch->ecc_scheme = OMAP_ECC_HAM1_CODE_SW;
+ break;
+
+ case OMAP_ECC_HAM1_CODE_HW:
+ debug("nand: selected OMAP_ECC_HAM1_CODE_HW\n");
+ /* check ecc-scheme requirements before updating ecc info */
+ if ((3 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) {
+ printf("nand: error: insufficient OOB: require=%d\n", (
+ (3 * eccsteps) + BADBLOCK_MARKER_LENGTH));
+ return -EINVAL;
+ }
+ bch_priv.control = NULL;
+ bch_priv.type = 0;
+ /* populate ecc specific fields */
+ nand->ecc.mode = NAND_ECC_HW;
+ nand->ecc.strength = 1;
+ nand->ecc.size = SECTOR_BYTES;
+ nand->ecc.bytes = 3;
+ nand->ecc.hwctl = omap_enable_hwecc;
+ nand->ecc.correct = omap_correct_data;
+ nand->ecc.calculate = omap_calculate_ecc;
+ /* define ecc-layout */
+ ecclayout->eccbytes = nand->ecc.bytes * eccsteps;
+ for (i = 0; i < ecclayout->eccbytes; i++)
+ ecclayout->eccpos[i] = i + BADBLOCK_MARKER_LENGTH;
+ ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH;
+ ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes -
+ BADBLOCK_MARKER_LENGTH;
+ bch->ecc_scheme = OMAP_ECC_HAM1_CODE_HW;
+ break;
+
+ case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
+#ifdef CONFIG_BCH
+ debug("nand: selected OMAP_ECC_BCH8_CODE_HW_DETECTION_SW\n");
+ /* check ecc-scheme requirements before updating ecc info */
+ if ((13 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) {
+ printf("nand: error: insufficient OOB: require=%d\n", (
+ (13 * eccsteps) + BADBLOCK_MARKER_LENGTH));
+ return -EINVAL;
+ }
+ /* check if BCH S/W library can be used for error detection */
+ bch_priv.control = init_bch(13, 8, 0x201b);
+ if (!bch_priv.control) {
+ printf("nand: error: could not init_bch()\n");
+ return -ENODEV;
+ }
+ bch_priv.type = ECC_BCH8;
+ /* populate ecc specific fields */
+ nand->ecc.mode = NAND_ECC_HW;
+ nand->ecc.strength = 8;
+ nand->ecc.size = SECTOR_BYTES;
+ nand->ecc.bytes = 13;
+ nand->ecc.hwctl = omap_enable_ecc_bch;
+ nand->ecc.correct = omap_correct_data_bch_sw;
+ nand->ecc.calculate = omap_calculate_ecc_bch_sw;
+ /* define ecc-layout */
+ ecclayout->eccbytes = nand->ecc.bytes * eccsteps;
+ ecclayout->eccpos[0] = BADBLOCK_MARKER_LENGTH;
+ for (i = 1; i < ecclayout->eccbytes; i++) {
+ if (i % nand->ecc.bytes)
+ ecclayout->eccpos[i] =
+ ecclayout->eccpos[i - 1] + 1;
+ else
+ ecclayout->eccpos[i] =
+ ecclayout->eccpos[i - 1] + 2;
+ }
+ ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH;
+ ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes -
+ BADBLOCK_MARKER_LENGTH;
+ omap_hwecc_init_bch(nand, NAND_ECC_READ);
+ bch->ecc_scheme = OMAP_ECC_BCH8_CODE_HW_DETECTION_SW;
+ break;
+#else
+ printf("nand: error: CONFIG_BCH required for ECC\n");
+ return -EINVAL;
+#endif
+
+ case OMAP_ECC_BCH8_CODE_HW:
+#ifdef CONFIG_NAND_OMAP_ELM
+ debug("nand: selected OMAP_ECC_BCH8_CODE_HW\n");
+ /* check ecc-scheme requirements before updating ecc info */
+ if ((14 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) {
+ printf("nand: error: insufficient OOB: require=%d\n", (
+ (14 * eccsteps) + BADBLOCK_MARKER_LENGTH));
+ return -EINVAL;
+ }
+ /* intialize ELM for ECC error detection */
+ elm_init();
+ bch_priv.type = ECC_BCH8;
+ /* populate ecc specific fields */
+ nand->ecc.mode = NAND_ECC_HW;
+ nand->ecc.strength = 8;
+ nand->ecc.size = SECTOR_BYTES;
+ nand->ecc.bytes = 14;
+ nand->ecc.hwctl = omap_enable_ecc_bch;
+ nand->ecc.correct = omap_correct_data_bch;
+ nand->ecc.calculate = omap_calculate_ecc_bch;
+ nand->ecc.read_page = omap_read_page_bch;
+ /* define ecc-layout */
+ ecclayout->eccbytes = nand->ecc.bytes * eccsteps;
+ for (i = 0; i < ecclayout->eccbytes; i++)
+ ecclayout->eccpos[i] = i + BADBLOCK_MARKER_LENGTH;
+ ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH;
+ ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes -
+ BADBLOCK_MARKER_LENGTH;
+ bch->ecc_scheme = OMAP_ECC_BCH8_CODE_HW;
+ break;
+#else
+ printf("nand: error: CONFIG_NAND_OMAP_ELM required for ECC\n");
+ return -EINVAL;
+#endif
+
+ default:
+ debug("nand: error: ecc scheme not enabled or supported\n");
+ return -EINVAL;
+ }
+ return 0;
+}
#ifndef CONFIG_SPL_BUILD
/*
@@ -763,77 +903,45 @@
* @eccstrength - the number of bits that could be corrected
* (1 - hamming, 4 - BCH4, 8 - BCH8, 16 - BCH16)
*/
-void omap_nand_switch_ecc(uint32_t hardware, uint32_t eccstrength)
+int __maybe_unused omap_nand_switch_ecc(uint32_t hardware, uint32_t eccstrength)
{
struct nand_chip *nand;
struct mtd_info *mtd;
+ int err = 0;
if (nand_curr_device < 0 ||
nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE ||
!nand_info[nand_curr_device].name) {
- printf("Error: Can't switch ecc, no devices available\n");
- return;
+ printf("nand: error: no NAND devices found\n");
+ return -ENODEV;
}
mtd = &nand_info[nand_curr_device];
nand = mtd->priv;
-
nand->options |= NAND_OWN_BUFFERS;
-
- /* Reset ecc interface */
- nand->ecc.mode = NAND_ECC_NONE;
- nand->ecc.read_page = NULL;
- nand->ecc.write_page = NULL;
- nand->ecc.read_oob = NULL;
- nand->ecc.write_oob = NULL;
- nand->ecc.hwctl = NULL;
- nand->ecc.correct = NULL;
- nand->ecc.calculate = NULL;
- nand->ecc.strength = eccstrength;
-
/* Setup the ecc configurations again */
if (hardware) {
if (eccstrength == 1) {
- nand->ecc.mode = NAND_ECC_HW;
- nand->ecc.layout = &hw_nand_oob;
- nand->ecc.size = 512;
- nand->ecc.bytes = 3;
- nand->ecc.hwctl = omap_enable_hwecc;
- nand->ecc.correct = omap_correct_data;
- nand->ecc.calculate = omap_calculate_ecc;
- omap_hwecc_init(nand);
- printf("1-bit hamming HW ECC selected\n");
+ err = omap_select_ecc_scheme(nand,
+ OMAP_ECC_HAM1_CODE_HW,
+ mtd->writesize, mtd->oobsize);
+ } else if (eccstrength == 8) {
+ err = omap_select_ecc_scheme(nand,
+ OMAP_ECC_BCH8_CODE_HW,
+ mtd->writesize, mtd->oobsize);
+ } else {
+ printf("nand: error: unsupported ECC scheme\n");
+ return -EINVAL;
}
-#if defined(CONFIG_AM33XX) || defined(CONFIG_NAND_OMAP_BCH8)
- else if (eccstrength == 8) {
- nand->ecc.mode = NAND_ECC_HW;
- nand->ecc.layout = &hw_bch8_nand_oob;
- nand->ecc.size = 512;
-#ifdef CONFIG_AM33XX
- nand->ecc.bytes = 14;
- nand->ecc.read_page = omap_read_page_bch;
-#else
- nand->ecc.bytes = 13;
-#endif
- nand->ecc.hwctl = omap_enable_ecc_bch;
- nand->ecc.correct = omap_correct_data_bch;
- nand->ecc.calculate = omap_calculate_ecc_bch;
- omap_hwecc_init_bch(nand, NAND_ECC_READ);
- printf("8-bit BCH HW ECC selected\n");
- }
-#endif
} else {
- nand->ecc.mode = NAND_ECC_SOFT;
- /* Use mtd default settings */
- nand->ecc.layout = NULL;
- nand->ecc.size = 0;
- printf("SW ECC selected\n");
+ err = omap_select_ecc_scheme(nand, OMAP_ECC_HAM1_CODE_SW,
+ mtd->writesize, mtd->oobsize);
}
/* Update NAND handling after ECC mode switch */
- nand_scan_tail(mtd);
-
- nand->options &= ~NAND_OWN_BUFFERS;
+ if (!err)
+ err = nand_scan_tail(mtd);
+ return err;
}
#endif /* CONFIG_SPL_BUILD */
@@ -856,7 +964,7 @@
{
int32_t gpmc_config = 0;
cs = 0;
-
+ int err = 0;
/*
* xloader/Uboot's gpmc configuration would have configured GPMC for
* nand type of memory. The following logic scans and latches on to the
@@ -873,7 +981,7 @@
cs++;
}
if (cs >= GPMC_MAX_CS) {
- printf("NAND: Unable to find NAND settings in "
+ printf("nand: error: Unable to find NAND settings in "
"GPMC Configuration - quitting\n");
return -ENODEV;
}
@@ -885,64 +993,27 @@
nand->IO_ADDR_R = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat;
nand->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
-
- nand->cmd_ctrl = omap_nand_hwcontrol;
- nand->options = NAND_NO_PADDING | NAND_CACHEPRG;
+ nand->priv = &bch_priv;
+ nand->cmd_ctrl = omap_nand_hwcontrol;
+ nand->options |= NAND_NO_PADDING | NAND_CACHEPRG;
/* If we are 16 bit dev, our gpmc config tells us that */
if ((readl(&gpmc_cfg->cs[cs].config1) & 0x3000) == 0x1000)
nand->options |= NAND_BUSWIDTH_16;
nand->chip_delay = 100;
+ nand->ecc.layout = &omap_ecclayout;
-#if defined(CONFIG_AM33XX) || defined(CONFIG_NAND_OMAP_BCH8)
-#ifdef CONFIG_AM33XX
- /* AM33xx uses the ELM */
- /* required in case of BCH */
- elm_init();
+ /* select ECC scheme */
+#if defined(CONFIG_NAND_OMAP_ECCSCHEME)
+ err = omap_select_ecc_scheme(nand, CONFIG_NAND_OMAP_ECCSCHEME,
+ CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE);
#else
- /*
- * Whereas other OMAP based SoC do not have the ELM, they use the BCH
- * SW library.
- */
- bch_priv.control = init_bch(13, 8, 0x201b /* hw polynominal */);
- if (!bch_priv.control) {
- puts("Could not init_bch()\n");
- return -ENODEV;
- }
+ /* pagesize and oobsize are not required to configure sw ecc-scheme */
+ err = omap_select_ecc_scheme(nand, OMAP_ECC_HAM1_CODE_SW,
+ 0, 0);
#endif
- /* BCH info that will be correct for SPL or overridden otherwise. */
- nand->priv = &bch_priv;
-#endif
-
- /* Default ECC mode */
-#if defined(CONFIG_AM33XX) || defined(CONFIG_NAND_OMAP_BCH8)
- nand->ecc.mode = NAND_ECC_HW;
- nand->ecc.layout = &hw_bch8_nand_oob;
- nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE;
- nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES;
- nand->ecc.strength = 8;
- nand->ecc.hwctl = omap_enable_ecc_bch;
- nand->ecc.correct = omap_correct_data_bch;
- nand->ecc.calculate = omap_calculate_ecc_bch;
-#ifdef CONFIG_AM33XX
- nand->ecc.read_page = omap_read_page_bch;
-#endif
- omap_hwecc_init_bch(nand, NAND_ECC_READ);
-#else
-#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_NAND_SOFTECC)
- nand->ecc.mode = NAND_ECC_SOFT;
-#else
- nand->ecc.mode = NAND_ECC_HW;
- nand->ecc.layout = &hw_nand_oob;
- nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE;
- nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES;
- nand->ecc.hwctl = omap_enable_hwecc;
- nand->ecc.correct = omap_correct_data;
- nand->ecc.calculate = omap_calculate_ecc;
- nand->ecc.strength = 1;
- omap_hwecc_init(nand);
-#endif
-#endif
+ if (err)
+ return err;
#ifdef CONFIG_SPL_BUILD
if (nand->options & NAND_BUSWIDTH_16)
diff --git a/drivers/mtd/onenand/onenand_base.c b/drivers/mtd/onenand/onenand_base.c
index 067f8ef..979e4af 100644
--- a/drivers/mtd/onenand/onenand_base.c
+++ b/drivers/mtd/onenand/onenand_base.c
@@ -761,7 +761,8 @@
uint8_t *oob_buf = this->oob_buf;
free = this->ecclayout->oobfree;
- for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES && free->length; i++, free++) {
+ for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES_LARGE && free->length;
+ i++, free++) {
if (readcol >= lastgap)
readcol += free->offset - lastgap;
if (readend >= lastgap)
@@ -770,7 +771,8 @@
}
this->read_bufferram(mtd, 0, ONENAND_SPARERAM, oob_buf, 0, mtd->oobsize);
free = this->ecclayout->oobfree;
- for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES && free->length; i++, free++) {
+ for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES_LARGE && free->length;
+ i++, free++) {
int free_end = free->offset + free->length;
if (free->offset < readend && free_end > readcol) {
int st = max_t(int,free->offset,readcol);
@@ -1356,7 +1358,8 @@
unsigned int i;
free = this->ecclayout->oobfree;
- for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES && free->length; i++, free++) {
+ for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES_LARGE && free->length;
+ i++, free++) {
if (writecol >= lastgap)
writecol += free->offset - lastgap;
if (writeend >= lastgap)
@@ -1364,7 +1367,8 @@
lastgap = free->offset + free->length;
}
free = this->ecclayout->oobfree;
- for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES && free->length; i++, free++) {
+ for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES_LARGE && free->length;
+ i++, free++) {
int free_end = free->offset + free->length;
if (free->offset < writeend && free_end > writecol) {
int st = max_t(int,free->offset,writecol);
@@ -2750,7 +2754,8 @@
* the out of band area
*/
this->ecclayout->oobavail = 0;
- for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES &&
+
+ for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES_LARGE &&
this->ecclayout->oobfree[i].length; i++)
this->ecclayout->oobavail +=
this->ecclayout->oobfree[i].length;
diff --git a/drivers/net/designware.c b/drivers/net/designware.c
index 8413d57..22155b4 100644
--- a/drivers/net/designware.c
+++ b/drivers/net/designware.c
@@ -96,7 +96,7 @@
ulong start;
int timeout = CONFIG_MACRESET_TIMEOUT;
- writel(DMAMAC_SRST, &dma_p->busmode);
+ writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode);
if (priv->interface != PHY_INTERFACE_MODE_RGMII)
writel(MII_PORTSELECT, &mac_p->conf);
diff --git a/drivers/net/designware.h b/drivers/net/designware.h
index e80002a..5440c92 100644
--- a/drivers/net/designware.h
+++ b/drivers/net/designware.h
@@ -112,7 +112,7 @@
u32 dmamac_cntl;
void *dmamac_addr;
struct dmamacdescr *dmamac_next;
-};
+} __aligned(16);
/*
* txrx_status definitions
@@ -224,8 +224,7 @@
u32 tx_currdescnum;
u32 rx_currdescnum;
u32 phy_configured;
- int link_printed;
- u32 padding;
+ u32 link_printed;
struct dmamacdescr tx_mac_descrtable[CONFIG_TX_DESCR_NUM];
struct dmamacdescr rx_mac_descrtable[CONFIG_RX_DESCR_NUM];
@@ -237,7 +236,7 @@
struct eth_dma_regs *dma_regs_p;
struct eth_device *dev;
-} __attribute__ ((aligned(8)));
+};
/* Speed specific definitions */
#define SPEED_10M 1
diff --git a/drivers/net/dm9000x.c b/drivers/net/dm9000x.c
index f7170e0..b68d808 100644
--- a/drivers/net/dm9000x.c
+++ b/drivers/net/dm9000x.c
@@ -342,6 +342,15 @@
DM9000_iow(DM9000_ISR, ISR_ROOS | ISR_ROS | ISR_PTS | ISR_PRS);
printf("MAC: %pM\n", dev->enetaddr);
+ if (!is_valid_ether_addr(dev->enetaddr)) {
+#ifdef CONFIG_RANDOM_MACADDR
+ printf("Bad MAC address (uninitialized EEPROM?), randomizing\n");
+ eth_random_enetaddr(dev->enetaddr);
+ printf("MAC: %pM\n", dev->enetaddr);
+#else
+ printf("WARNING: Bad MAC address (uninitialized EEPROM?)\n");
+#endif
+ }
/* fill device MAC address registers */
for (i = 0, oft = DM9000_PAR; i < 6; i++, oft++)
diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c
index 57aa53d..9a66e68 100644
--- a/drivers/net/e1000.c
+++ b/drivers/net/e1000.c
@@ -114,12 +114,13 @@
static int32_t e1000_phy_hw_reset(struct e1000_hw *hw);
static int e1000_phy_reset(struct e1000_hw *hw);
static int e1000_detect_gig_phy(struct e1000_hw *hw);
-static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
static void e1000_set_media_type(struct e1000_hw *hw);
static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask);
static int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
+#ifndef CONFIG_E1000_NO_NVM
+static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
static int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
uint16_t words,
uint16_t *data);
@@ -885,6 +886,7 @@
return -E1000_ERR_EEPROM;
}
+#endif /* CONFIG_E1000_NO_NVM */
/*****************************************************************************
* Set PHY to class A mode
@@ -897,6 +899,7 @@
static int32_t
e1000_set_phy_mode(struct e1000_hw *hw)
{
+#ifndef CONFIG_E1000_NO_NVM
int32_t ret_val;
uint16_t eeprom_data;
@@ -923,10 +926,11 @@
hw->phy_reset_disable = false;
}
}
-
+#endif
return E1000_SUCCESS;
}
+#ifndef CONFIG_E1000_NO_NVM
/***************************************************************************
*
* Obtaining software semaphore bit (SMBI) before resetting PHY.
@@ -965,6 +969,7 @@
return E1000_SUCCESS;
}
+#endif
/***************************************************************************
* This function clears HW semaphore bits.
@@ -977,6 +982,7 @@
static void
e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
{
+#ifndef CONFIG_E1000_NO_NVM
uint32_t swsm;
DEBUGFUNC();
@@ -991,6 +997,7 @@
} else
swsm &= ~(E1000_SWSM_SWESMBI);
E1000_WRITE_REG(hw, SWSM, swsm);
+#endif
}
/***************************************************************************
@@ -1007,6 +1014,7 @@
static int32_t
e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
{
+#ifndef CONFIG_E1000_NO_NVM
int32_t timeout;
uint32_t swsm;
@@ -1043,7 +1051,7 @@
"SWESMBI bit is set.\n");
return -E1000_ERR_EEPROM;
}
-
+#endif
return E1000_SUCCESS;
}
@@ -1097,6 +1105,7 @@
}
}
+#ifndef CONFIG_E1000_NO_NVM
/******************************************************************************
* Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
* second function of dual function devices
@@ -1136,6 +1145,7 @@
#endif
return 0;
}
+#endif
/******************************************************************************
* Initializes receive address filters.
@@ -1764,9 +1774,11 @@
e1000_setup_link(struct eth_device *nic)
{
struct e1000_hw *hw = nic->priv;
- uint32_t ctrl_ext;
int32_t ret_val;
+#ifndef CONFIG_E1000_NO_NVM
+ uint32_t ctrl_ext;
uint16_t eeprom_data;
+#endif
DEBUGFUNC();
@@ -1775,6 +1787,7 @@
if (e1000_check_phy_reset_block(hw))
return E1000_SUCCESS;
+#ifndef CONFIG_E1000_NO_NVM
/* Read and store word 0x0F of the EEPROM. This word contains bits
* that determine the hardware's default PAUSE (flow control) mode,
* a bit that determines whether the HW defaults to enabling or
@@ -1788,7 +1801,7 @@
DEBUGOUT("EEPROM Read Error\n");
return -E1000_ERR_EEPROM;
}
-
+#endif
if (hw->fc == e1000_fc_default) {
switch (hw->mac_type) {
case e1000_ich8lan:
@@ -1797,6 +1810,7 @@
hw->fc = e1000_fc_full;
break;
default:
+#ifndef CONFIG_E1000_NO_NVM
ret_val = e1000_read_eeprom(hw,
EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data);
if (ret_val) {
@@ -1809,6 +1823,7 @@
EEPROM_WORD0F_ASM_DIR)
hw->fc = e1000_fc_tx_pause;
else
+#endif
hw->fc = e1000_fc_full;
break;
}
@@ -1828,6 +1843,7 @@
DEBUGOUT("After fix-ups FlowControl is now = %x\n", hw->fc);
+#ifndef CONFIG_E1000_NO_NVM
/* Take the 4 bits from EEPROM word 0x0F that determine the initial
* polarity value for the SW controlled pins, and setup the
* Extended Device Control reg with that info.
@@ -1840,6 +1856,7 @@
SWDPIO__EXT_SHIFT);
E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
}
+#endif
/* Call the necessary subroutine to configure the link. */
ret_val = (hw->media_type == e1000_media_type_fiber) ?
@@ -5196,6 +5213,7 @@
e1000_reset_hw(hw);
list_add_tail(&hw->list_node, &e1000_hw_list);
+#ifndef CONFIG_E1000_NO_NVM
/* Validate the EEPROM and get chipset information */
#if !defined(CONFIG_MVBC_1G)
if (e1000_init_eeprom_params(hw)) {
@@ -5206,11 +5224,17 @@
continue;
#endif
e1000_read_mac_addr(nic);
+#endif
e1000_get_bus_type(hw);
+#ifndef CONFIG_E1000_NO_NVM
printf("e1000: %02x:%02x:%02x:%02x:%02x:%02x\n ",
nic->enetaddr[0], nic->enetaddr[1], nic->enetaddr[2],
nic->enetaddr[3], nic->enetaddr[4], nic->enetaddr[5]);
+#else
+ memset(nic->enetaddr, 0, 6);
+ printf("e1000: no NVM\n");
+#endif
/* Set up the function pointers and register the device */
nic->init = e1000_init;
diff --git a/drivers/net/e1000.h b/drivers/net/e1000.h
index 25884f5..ff87af2 100644
--- a/drivers/net/e1000.h
+++ b/drivers/net/e1000.h
@@ -63,11 +63,14 @@
/* Internal E1000 helper functions */
struct e1000_hw *e1000_find_card(unsigned int cardnum);
+
+#ifndef CONFIG_E1000_NO_NVM
int32_t e1000_acquire_eeprom(struct e1000_hw *hw);
void e1000_standby_eeprom(struct e1000_hw *hw);
void e1000_release_eeprom(struct e1000_hw *hw);
void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t *eecd);
void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t *eecd);
+#endif
#ifdef CONFIG_E1000_SPI
int do_e1000_spi(cmd_tbl_t *cmdtp, struct e1000_hw *hw,
@@ -1019,6 +1022,7 @@
uint64_t tsctfc;
};
+#ifndef CONFIG_E1000_NO_NVM
struct e1000_eeprom_info {
e1000_eeprom_type type;
uint16_t word_size;
@@ -1029,6 +1033,7 @@
bool use_eerd;
bool use_eewr;
};
+#endif
typedef enum {
e1000_smart_speed_default = 0,
@@ -1081,10 +1086,14 @@
uint32_t io_base;
#endif
uint32_t asf_firmware_present;
+#ifndef CONFIG_E1000_NO_NVM
uint32_t eeprom_semaphore_present;
+#endif
uint32_t swfw_sync_present;
uint32_t swfwhw_semaphore_present;
+#ifndef CONFIG_E1000_NO_NVM
struct e1000_eeprom_info eeprom;
+#endif
e1000_ms_type master_slave;
e1000_ms_type original_master_slave;
e1000_ffe_config ffe_config_state;
diff --git a/drivers/net/fm/Makefile b/drivers/net/fm/Makefile
index bec86c1..ee5d768 100644
--- a/drivers/net/fm/Makefile
+++ b/drivers/net/fm/Makefile
@@ -4,7 +4,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifdef CONFIG_FMAN_ENET
obj-y += dtsec.o
obj-y += eth.o
obj-y += fm.o
@@ -26,8 +25,12 @@
obj-$(CONFIG_PPC_P5020) += p5020.o
obj-$(CONFIG_PPC_P5040) += p5040.o
obj-$(CONFIG_PPC_T1040) += t1040.o
+obj-$(CONFIG_PPC_T1042) += t1040.o
+obj-$(CONFIG_PPC_T1020) += t1040.o
+obj-$(CONFIG_PPC_T1022) += t1040.o
+obj-$(CONFIG_PPC_T2080) += t2080.o
+obj-$(CONFIG_PPC_T2081) += t2080.o
obj-$(CONFIG_PPC_T4240) += t4240.o
obj-$(CONFIG_PPC_T4160) += t4240.o
obj-$(CONFIG_PPC_B4420) += b4860.o
obj-$(CONFIG_PPC_B4860) += b4860.o
-endif
diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c
index cb099cd..218a5ed 100644
--- a/drivers/net/fm/eth.c
+++ b/drivers/net/fm/eth.c
@@ -557,8 +557,16 @@
num = fm_eth->num;
#ifdef CONFIG_SYS_FMAN_V3
- if (fm_eth->type == FM_ETH_10G_E)
- num += 8;
+ if (fm_eth->type == FM_ETH_10G_E) {
+ /* 10GEC1/10GEC2 use mEMAC9/mEMAC10
+ * 10GEC3/10GEC4 use mEMAC1/mEMAC2
+ * so it needs to change the num.
+ */
+ if (fm_eth->num >= 2)
+ num -= 2;
+ else
+ num += 8;
+ }
base = ®->memac[num].fm_memac;
phyregs = ®->memac[num].fm_memac_mdio;
#else
diff --git a/drivers/net/fm/fm.h b/drivers/net/fm/fm.h
index 3ec49a4..43de114 100644
--- a/drivers/net/fm/fm.h
+++ b/drivers/net/fm/fm.h
@@ -18,9 +18,11 @@
#define RX_PORT_1G_BASE 0x08
#define MAX_NUM_RX_PORT_1G CONFIG_SYS_NUM_FM1_DTSEC
#define RX_PORT_10G_BASE 0x10
+#define RX_PORT_10G_BASE2 0x08
#define TX_PORT_1G_BASE 0x28
#define MAX_NUM_TX_PORT_1G CONFIG_SYS_NUM_FM1_DTSEC
#define TX_PORT_10G_BASE 0x30
+#define TX_PORT_10G_BASE2 0x28
#define MIIM_TIMEOUT 0xFFFF
struct fm_muram {
diff --git a/drivers/net/fm/init.c b/drivers/net/fm/init.c
index 35edd7a..cd787f4 100644
--- a/drivers/net/fm/init.c
+++ b/drivers/net/fm/init.c
@@ -64,6 +64,12 @@
#if (CONFIG_SYS_NUM_FM1_10GEC >= 2)
FM_TGEC_INFO_INITIALIZER(1, 2),
#endif
+#if (CONFIG_SYS_NUM_FM1_10GEC >= 3)
+ FM_TGEC_INFO_INITIALIZER2(1, 3),
+#endif
+#if (CONFIG_SYS_NUM_FM1_10GEC >= 4)
+ FM_TGEC_INFO_INITIALIZER2(1, 4),
+#endif
#if (CONFIG_SYS_NUM_FM2_10GEC >= 1)
FM_TGEC_INFO_INITIALIZER(2, 1),
#endif
@@ -239,10 +245,14 @@
* FM1_10GEC1 is enabled and FM1_DTSEC9 is disabled, ensure that the
* dual-role MAC is not disabled, ditto for other dual-role MACs.
*/
- if (((info->port == FM1_DTSEC9) && (PORT_IS_ENABLED(FM1_10GEC1))) ||
- ((info->port == FM1_DTSEC10) && (PORT_IS_ENABLED(FM1_10GEC2))) ||
- ((info->port == FM1_10GEC1) && (PORT_IS_ENABLED(FM1_DTSEC9))) ||
- ((info->port == FM1_10GEC2) && (PORT_IS_ENABLED(FM1_DTSEC10)))
+ if (((info->port == FM1_DTSEC9) && (PORT_IS_ENABLED(FM1_10GEC1))) ||
+ ((info->port == FM1_DTSEC10) && (PORT_IS_ENABLED(FM1_10GEC2))) ||
+ ((info->port == FM1_DTSEC1) && (PORT_IS_ENABLED(FM1_10GEC3))) ||
+ ((info->port == FM1_DTSEC2) && (PORT_IS_ENABLED(FM1_10GEC4))) ||
+ ((info->port == FM1_10GEC1) && (PORT_IS_ENABLED(FM1_DTSEC9))) ||
+ ((info->port == FM1_10GEC2) && (PORT_IS_ENABLED(FM1_DTSEC10))) ||
+ ((info->port == FM1_10GEC3) && (PORT_IS_ENABLED(FM1_DTSEC1))) ||
+ ((info->port == FM1_10GEC4) && (PORT_IS_ENABLED(FM1_DTSEC2)))
#if (CONFIG_SYS_NUM_FMAN == 2)
||
((info->port == FM2_DTSEC9) && (PORT_IS_ENABLED(FM2_10GEC1))) ||
diff --git a/drivers/net/fm/t2080.c b/drivers/net/fm/t2080.c
new file mode 100644
index 0000000..b5c1e9f
--- /dev/null
+++ b/drivers/net/fm/t2080.c
@@ -0,0 +1,91 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * Shengzhou Liu <Shengzhou.Liu@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <phy.h>
+#include <fm_eth.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_serdes.h>
+
+u32 port_to_devdisr[] = {
+ [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
+ [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2,
+ [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3,
+ [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4,
+ [FM1_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC1_5,
+ [FM1_DTSEC6] = FSL_CORENET_DEVDISR2_DTSEC1_6,
+ [FM1_DTSEC9] = FSL_CORENET_DEVDISR2_DTSEC1_9,
+ [FM1_DTSEC10] = FSL_CORENET_DEVDISR2_DTSEC1_10,
+ [FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1_1,
+ [FM1_10GEC2] = FSL_CORENET_DEVDISR2_10GEC1_2,
+ [FM1_10GEC3] = FSL_CORENET_DEVDISR2_10GEC1_3,
+ [FM1_10GEC4] = FSL_CORENET_DEVDISR2_10GEC1_4,
+};
+
+static int is_device_disabled(enum fm_port port)
+{
+ ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 devdisr2 = in_be32(&gur->devdisr2);
+
+ return port_to_devdisr[port] & devdisr2;
+}
+
+void fman_disable_port(enum fm_port port)
+{
+ ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+ setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
+}
+
+phy_interface_t fman_port_enet_if(enum fm_port port)
+{
+ ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
+
+ if (is_device_disabled(port))
+ return PHY_INTERFACE_MODE_NONE;
+
+ if ((port == FM1_10GEC1 || port == FM1_10GEC2 ||
+ port == FM1_10GEC3 || port == FM1_10GEC4) &&
+ ((is_serdes_configured(XAUI_FM1_MAC9)) ||
+ (is_serdes_configured(XFI_FM1_MAC1)) ||
+ (is_serdes_configured(XFI_FM1_MAC2)) ||
+ (is_serdes_configured(XFI_FM1_MAC9)) ||
+ (is_serdes_configured(XFI_FM1_MAC10))))
+ return PHY_INTERFACE_MODE_XGMII;
+
+ if ((port == FM1_DTSEC3) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) ==
+ FSL_CORENET_RCWSR13_EC1_DTSEC3_RGMII))
+ return PHY_INTERFACE_MODE_RGMII;
+
+ if ((port == FM1_DTSEC4) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
+ FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII))
+ return PHY_INTERFACE_MODE_RGMII;
+
+ if ((port == FM1_DTSEC10) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
+ FSL_CORENET_RCWSR13_EC2_DTSEC10_RGMII))
+ return PHY_INTERFACE_MODE_RGMII;
+
+ switch (port) {
+ case FM1_DTSEC1:
+ case FM1_DTSEC2:
+ case FM1_DTSEC3:
+ case FM1_DTSEC4:
+ case FM1_DTSEC5:
+ case FM1_DTSEC6:
+ case FM1_DTSEC9:
+ case FM1_DTSEC10:
+ if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
+ return PHY_INTERFACE_MODE_SGMII;
+ break;
+ default:
+ return PHY_INTERFACE_MODE_NONE;
+ }
+
+ return PHY_INTERFACE_MODE_NONE;
+}
diff --git a/drivers/net/fsl_mdio.c b/drivers/net/fsl_mdio.c
index ce36bd7..1d88e65 100644
--- a/drivers/net/fsl_mdio.c
+++ b/drivers/net/fsl_mdio.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ * Copyright 2009-2010, 2013 Freescale Semiconductor, Inc.
* Jun-jie Zhang <b18070@freescale.com>
* Mingkai Hu <Mingkai.hu@freescale.com>
*
@@ -13,7 +13,7 @@
#include <asm/errno.h>
#include <asm/fsl_enet.h>
-void tsec_local_mdio_write(struct tsec_mii_mng *phyregs, int port_addr,
+void tsec_local_mdio_write(struct tsec_mii_mng __iomem *phyregs, int port_addr,
int dev_addr, int regnum, int value)
{
int timeout = 1000000;
@@ -26,7 +26,7 @@
;
}
-int tsec_local_mdio_read(struct tsec_mii_mng *phyregs, int port_addr,
+int tsec_local_mdio_read(struct tsec_mii_mng __iomem *phyregs, int port_addr,
int dev_addr, int regnum)
{
int value;
@@ -57,7 +57,8 @@
static int fsl_pq_mdio_reset(struct mii_dev *bus)
{
- struct tsec_mii_mng *regs = bus->priv;
+ struct tsec_mii_mng __iomem *regs =
+ (struct tsec_mii_mng __iomem *)bus->priv;
/* Reset MII (due to new addresses) */
out_be32(®s->miimcfg, MIIMCFG_RESET_MGMT);
@@ -72,7 +73,8 @@
int tsec_phy_read(struct mii_dev *bus, int addr, int dev_addr, int regnum)
{
- struct tsec_mii_mng *phyregs = bus->priv;
+ struct tsec_mii_mng __iomem *phyregs =
+ (struct tsec_mii_mng __iomem *)bus->priv;
return tsec_local_mdio_read(phyregs, addr, dev_addr, regnum);
}
@@ -80,7 +82,8 @@
int tsec_phy_write(struct mii_dev *bus, int addr, int dev_addr, int regnum,
u16 value)
{
- struct tsec_mii_mng *phyregs = bus->priv;
+ struct tsec_mii_mng __iomem *phyregs =
+ (struct tsec_mii_mng __iomem *)bus->priv;
tsec_local_mdio_write(phyregs, addr, dev_addr, regnum, value);
@@ -101,7 +104,7 @@
bus->reset = fsl_pq_mdio_reset;
sprintf(bus->name, info->name);
- bus->priv = info->regs;
+ bus->priv = (void *)info->regs;
return mdio_register(bus);
}
diff --git a/drivers/net/mvgbe.c b/drivers/net/mvgbe.c
index 6c901d1..0cd06b6 100644
--- a/drivers/net/mvgbe.c
+++ b/drivers/net/mvgbe.c
@@ -420,8 +420,9 @@
{
struct mvgbe_device *dmvgbe = to_mvgbe(dev);
struct mvgbe_registers *regs = dmvgbe->regs;
-#if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \
- && defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
+#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) && \
+ !defined(CONFIG_PHYLIB) && \
+ defined(CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
int i;
#endif
/* setup RX rings */
diff --git a/drivers/net/npe/Makefile b/drivers/net/npe/Makefile
index 7fa5ea6..0779255 100644
--- a/drivers/net/npe/Makefile
+++ b/drivers/net/npe/Makefile
@@ -8,9 +8,8 @@
LOCAL_CFLAGS += -I$(TOPDIR)/drivers/net/npe/include -DCONFIG_IXP425_COMPONENT_ETHDB -D__linux
CFLAGS += $(LOCAL_CFLAGS)
CPPFLAGS += $(LOCAL_CFLAGS) # needed for depend
-HOSTCFLAGS += $(LOCAL_CFLAGS)
-obj-$(CONFIG_IXP4XX_NPE) := npe.o \
+obj-y := npe.o \
miiphy.o \
IxOsalBufferMgt.o \
IxOsalIoMem.o \
diff --git a/drivers/net/pcnet.c b/drivers/net/pcnet.c
index 283cb48..71a3110 100644
--- a/drivers/net/pcnet.c
+++ b/drivers/net/pcnet.c
@@ -89,39 +89,39 @@
#define PCNET_RESET 0x14
#define PCNET_BDP 0x16
-static u16 pcnet_read_csr (struct eth_device *dev, int index)
+static u16 pcnet_read_csr(struct eth_device *dev, int index)
{
- outw (index, dev->iobase + PCNET_RAP);
- return inw (dev->iobase + PCNET_RDP);
+ outw(index, dev->iobase + PCNET_RAP);
+ return inw(dev->iobase + PCNET_RDP);
}
-static void pcnet_write_csr (struct eth_device *dev, int index, u16 val)
+static void pcnet_write_csr(struct eth_device *dev, int index, u16 val)
{
- outw (index, dev->iobase + PCNET_RAP);
- outw (val, dev->iobase + PCNET_RDP);
+ outw(index, dev->iobase + PCNET_RAP);
+ outw(val, dev->iobase + PCNET_RDP);
}
-static u16 pcnet_read_bcr (struct eth_device *dev, int index)
+static u16 pcnet_read_bcr(struct eth_device *dev, int index)
{
- outw (index, dev->iobase + PCNET_RAP);
- return inw (dev->iobase + PCNET_BDP);
+ outw(index, dev->iobase + PCNET_RAP);
+ return inw(dev->iobase + PCNET_BDP);
}
-static void pcnet_write_bcr (struct eth_device *dev, int index, u16 val)
+static void pcnet_write_bcr(struct eth_device *dev, int index, u16 val)
{
- outw (index, dev->iobase + PCNET_RAP);
- outw (val, dev->iobase + PCNET_BDP);
+ outw(index, dev->iobase + PCNET_RAP);
+ outw(val, dev->iobase + PCNET_BDP);
}
-static void pcnet_reset (struct eth_device *dev)
+static void pcnet_reset(struct eth_device *dev)
{
- inw (dev->iobase + PCNET_RESET);
+ inw(dev->iobase + PCNET_RESET);
}
-static int pcnet_check (struct eth_device *dev)
+static int pcnet_check(struct eth_device *dev)
{
- outw (88, dev->iobase + PCNET_RAP);
- return (inw (dev->iobase + PCNET_RAP) == 88);
+ outw(88, dev->iobase + PCNET_RAP);
+ return inw(dev->iobase + PCNET_RAP) == 88;
}
static int pcnet_init (struct eth_device *dev, bd_t * bis);
@@ -139,63 +139,64 @@
};
-int pcnet_initialize (bd_t * bis)
+int pcnet_initialize(bd_t *bis)
{
pci_dev_t devbusfn;
struct eth_device *dev;
u16 command, status;
int dev_nr = 0;
- PCNET_DEBUG1 ("\npcnet_initialize...\n");
+ PCNET_DEBUG1("\npcnet_initialize...\n");
for (dev_nr = 0;; dev_nr++) {
/*
* Find the PCnet PCI device(s).
*/
- if ((devbusfn = pci_find_devices (supported, dev_nr)) < 0) {
+ devbusfn = pci_find_devices(supported, dev_nr);
+ if (devbusfn < 0)
break;
- }
/*
* Allocate and pre-fill the device structure.
*/
- dev = (struct eth_device *) malloc (sizeof *dev);
+ dev = (struct eth_device *)malloc(sizeof(*dev));
if (!dev) {
printf("pcnet: Can not allocate memory\n");
break;
}
memset(dev, 0, sizeof(*dev));
- dev->priv = (void *) devbusfn;
- sprintf (dev->name, "pcnet#%d", dev_nr);
+ dev->priv = (void *)devbusfn;
+ sprintf(dev->name, "pcnet#%d", dev_nr);
/*
* Setup the PCI device.
*/
- pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0,
- (unsigned int *) &dev->iobase);
- dev->iobase=pci_io_to_phys (devbusfn, dev->iobase);
+ pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0,
+ (unsigned int *)&dev->iobase);
+ dev->iobase = pci_io_to_phys(devbusfn, dev->iobase);
dev->iobase &= ~0xf;
- PCNET_DEBUG1 ("%s: devbusfn=0x%x iobase=0x%x: ",
- dev->name, devbusfn, dev->iobase);
+ PCNET_DEBUG1("%s: devbusfn=0x%x iobase=0x%x: ",
+ dev->name, devbusfn, dev->iobase);
command = PCI_COMMAND_IO | PCI_COMMAND_MASTER;
- pci_write_config_word (devbusfn, PCI_COMMAND, command);
- pci_read_config_word (devbusfn, PCI_COMMAND, &status);
+ pci_write_config_word(devbusfn, PCI_COMMAND, command);
+ pci_read_config_word(devbusfn, PCI_COMMAND, &status);
if ((status & command) != command) {
- printf ("%s: Couldn't enable IO access or Bus Mastering\n", dev->name);
- free (dev);
+ printf("%s: Couldn't enable IO access or Bus Mastering\n",
+ dev->name);
+ free(dev);
continue;
}
- pci_write_config_byte (devbusfn, PCI_LATENCY_TIMER, 0x40);
+ pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x40);
/*
* Probe the PCnet chip.
*/
- if (pcnet_probe (dev, bis, dev_nr) < 0) {
- free (dev);
+ if (pcnet_probe(dev, bis, dev_nr) < 0) {
+ free(dev);
continue;
}
@@ -207,15 +208,15 @@
dev->send = pcnet_send;
dev->recv = pcnet_recv;
- eth_register (dev);
+ eth_register(dev);
}
- udelay (10 * 1000);
+ udelay(10 * 1000);
return dev_nr;
}
-static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_nr)
+static int pcnet_probe(struct eth_device *dev, bd_t *bis, int dev_nr)
{
int chip_version;
char *chipname;
@@ -225,17 +226,17 @@
#endif
/* Reset the PCnet controller */
- pcnet_reset (dev);
+ pcnet_reset(dev);
/* Check if register access is working */
- if (pcnet_read_csr (dev, 0) != 4 || !pcnet_check (dev)) {
- printf ("%s: CSR register access check failed\n", dev->name);
+ if (pcnet_read_csr(dev, 0) != 4 || !pcnet_check(dev)) {
+ printf("%s: CSR register access check failed\n", dev->name);
return -1;
}
/* Identify the chip */
chip_version =
- pcnet_read_csr (dev, 88) | (pcnet_read_csr (dev, 89) << 16);
+ pcnet_read_csr(dev, 88) | (pcnet_read_csr(dev, 89) << 16);
if ((chip_version & 0xfff) != 0x003)
return -1;
chip_version = (chip_version >> 12) & 0xffff;
@@ -254,12 +255,12 @@
break;
#endif
default:
- printf ("%s: PCnet version %#x not supported\n",
- dev->name, chip_version);
+ printf("%s: PCnet version %#x not supported\n",
+ dev->name, chip_version);
return -1;
}
- PCNET_DEBUG1 ("AMD %s\n", chipname);
+ PCNET_DEBUG1("AMD %s\n", chipname);
#ifdef PCNET_HAS_PROM
/*
@@ -270,7 +271,7 @@
for (i = 0; i < 3; i++) {
unsigned int val;
- val = pcnet_read_csr (dev, i + 12) & 0x0ffff;
+ val = pcnet_read_csr(dev, i + 12) & 0x0ffff;
/* There may be endianness issues here. */
dev->enetaddr[2 * i] = val & 0x0ff;
dev->enetaddr[2 * i + 1] = (val >> 8) & 0x0ff;
@@ -280,35 +281,40 @@
return 0;
}
-static int pcnet_init (struct eth_device *dev, bd_t * bis)
+static int pcnet_init(struct eth_device *dev, bd_t *bis)
{
int i, val;
u32 addr;
- PCNET_DEBUG1 ("%s: pcnet_init...\n", dev->name);
+ PCNET_DEBUG1("%s: pcnet_init...\n", dev->name);
/* Switch pcnet to 32bit mode */
- pcnet_write_bcr (dev, 20, 2);
-
-#ifdef CONFIG_PN62
- /* Setup LED registers */
- val = pcnet_read_bcr (dev, 2) | 0x1000;
- pcnet_write_bcr (dev, 2, val); /* enable LEDPE */
- pcnet_write_bcr (dev, 4, 0x5080); /* 100MBit */
- pcnet_write_bcr (dev, 5, 0x40c0); /* LNKSE */
- pcnet_write_bcr (dev, 6, 0x4090); /* TX Activity */
- pcnet_write_bcr (dev, 7, 0x4084); /* RX Activity */
-#endif
+ pcnet_write_bcr(dev, 20, 2);
/* Set/reset autoselect bit */
- val = pcnet_read_bcr (dev, 2) & ~2;
+ val = pcnet_read_bcr(dev, 2) & ~2;
val |= 2;
- pcnet_write_bcr (dev, 2, val);
+ pcnet_write_bcr(dev, 2, val);
/* Enable auto negotiate, setup, disable fd */
- val = pcnet_read_bcr (dev, 32) & ~0x98;
+ val = pcnet_read_bcr(dev, 32) & ~0x98;
val |= 0x20;
- pcnet_write_bcr (dev, 32, val);
+ pcnet_write_bcr(dev, 32, val);
+
+ /*
+ * Enable NOUFLO on supported controllers, with the transmit
+ * start point set to the full packet. This will cause entire
+ * packets to be buffered by the ethernet controller before
+ * transmission, eliminating underflows which are common on
+ * slower devices. Controllers which do not support NOUFLO will
+ * simply be left with a larger transmit FIFO threshold.
+ */
+ val = pcnet_read_bcr(dev, 18);
+ val |= 1 << 11;
+ pcnet_write_bcr(dev, 18, val);
+ val = pcnet_read_csr(dev, 80);
+ val |= 0x3 << 10;
+ pcnet_write_csr(dev, 80, val);
/*
* We only maintain one structure because the drivers will never
@@ -316,12 +322,12 @@
* must be aligned on 16-byte boundaries.
*/
if (lp == NULL) {
- addr = (u32) malloc (sizeof (pcnet_priv_t) + 0x10);
+ addr = (u32)malloc(sizeof(pcnet_priv_t) + 0x10);
addr = (addr + 0xf) & ~0xf;
- lp = (pcnet_priv_t *) addr;
+ lp = (pcnet_priv_t *)addr;
}
- lp->init_block.mode = cpu_to_le16 (0x0000);
+ lp->init_block.mode = cpu_to_le16(0x0000);
lp->init_block.filter[0] = 0x00000000;
lp->init_block.filter[1] = 0x00000000;
@@ -330,9 +336,9 @@
*/
lp->cur_rx = 0;
for (i = 0; i < RX_RING_SIZE; i++) {
- lp->rx_ring[i].base = PCI_TO_MEM_LE (dev, lp->rx_buf[i]);
- lp->rx_ring[i].buf_length = cpu_to_le16 (-PKT_BUF_SZ);
- lp->rx_ring[i].status = cpu_to_le16 (0x8000);
+ lp->rx_ring[i].base = PCI_TO_MEM_LE(dev, lp->rx_buf[i]);
+ lp->rx_ring[i].buf_length = cpu_to_le16(-PKT_BUF_SZ);
+ lp->rx_ring[i].status = cpu_to_le16(0x8000);
PCNET_DEBUG1
("Rx%d: base=0x%x buf_length=0x%hx status=0x%hx\n", i,
lp->rx_ring[i].base, lp->rx_ring[i].buf_length,
@@ -352,48 +358,49 @@
/*
* Setup Init Block.
*/
- PCNET_DEBUG1 ("Init block at 0x%p: MAC", &lp->init_block);
+ PCNET_DEBUG1("Init block at 0x%p: MAC", &lp->init_block);
for (i = 0; i < 6; i++) {
lp->init_block.phys_addr[i] = dev->enetaddr[i];
- PCNET_DEBUG1 (" %02x", lp->init_block.phys_addr[i]);
+ PCNET_DEBUG1(" %02x", lp->init_block.phys_addr[i]);
}
- lp->init_block.tlen_rlen = cpu_to_le16 (TX_RING_LEN_BITS |
- RX_RING_LEN_BITS);
- lp->init_block.rx_ring = PCI_TO_MEM_LE (dev, lp->rx_ring);
- lp->init_block.tx_ring = PCI_TO_MEM_LE (dev, lp->tx_ring);
+ lp->init_block.tlen_rlen = cpu_to_le16(TX_RING_LEN_BITS |
+ RX_RING_LEN_BITS);
+ lp->init_block.rx_ring = PCI_TO_MEM_LE(dev, lp->rx_ring);
+ lp->init_block.tx_ring = PCI_TO_MEM_LE(dev, lp->tx_ring);
+ flush_dcache_range((unsigned long)lp, (unsigned long)&lp->rx_buf);
- PCNET_DEBUG1 ("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n",
- lp->init_block.tlen_rlen,
- lp->init_block.rx_ring, lp->init_block.tx_ring);
+ PCNET_DEBUG1("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n",
+ lp->init_block.tlen_rlen,
+ lp->init_block.rx_ring, lp->init_block.tx_ring);
/*
* Tell the controller where the Init Block is located.
*/
- addr = PCI_TO_MEM (dev, &lp->init_block);
- pcnet_write_csr (dev, 1, addr & 0xffff);
- pcnet_write_csr (dev, 2, (addr >> 16) & 0xffff);
+ addr = PCI_TO_MEM(dev, &lp->init_block);
+ pcnet_write_csr(dev, 1, addr & 0xffff);
+ pcnet_write_csr(dev, 2, (addr >> 16) & 0xffff);
- pcnet_write_csr (dev, 4, 0x0915);
- pcnet_write_csr (dev, 0, 0x0001); /* start */
+ pcnet_write_csr(dev, 4, 0x0915);
+ pcnet_write_csr(dev, 0, 0x0001); /* start */
/* Wait for Init Done bit */
for (i = 10000; i > 0; i--) {
- if (pcnet_read_csr (dev, 0) & 0x0100)
+ if (pcnet_read_csr(dev, 0) & 0x0100)
break;
- udelay (10);
+ udelay(10);
}
if (i <= 0) {
- printf ("%s: TIMEOUT: controller init failed\n", dev->name);
- pcnet_reset (dev);
+ printf("%s: TIMEOUT: controller init failed\n", dev->name);
+ pcnet_reset(dev);
return -1;
}
/*
* Finally start network controller operation.
*/
- pcnet_write_csr (dev, 0, 0x0002);
+ pcnet_write_csr(dev, 0, 0x0002);
return 0;
}
@@ -403,20 +410,25 @@
int i, status;
struct pcnet_tx_head *entry = &lp->tx_ring[lp->cur_tx];
- PCNET_DEBUG2 ("Tx%d: %d bytes from 0x%p ", lp->cur_tx, pkt_len,
- packet);
+ PCNET_DEBUG2("Tx%d: %d bytes from 0x%p ", lp->cur_tx, pkt_len,
+ packet);
+
+ flush_dcache_range((unsigned long)packet,
+ (unsigned long)packet + pkt_len);
/* Wait for completion by testing the OWN bit */
for (i = 1000; i > 0; i--) {
- status = le16_to_cpu (entry->status);
+ invalidate_dcache_range((unsigned long)entry,
+ (unsigned long)entry + sizeof(*entry));
+ status = le16_to_cpu(entry->status);
if ((status & 0x8000) == 0)
break;
- udelay (100);
- PCNET_DEBUG2 (".");
+ udelay(100);
+ PCNET_DEBUG2(".");
}
if (i <= 0) {
- printf ("%s: TIMEOUT: Tx%d failed (status = 0x%x)\n",
- dev->name, lp->cur_tx, status);
+ printf("%s: TIMEOUT: Tx%d failed (status = 0x%x)\n",
+ dev->name, lp->cur_tx, status);
pkt_len = 0;
goto failure;
}
@@ -426,19 +438,21 @@
* set the status with the "ownership" bits last.
*/
status = 0x8300;
- entry->length = le16_to_cpu (-pkt_len);
+ entry->length = cpu_to_le16(-pkt_len);
entry->misc = 0x00000000;
- entry->base = PCI_TO_MEM_LE (dev, packet);
- entry->status = le16_to_cpu (status);
+ entry->base = PCI_TO_MEM_LE(dev, packet);
+ entry->status = cpu_to_le16(status);
+ flush_dcache_range((unsigned long)entry,
+ (unsigned long)entry + sizeof(*entry));
/* Trigger an immediate send poll. */
- pcnet_write_csr (dev, 0, 0x0008);
+ pcnet_write_csr(dev, 0, 0x0008);
failure:
if (++lp->cur_tx >= TX_RING_SIZE)
lp->cur_tx = 0;
- PCNET_DEBUG2 ("done\n");
+ PCNET_DEBUG2("done\n");
return pkt_len;
}
@@ -450,43 +464,49 @@
while (1) {
entry = &lp->rx_ring[lp->cur_rx];
+ invalidate_dcache_range((unsigned long)entry,
+ (unsigned long)entry + sizeof(*entry));
/*
* If we own the next entry, it's a new packet. Send it up.
*/
- if (((status = le16_to_cpu (entry->status)) & 0x8000) != 0) {
+ status = le16_to_cpu(entry->status);
+ if ((status & 0x8000) != 0)
break;
- }
status >>= 8;
if (status != 0x03) { /* There was an error. */
-
- printf ("%s: Rx%d", dev->name, lp->cur_rx);
- PCNET_DEBUG1 (" (status=0x%x)", status);
+ printf("%s: Rx%d", dev->name, lp->cur_rx);
+ PCNET_DEBUG1(" (status=0x%x)", status);
if (status & 0x20)
- printf (" Frame");
+ printf(" Frame");
if (status & 0x10)
- printf (" Overflow");
+ printf(" Overflow");
if (status & 0x08)
- printf (" CRC");
+ printf(" CRC");
if (status & 0x04)
- printf (" Fifo");
- printf (" Error\n");
- entry->status &= le16_to_cpu (0x03ff);
+ printf(" Fifo");
+ printf(" Error\n");
+ entry->status &= le16_to_cpu(0x03ff);
} else {
-
- pkt_len =
- (le32_to_cpu (entry->msg_length) & 0xfff) - 4;
+ pkt_len = (le32_to_cpu(entry->msg_length) & 0xfff) - 4;
if (pkt_len < 60) {
- printf ("%s: Rx%d: invalid packet length %d\n", dev->name, lp->cur_rx, pkt_len);
+ printf("%s: Rx%d: invalid packet length %d\n",
+ dev->name, lp->cur_rx, pkt_len);
} else {
- NetReceive (lp->rx_buf[lp->cur_rx], pkt_len);
- PCNET_DEBUG2 ("Rx%d: %d bytes from 0x%p\n",
- lp->cur_rx, pkt_len,
- lp->rx_buf[lp->cur_rx]);
+ invalidate_dcache_range(
+ (unsigned long)lp->rx_buf[lp->cur_rx],
+ (unsigned long)lp->rx_buf[lp->cur_rx] +
+ pkt_len);
+ NetReceive(lp->rx_buf[lp->cur_rx], pkt_len);
+ PCNET_DEBUG2("Rx%d: %d bytes from 0x%p\n",
+ lp->cur_rx, pkt_len,
+ lp->rx_buf[lp->cur_rx]);
}
}
- entry->status |= cpu_to_le16 (0x8000);
+ entry->status |= cpu_to_le16(0x8000);
+ flush_dcache_range((unsigned long)entry,
+ (unsigned long)entry + sizeof(*entry));
if (++lp->cur_rx >= RX_RING_SIZE)
lp->cur_rx = 0;
@@ -494,22 +514,21 @@
return pkt_len;
}
-static void pcnet_halt (struct eth_device *dev)
+static void pcnet_halt(struct eth_device *dev)
{
int i;
- PCNET_DEBUG1 ("%s: pcnet_halt...\n", dev->name);
+ PCNET_DEBUG1("%s: pcnet_halt...\n", dev->name);
/* Reset the PCnet controller */
- pcnet_reset (dev);
+ pcnet_reset(dev);
/* Wait for Stop bit */
for (i = 1000; i > 0; i--) {
- if (pcnet_read_csr (dev, 0) & 0x4)
+ if (pcnet_read_csr(dev, 0) & 0x4)
break;
- udelay (10);
+ udelay(10);
}
- if (i <= 0) {
- printf ("%s: TIMEOUT: controller reset failed\n", dev->name);
- }
+ if (i <= 0)
+ printf("%s: TIMEOUT: controller reset failed\n", dev->name);
}
diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c
index 0f2dfd6..b20b4df 100644
--- a/drivers/net/phy/atheros.c
+++ b/drivers/net/phy/atheros.c
@@ -40,7 +40,7 @@
static struct phy_driver AR8021_driver = {
.name = "AR8021",
.uid = 0x4dd040,
- .mask = 0xfffff0,
+ .mask = 0x4fffff,
.features = PHY_GBIT_FEATURES,
.config = ar8021_config,
.startup = genphy_startup,
@@ -48,11 +48,11 @@
};
static struct phy_driver AR8031_driver = {
- .name = "AR8031",
+ .name = "AR8031/AR8033",
.uid = 0x4dd074,
- .mask = 0xfffff0,
+ .mask = 0x4fffff,
.features = PHY_GBIT_FEATURES,
- .config = genphy_config,
+ .config = ar8021_config,
.startup = genphy_startup,
.shutdown = genphy_shutdown,
};
diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
index a7450f8..5d7e3be 100644
--- a/drivers/net/phy/micrel.c
+++ b/drivers/net/phy/micrel.c
@@ -100,6 +100,19 @@
return phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_DATAR);
}
+
+static int ksz9021_phy_extread(struct phy_device *phydev, int addr, int devaddr,
+ int regnum)
+{
+ return ksz9021_phy_extended_read(phydev, regnum);
+}
+
+static int ksz9021_phy_extwrite(struct phy_device *phydev, int addr,
+ int devaddr, int regnum, u16 val)
+{
+ return ksz9021_phy_extended_write(phydev, regnum, val);
+}
+
/* Micrel ksz9021 */
static int ksz9021_config(struct phy_device *phydev)
{
@@ -131,6 +144,8 @@
.config = &ksz9021_config,
.startup = &ksz90xx_startup,
.shutdown = &genphy_shutdown,
+ .writeext = &ksz9021_phy_extwrite,
+ .readext = &ksz9021_phy_extread,
};
#endif
@@ -171,14 +186,31 @@
return phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ9031_MMD_REG_DATA);
}
+static int ksz9031_phy_extread(struct phy_device *phydev, int addr, int devaddr,
+ int regnum)
+{
+ return ksz9031_phy_extended_read(phydev, devaddr, regnum,
+ MII_KSZ9031_MOD_DATA_NO_POST_INC);
+};
+
+static int ksz9031_phy_extwrite(struct phy_device *phydev, int addr,
+ int devaddr, int regnum, u16 val)
+{
+ return ksz9031_phy_extended_write(phydev, devaddr, regnum,
+ MII_KSZ9031_MOD_DATA_POST_INC_RW, val);
+};
+
+
static struct phy_driver ksz9031_driver = {
.name = "Micrel ksz9031",
.uid = 0x221620,
- .mask = 0xfffffe,
+ .mask = 0xfffff0,
.features = PHY_GBIT_FEATURES,
.config = &genphy_config,
.startup = &ksz90xx_startup,
.shutdown = &genphy_shutdown,
+ .writeext = &ksz9031_phy_extwrite,
+ .readext = &ksz9031_phy_extread,
};
int phy_micrel_init(void)
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index 62925bb..c691fbb 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -275,13 +275,14 @@
int mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR);
/* We're using autonegotiation */
- if (mii_reg & BMSR_ANEGCAPABLE) {
+ if (phydev->supported & SUPPORTED_Autoneg) {
u32 lpa = 0;
int gblpa = 0;
u32 estatus = 0;
/* Check for gigabit capability */
- if (mii_reg & BMSR_ERCAP) {
+ if (phydev->supported & (SUPPORTED_1000baseT_Full |
+ SUPPORTED_1000baseT_Half)) {
/* We want a list of states supported by
* both PHYs in the link
*/
diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c
index ddbbc35..a3ace68 100644
--- a/drivers/net/phy/realtek.c
+++ b/drivers/net/phy/realtek.c
@@ -102,7 +102,7 @@
static struct phy_driver RTL8211B_driver = {
.name = "RealTek RTL8211B",
.uid = 0x1cc910,
- .mask = 0xfffff0,
+ .mask = 0xffffff,
.features = PHY_GBIT_FEATURES,
.config = &rtl8211x_config,
.startup = &rtl8211x_startup,
@@ -113,7 +113,7 @@
static struct phy_driver RTL8211E_driver = {
.name = "RealTek RTL8211E",
.uid = 0x1cc915,
- .mask = 0xfffff0,
+ .mask = 0xffffff,
.features = PHY_GBIT_FEATURES,
.config = &rtl8211x_config,
.startup = &rtl8211x_startup,
@@ -124,7 +124,7 @@
static struct phy_driver RTL8211DN_driver = {
.name = "RealTek RTL8211DN",
.uid = 0x1cc914,
- .mask = 0xfffff0,
+ .mask = 0xffffff,
.features = PHY_GBIT_FEATURES,
.config = &rtl8211x_config,
.startup = &rtl8211x_startup,
diff --git a/drivers/net/phy/smsc.c b/drivers/net/phy/smsc.c
index 60ed92d..bfd9815 100644
--- a/drivers/net/phy/smsc.c
+++ b/drivers/net/phy/smsc.c
@@ -12,6 +12,7 @@
*/
#include <miiphy.h>
+/* This code does not check the partner abilities. */
static int smsc_parse_status(struct phy_device *phydev)
{
int mii_reg;
@@ -64,7 +65,7 @@
.mask = 0xffff0,
.features = PHY_BASIC_FEATURES,
.config = &genphy_config_aneg,
- .startup = &smsc_startup,
+ .startup = &genphy_startup,
.shutdown = &genphy_shutdown,
};
diff --git a/drivers/net/phy/vitesse.c b/drivers/net/phy/vitesse.c
index 5cf103e..c555979 100644
--- a/drivers/net/phy/vitesse.c
+++ b/drivers/net/phy/vitesse.c
@@ -49,6 +49,15 @@
#define MIIM_VSC8574_18G_QSGMII 0x80e0
#define MIIM_VSC8574_18G_CMDSTAT 0x8000
+/* Vitesse VSC8514 control register */
+#define MIIM_VSC8514_GENERAL18 0x12
+#define MIIM_VSC8514_GENERAL19 0x13
+#define MIIM_VSC8514_GENERAL23 0x17
+
+/* Vitesse VSC8514 gerenal purpose register 18 */
+#define MIIM_VSC8514_18G_QSGMII 0x80e0
+#define MIIM_VSC8514_18G_CMDSTAT 0x8000
+
/* CIS8201 */
static int vitesse_config(struct phy_device *phydev)
{
@@ -148,7 +157,7 @@
static int vsc8574_config(struct phy_device *phydev)
{
u32 val;
- /* configure regiser 19G for MAC */
+ /* configure register 19G for MAC */
phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS,
PHY_EXT_PAGE_ACCESS_GENERAL);
@@ -188,6 +197,53 @@
return 0;
}
+static int vsc8514_config(struct phy_device *phydev)
+{
+ u32 val;
+ int timeout = 1000000;
+
+ /* configure register to access 19G */
+ phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS,
+ PHY_EXT_PAGE_ACCESS_GENERAL);
+
+ val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL19);
+ if (phydev->interface == PHY_INTERFACE_MODE_QSGMII) {
+ /* set bit 15:14 to '01' for QSGMII mode */
+ val = (val & 0x3fff) | (1 << 14);
+ phy_write(phydev, MDIO_DEVAD_NONE,
+ MIIM_VSC8514_GENERAL19, val);
+ /* Enable 4 ports MAC QSGMII */
+ phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL18,
+ MIIM_VSC8514_18G_QSGMII);
+ } else {
+ /*TODO Add SGMII functionality once spec sheet
+ * for VSC8514 defines complete functionality
+ */
+ }
+
+ val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL18);
+ /* When bit 15 is cleared the command has completed */
+ while ((val & MIIM_VSC8514_18G_CMDSTAT) && timeout--)
+ val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL18);
+
+ if (0 == timeout) {
+ printf("PHY 8514 config failed\n");
+ return -1;
+ }
+
+ phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, 0);
+
+ /* configure register to access 23 */
+ val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL23);
+ /* set bits 10:8 to '000' */
+ val = (val & 0xf8ff);
+ phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL23, val);
+
+ genphy_config_aneg(phydev);
+
+ return 0;
+}
+
static struct phy_driver VSC8211_driver = {
.name = "Vitesse VSC8211",
.uid = 0xfc4b0,
@@ -238,6 +294,16 @@
.shutdown = &genphy_shutdown,
};
+static struct phy_driver VSC8514_driver = {
+ .name = "Vitesse VSC8514",
+ .uid = 0x70570,
+ .mask = 0xffff0,
+ .features = PHY_GBIT_FEATURES,
+ .config = &vsc8514_config,
+ .startup = &vitesse_startup,
+ .shutdown = &genphy_shutdown,
+};
+
static struct phy_driver VSC8601_driver = {
.name = "Vitesse VSC8601",
.uid = 0x70420,
@@ -298,6 +364,7 @@
phy_register(&VSC8211_driver);
phy_register(&VSC8221_driver);
phy_register(&VSC8574_driver);
+ phy_register(&VSC8514_driver);
phy_register(&VSC8662_driver);
phy_register(&cis8201_driver);
phy_register(&cis8204_driver);
diff --git a/drivers/net/rtl8139.c b/drivers/net/rtl8139.c
index 4186699..208ce5c 100644
--- a/drivers/net/rtl8139.c
+++ b/drivers/net/rtl8139.c
@@ -188,7 +188,7 @@
static int rtl_poll(struct eth_device *dev);
static void rtl_disable(struct eth_device *dev);
#ifdef CONFIG_MCAST_TFTP/* This driver already accepts all b/mcast */
-static int rtl_bcast_addr (struct eth_device *dev, u8 bcast_mac, u8 set)
+static int rtl_bcast_addr(struct eth_device *dev, const u8 *bcast_mac, u8 set)
{
return (0);
}
diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c
index 13fa9c0..d040ab1 100644
--- a/drivers/net/rtl8169.c
+++ b/drivers/net/rtl8169.c
@@ -246,6 +246,8 @@
{"RTL-8169sc/8110sc", 0x18, 0xff7e1880,},
{"RTL-8168b/8111sb", 0x30, 0xff7e1880,},
{"RTL-8168b/8111sb", 0x38, 0xff7e1880,},
+ {"RTL-8168d/8111d", 0x28, 0xff7e1880,},
+ {"RTL-8168evl/8111evl", 0x2e, 0xff7e1880,},
{"RTL-8101e", 0x34, 0xff7e1880,},
{"RTL-8100e", 0x32, 0xff7e1880,},
};
@@ -314,6 +316,7 @@
static struct pci_device_id supported[] = {
{PCI_VENDOR_ID_REALTEK, 0x8167},
+ {PCI_VENDOR_ID_REALTEK, 0x8168},
{PCI_VENDOR_ID_REALTEK, 0x8169},
{}
};
@@ -394,6 +397,50 @@
return 0;
}
+/*
+ * Cache maintenance functions. These are simple wrappers around the more
+ * general purpose flush_cache() and invalidate_dcache_range() functions.
+ */
+
+static void rtl_inval_rx_desc(struct RxDesc *desc)
+{
+ unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1);
+ unsigned long end = ALIGN(start + sizeof(*desc), ARCH_DMA_MINALIGN);
+
+ invalidate_dcache_range(start, end);
+}
+
+static void rtl_flush_rx_desc(struct RxDesc *desc)
+{
+ flush_cache((unsigned long)desc, sizeof(*desc));
+}
+
+static void rtl_inval_tx_desc(struct TxDesc *desc)
+{
+ unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1);
+ unsigned long end = ALIGN(start + sizeof(*desc), ARCH_DMA_MINALIGN);
+
+ invalidate_dcache_range(start, end);
+}
+
+static void rtl_flush_tx_desc(struct TxDesc *desc)
+{
+ flush_cache((unsigned long)desc, sizeof(*desc));
+}
+
+static void rtl_inval_buffer(void *buf, size_t size)
+{
+ unsigned long start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1);
+ unsigned long end = ALIGN(start + size, ARCH_DMA_MINALIGN);
+
+ invalidate_dcache_range(start, end);
+}
+
+static void rtl_flush_buffer(void *buf, size_t size)
+{
+ flush_cache((unsigned long)buf, size);
+}
+
/**************************************************************************
RECV - Receive a frame
***************************************************************************/
@@ -411,14 +458,16 @@
ioaddr = dev->iobase;
cur_rx = tpc->cur_rx;
- flush_cache((unsigned long)&tpc->RxDescArray[cur_rx],
- sizeof(struct RxDesc));
+
+ rtl_inval_rx_desc(&tpc->RxDescArray[cur_rx]);
+
if ((le32_to_cpu(tpc->RxDescArray[cur_rx].status) & OWNbit) == 0) {
if (!(le32_to_cpu(tpc->RxDescArray[cur_rx].status) & RxRES)) {
unsigned char rxdata[RX_BUF_LEN];
length = (int) (le32_to_cpu(tpc->RxDescArray[cur_rx].
status) & 0x00001FFF) - 4;
+ rtl_inval_buffer(tpc->RxBufferRing[cur_rx], length);
memcpy(rxdata, tpc->RxBufferRing[cur_rx], length);
NetReceive(rxdata, length);
@@ -430,8 +479,7 @@
cpu_to_le32(OWNbit + RX_BUF_SIZE);
tpc->RxDescArray[cur_rx].buf_addr =
cpu_to_le32(bus_to_phys(tpc->RxBufferRing[cur_rx]));
- flush_cache((unsigned long)tpc->RxBufferRing[cur_rx],
- RX_BUF_SIZE);
+ rtl_flush_rx_desc(&tpc->RxDescArray[cur_rx]);
} else {
puts("Error Rx");
}
@@ -473,7 +521,7 @@
/* point to the current txb incase multiple tx_rings are used */
ptxb = tpc->Tx_skbuff[entry * MAX_ETH_FRAME_SIZE];
memcpy(ptxb, (char *)packet, (int)length);
- flush_cache((unsigned long)ptxb, length);
+ rtl_flush_buffer(ptxb, length);
while (len < ETH_ZLEN)
ptxb[len++] = '\0';
@@ -489,20 +537,20 @@
cpu_to_le32((OWNbit | EORbit | FSbit | LSbit) |
((len > ETH_ZLEN) ? len : ETH_ZLEN));
}
+ rtl_flush_tx_desc(&tpc->TxDescArray[entry]);
RTL_W8(TxPoll, 0x40); /* set polling bit */
tpc->cur_tx++;
to = currticks() + TX_TIMEOUT;
do {
- flush_cache((unsigned long)&tpc->TxDescArray[entry],
- sizeof(struct TxDesc));
+ rtl_inval_tx_desc(&tpc->TxDescArray[entry]);
} while ((le32_to_cpu(tpc->TxDescArray[entry].status) & OWNbit)
&& (currticks() < to)); /* wait */
if (currticks() >= to) {
#ifdef DEBUG_RTL8169_TX
- puts ("tx timeout/error\n");
- printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime);
+ puts("tx timeout/error\n");
+ printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
#endif
ret = 0;
} else {
@@ -604,7 +652,7 @@
RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
#ifdef DEBUG_RTL8169
- printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime);
+ printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
#endif
}
@@ -638,11 +686,11 @@
tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE];
tpc->RxDescArray[i].buf_addr =
cpu_to_le32(bus_to_phys(tpc->RxBufferRing[i]));
- flush_cache((unsigned long)tpc->RxBufferRing[i], RX_BUF_SIZE);
+ rtl_flush_rx_desc(&tpc->RxDescArray[i]);
}
#ifdef DEBUG_RTL8169
- printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime);
+ printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
#endif
}
@@ -683,7 +731,7 @@
txb[5] = dev->enetaddr[5];
#ifdef DEBUG_RTL8169
- printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime);
+ printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
#endif
return 0;
}
@@ -869,11 +917,25 @@
int idx=0;
while(1){
+ unsigned int region;
+ u16 device;
+
/* Find RTL8169 */
if ((devno = pci_find_devices(supported, idx++)) < 0)
break;
- pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase);
+ pci_read_config_word(devno, PCI_DEVICE_ID, &device);
+ switch (device) {
+ case 0x8168:
+ region = 2;
+ break;
+
+ default:
+ region = 1;
+ break;
+ }
+
+ pci_read_config_dword(devno, PCI_BASE_ADDRESS_0 + (region * 4), &iobase);
iobase &= ~0xf;
debug ("rtl8169: REALTEK RTL8169 @0x%x\n", iobase);
diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c
index d5a83e0..5e132f2 100644
--- a/drivers/net/sh_eth.c
+++ b/drivers/net/sh_eth.c
@@ -4,6 +4,7 @@
* Copyright (C) 2008, 2011 Renesas Solutions Corp.
* Copyright (c) 2008, 2011 Nobuhiro Iwamatsu
* Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
+ * Copyright (C) 2013 Renesas Electronics Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -25,13 +26,31 @@
#ifndef CONFIG_SH_ETHER_PHY_ADDR
# error "Please define CONFIG_SH_ETHER_PHY_ADDR"
#endif
-#ifdef CONFIG_SH_ETHER_CACHE_WRITEBACK
-#define flush_cache_wback(addr, len) \
- dcache_wback_range((u32)addr, (u32)(addr + len - 1))
+
+#if defined(CONFIG_SH_ETHER_CACHE_WRITEBACK) && !defined(CONFIG_SYS_DCACHE_OFF)
+#define flush_cache_wback(addr, len) \
+ flush_dcache_range((u32)addr, (u32)(addr + len - 1))
#else
#define flush_cache_wback(...)
#endif
+#if defined(CONFIG_SH_ETHER_CACHE_INVALIDATE) && defined(CONFIG_ARM)
+#define invalidate_cache(addr, len) \
+ { \
+ u32 line_size = CONFIG_SH_ETHER_ALIGNE_SIZE; \
+ u32 start, end; \
+ \
+ start = (u32)addr; \
+ end = start + len; \
+ start &= ~(line_size - 1); \
+ end = ((end + line_size - 1) & ~(line_size - 1)); \
+ \
+ invalidate_dcache_range(start, end); \
+ }
+#else
+#define invalidate_cache(...)
+#endif
+
#define TIMEOUT_CNT 1000
int sh_eth_send(struct eth_device *dev, void *packet, int len)
@@ -69,8 +88,11 @@
/* Wait until packet is transmitted */
timeout = TIMEOUT_CNT;
- while (port_info->tx_desc_cur->td0 & TD_TACT && timeout--)
+ do {
+ invalidate_cache(port_info->tx_desc_cur,
+ sizeof(struct tx_desc_s));
udelay(100);
+ } while (port_info->tx_desc_cur->td0 & TD_TACT && timeout--);
if (timeout < 0) {
printf(SHETHER_NAME ": transmit timeout\n");
@@ -94,12 +116,14 @@
uchar *packet;
/* Check if the rx descriptor is ready */
+ invalidate_cache(port_info->rx_desc_cur, sizeof(struct rx_desc_s));
if (!(port_info->rx_desc_cur->rd0 & RD_RACT)) {
/* Check for errors */
if (!(port_info->rx_desc_cur->rd0 & RD_RFE)) {
len = port_info->rx_desc_cur->rd1 & 0xffff;
packet = (uchar *)
ADDR_TO_P2(port_info->rx_desc_cur->rd2);
+ invalidate_cache(packet, len);
NetReceive(packet, len);
}
@@ -108,7 +132,6 @@
port_info->rx_desc_cur->rd0 = RD_RACT | RD_RDLE;
else
port_info->rx_desc_cur->rd0 = RD_RACT;
-
/* Point to the next descriptor */
port_info->rx_desc_cur++;
if (port_info->rx_desc_cur >=
@@ -237,15 +260,17 @@
* Allocate rx data buffers. They must be 32 bytes aligned and in
* P2 area
*/
- port_info->rx_buf_malloc = malloc(NUM_RX_DESC * MAX_BUF_SIZE + 31);
+ port_info->rx_buf_malloc = malloc(
+ NUM_RX_DESC * MAX_BUF_SIZE + RX_BUF_ALIGNE_SIZE - 1);
if (!port_info->rx_buf_malloc) {
printf(SHETHER_NAME ": malloc failed\n");
ret = -ENOMEM;
goto err_buf_malloc;
}
- tmp_addr = (u32)(((int)port_info->rx_buf_malloc + (32 - 1)) &
- ~(32 - 1));
+ tmp_addr = (u32)(((int)port_info->rx_buf_malloc
+ + (RX_BUF_ALIGNE_SIZE - 1)) &
+ ~(RX_BUF_ALIGNE_SIZE - 1));
port_info->rx_buf_base = (u8 *)ADDR_TO_P2(tmp_addr);
/* Initialize all descriptors */
@@ -351,8 +376,9 @@
struct phy_device *phy;
/* Configure e-dmac registers */
- sh_eth_write(eth, (sh_eth_read(eth, EDMR) & ~EMDR_DESC_R) | EDMR_EL,
- EDMR);
+ sh_eth_write(eth, (sh_eth_read(eth, EDMR) & ~EMDR_DESC_R) |
+ (EMDR_DESC | EDMR_EL), EDMR);
+
sh_eth_write(eth, 0, EESIPR);
sh_eth_write(eth, 0, TRSCER);
sh_eth_write(eth, 0, TFTR);
@@ -384,6 +410,8 @@
#if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740)
sh_eth_write(eth, CONFIG_SH_ETHER_SH7734_MII, RMII_MII);
+#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791)
+ sh_eth_write(eth, sh_eth_read(eth, RMIIMR) | 0x1, RMIIMR);
#endif
/* Configure phy */
ret = sh_eth_phy_config(eth);
@@ -407,7 +435,8 @@
sh_eth_write(eth, GECMR_100B, GECMR);
#elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
sh_eth_write(eth, 1, RTRATE);
-#elif defined(CONFIG_CPU_SH7724)
+#elif defined(CONFIG_CPU_SH7724) || defined(CONFIG_R8A7790) || \
+ defined(CONFIG_R8A7791)
val = ECMR_RTM;
#endif
} else if (phy->speed == 10) {
diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h
index 9ad800e..8aa7109 100644
--- a/drivers/net/sh_eth.h
+++ b/drivers/net/sh_eth.h
@@ -31,6 +31,11 @@
#define ADDR_TO_P2(addr) (addr)
#endif /* defined(CONFIG_SH) */
+/* base padding size is 16 */
+#ifndef CONFIG_SH_ETHER_ALIGNE_SIZE
+#define CONFIG_SH_ETHER_ALIGNE_SIZE 16
+#endif
+
/* Number of supported ports */
#define MAX_PORT_NUM 2
@@ -45,15 +50,16 @@
/* The size of the tx descriptor is determined by how much padding is used.
4, 20, or 52 bytes of padding can be used */
-#define TX_DESC_PADDING 4
-#define TX_DESC_SIZE (12 + TX_DESC_PADDING)
+#define TX_DESC_PADDING (CONFIG_SH_ETHER_ALIGNE_SIZE - 12)
+/* same as CONFIG_SH_ETHER_ALIGNE_SIZE */
+#define TX_DESC_SIZE (12 + TX_DESC_PADDING)
/* Tx descriptor. We always use 3 bytes of padding */
struct tx_desc_s {
volatile u32 td0;
u32 td1;
u32 td2; /* Buffer start */
- u32 padding;
+ u8 padding[TX_DESC_PADDING]; /* aligned cache line size */
};
/* There is no limitation in the number of rx descriptors */
@@ -61,15 +67,18 @@
/* The size of the rx descriptor is determined by how much padding is used.
4, 20, or 52 bytes of padding can be used */
-#define RX_DESC_PADDING 4
+#define RX_DESC_PADDING (CONFIG_SH_ETHER_ALIGNE_SIZE - 12)
+/* same as CONFIG_SH_ETHER_ALIGNE_SIZE */
#define RX_DESC_SIZE (12 + RX_DESC_PADDING)
+/* aligned cache line size */
+#define RX_BUF_ALIGNE_SIZE (CONFIG_SH_ETHER_ALIGNE_SIZE > 32 ? 64 : 32)
/* Rx descriptor. We always use 4 bytes of padding */
struct rx_desc_s {
volatile u32 rd0;
volatile u32 rd1;
u32 rd2; /* Buffer start */
- u32 padding;
+ u8 padding[TX_DESC_PADDING]; /* aligned cache line size */
};
struct sh_eth_info {
@@ -157,6 +166,7 @@
TLFRCR,
CERCR,
CEECR,
+ RMIIMR, /* R8A7790 */
MAFCR,
RTRATE,
CSMR,
@@ -263,6 +273,7 @@
[RMCR] = 0x0058,
[TFUCR] = 0x0064,
[RFOCR] = 0x0068,
+ [RMIIMR] = 0x006C,
[FCFTR] = 0x0070,
[RPADIR] = 0x0078,
[TRIMD] = 0x007c,
@@ -290,6 +301,9 @@
#elif defined(CONFIG_R8A7740)
#define SH_ETH_TYPE_GETHER
#define BASE_IO_ADDR 0xE9A00000
+#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791)
+#define SH_ETH_TYPE_ETHER
+#define BASE_IO_ADDR 0xEE700200
#endif
/*
@@ -320,6 +334,14 @@
#endif
};
+#if CONFIG_SH_ETHER_ALIGNE_SIZE == 64
+# define EMDR_DESC EDMR_DL1
+#elif CONFIG_SH_ETHER_ALIGNE_SIZE == 32
+# define EMDR_DESC EDMR_DL0
+#elif CONFIG_SH_ETHER_ALIGNE_SIZE == 16 /* Default */
+# define EMDR_DESC 0
+#endif
+
/* RFLR */
#define RFLR_RFL_MIN 0x05EE /* Recv Frame length 1518 byte */
@@ -485,6 +507,8 @@
ECMR_PRM = 0x00000001,
#ifdef CONFIG_CPU_SH7724
ECMR_RTM = 0x00000010,
+#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791)
+ ECMR_RTM = 0x00000004,
#endif
};
diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index f5e314b..e9138f0 100644
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c
@@ -5,7 +5,7 @@
* terms of the GNU Public License, Version 2, incorporated
* herein by reference.
*
- * Copyright 2004-2011 Freescale Semiconductor, Inc.
+ * Copyright 2004-2011, 2013 Freescale Semiconductor, Inc.
* (C) Copyright 2003, Motorola, Inc.
* author Andy Fleming
*
@@ -25,21 +25,13 @@
#define TX_BUF_CNT 2
-static uint rxIdx; /* index of the current RX buffer */
-static uint txIdx; /* index of the current TX buffer */
-
-typedef volatile struct rtxbd {
- txbd8_t txbd[TX_BUF_CNT];
- rxbd8_t rxbd[PKTBUFSRX];
-} RTXBD;
-
-#define MAXCONTROLLERS (8)
-
-static struct tsec_private *privlist[MAXCONTROLLERS];
-static int num_tsecs = 0;
+static uint rx_idx; /* index of the current RX buffer */
+static uint tx_idx; /* index of the current TX buffer */
#ifdef __GNUC__
-static RTXBD rtx __attribute__ ((aligned(8)));
+static struct txbd8 __iomem txbd[TX_BUF_CNT] __aligned(8);
+static struct rxbd8 __iomem rxbd[PKTBUFSRX] __aligned(8);
+
#else
#error "rtx must be 64-bit aligned"
#endif
@@ -57,7 +49,7 @@
#endif
#ifdef CONFIG_MPC85XX_FEC
{
- .regs = (tsec_t *)(TSEC_BASE_ADDR + 0x2000),
+ .regs = TSEC_GET_REGS(2, 0x2000),
.devname = CONFIG_MPC85XX_FEC_NAME,
.phyaddr = FEC_PHY_ADDR,
.flags = FEC_FLAGS,
@@ -113,32 +105,31 @@
* result.
* 2) Use the 8 most significant bits as a hash into a 256-entry
* table. The table is controlled through 8 32-bit registers:
- * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
- * gaddr7. This means that the 3 most significant bits in the
+ * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is entry
+ * 255. This means that the 3 most significant bits in the
* hash index which gaddr register to use, and the 5 other bits
* indicate which bit (assuming an IBM numbering scheme, which
- * for PowerPC (tm) is usually the case) in the tregister holds
+ * for PowerPC (tm) is usually the case) in the register holds
* the entry. */
static int
-tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set)
+tsec_mcast_addr(struct eth_device *dev, const u8 *mcast_mac, u8 set)
{
- struct tsec_private *priv = privlist[1];
- volatile tsec_t *regs = priv->regs;
- volatile u32 *reg_array, value;
- u8 result, whichbit, whichreg;
+ struct tsec_private *priv = (struct tsec_private *)dev->priv;
+ struct tsec __iomem *regs = priv->regs;
+ u32 result, value;
+ u8 whichbit, whichreg;
- result = (u8)((ether_crc(MAC_ADDR_LEN,mcast_mac) >> 24) & 0xff);
- whichbit = result & 0x1f; /* the 5 LSB = which bit to set */
- whichreg = result >> 5; /* the 3 MSB = which reg to set it in */
- value = (1 << (31-whichbit));
+ result = ether_crc(MAC_ADDR_LEN, mcast_mac);
+ whichbit = (result >> 24) & 0x1f; /* the 5 LSB = which bit to set */
+ whichreg = result >> 29; /* the 3 MSB = which reg to set it in */
- reg_array = &(regs->hash.gaddr0);
+ value = 1 << (31-whichbit);
- if (set) {
- reg_array[whichreg] |= value;
- } else {
- reg_array[whichreg] &= ~value;
- }
+ if (set)
+ setbits_be32(®s->hash.gaddr0 + whichreg, value);
+ else
+ clrbits_be32(®s->hash.gaddr0 + whichreg, value);
+
return 0;
}
#endif /* Multicast TFTP ? */
@@ -147,7 +138,7 @@
* those we don't care about (unless zero is bad, in which case,
* choose a more appropriate value)
*/
-static void init_registers(tsec_t *regs)
+static void init_registers(struct tsec __iomem *regs)
{
/* Clear IEVENT */
out_be32(®s->ievent, IEVENT_INIT_CLEAR);
@@ -175,7 +166,7 @@
out_be32(®s->rctrl, 0x00000000);
/* Init RMON mib registers */
- memset((void *)&(regs->rmon), 0, sizeof(rmon_mib_t));
+ memset((void *)®s->rmon, 0, sizeof(regs->rmon));
out_be32(®s->rmon.cam1, 0xffffffff);
out_be32(®s->rmon.cam2, 0xffffffff);
@@ -194,7 +185,7 @@
*/
static void adjust_link(struct tsec_private *priv, struct phy_device *phydev)
{
- tsec_t *regs = priv->regs;
+ struct tsec __iomem *regs = priv->regs;
u32 ecntrl, maccfg2;
if (!phydev->link) {
@@ -248,7 +239,7 @@
void redundant_init(struct eth_device *dev)
{
struct tsec_private *priv = dev->priv;
- tsec_t *regs = priv->regs;
+ struct tsec __iomem *regs = priv->regs;
uint t, count = 0;
int fail = 1;
static const u8 pkt[] = {
@@ -281,23 +272,26 @@
clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
do {
+ uint16_t status;
tsec_send(dev, (void *)pkt, sizeof(pkt));
/* Wait for buffer to be received */
- for (t = 0; rtx.rxbd[rxIdx].status & RXBD_EMPTY; t++) {
+ for (t = 0; in_be16(&rxbd[rx_idx].status) & RXBD_EMPTY; t++) {
if (t >= 10 * TOUT_LOOP) {
printf("%s: tsec: rx error\n", dev->name);
break;
}
}
- if (!memcmp(pkt, (void *)NetRxPackets[rxIdx], sizeof(pkt)))
+ if (!memcmp(pkt, (void *)NetRxPackets[rx_idx], sizeof(pkt)))
fail = 0;
- rtx.rxbd[rxIdx].length = 0;
- rtx.rxbd[rxIdx].status =
- RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0);
- rxIdx = (rxIdx + 1) % PKTBUFSRX;
+ out_be16(&rxbd[rx_idx].length, 0);
+ status = RXBD_EMPTY;
+ if ((rx_idx + 1) == PKTBUFSRX)
+ status |= RXBD_WRAP;
+ out_be16(&rxbd[rx_idx].status, status);
+ rx_idx = (rx_idx + 1) % PKTBUFSRX;
if (in_be32(®s->ievent) & IEVENT_BSY) {
out_be32(®s->ievent, IEVENT_BSY);
@@ -325,36 +319,39 @@
*/
static void startup_tsec(struct eth_device *dev)
{
- int i;
struct tsec_private *priv = (struct tsec_private *)dev->priv;
- tsec_t *regs = priv->regs;
+ struct tsec __iomem *regs = priv->regs;
+ uint16_t status;
+ int i;
/* reset the indices to zero */
- rxIdx = 0;
- txIdx = 0;
+ rx_idx = 0;
+ tx_idx = 0;
#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
uint svr;
#endif
/* Point to the buffer descriptors */
- out_be32(®s->tbase, (unsigned int)(&rtx.txbd[txIdx]));
- out_be32(®s->rbase, (unsigned int)(&rtx.rxbd[rxIdx]));
+ out_be32(®s->tbase, (u32)&txbd[0]);
+ out_be32(®s->rbase, (u32)&rxbd[0]);
/* Initialize the Rx Buffer descriptors */
for (i = 0; i < PKTBUFSRX; i++) {
- rtx.rxbd[i].status = RXBD_EMPTY;
- rtx.rxbd[i].length = 0;
- rtx.rxbd[i].bufPtr = (uint) NetRxPackets[i];
+ out_be16(&rxbd[i].status, RXBD_EMPTY);
+ out_be16(&rxbd[i].length, 0);
+ out_be32(&rxbd[i].bufptr, (u32)NetRxPackets[i]);
}
- rtx.rxbd[PKTBUFSRX - 1].status |= RXBD_WRAP;
+ status = in_be16(&rxbd[PKTBUFSRX - 1].status);
+ out_be16(&rxbd[PKTBUFSRX - 1].status, status | RXBD_WRAP);
/* Initialize the TX Buffer Descriptors */
for (i = 0; i < TX_BUF_CNT; i++) {
- rtx.txbd[i].status = 0;
- rtx.txbd[i].length = 0;
- rtx.txbd[i].bufPtr = 0;
+ out_be16(&txbd[i].status, 0);
+ out_be16(&txbd[i].length, 0);
+ out_be32(&txbd[i].bufptr, 0);
}
- rtx.txbd[TX_BUF_CNT - 1].status |= TXBD_WRAP;
+ status = in_be16(&txbd[TX_BUF_CNT - 1].status);
+ out_be16(&txbd[TX_BUF_CNT - 1].status, status | TXBD_WRAP);
#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
svr = get_svr();
@@ -378,66 +375,67 @@
*/
static int tsec_send(struct eth_device *dev, void *packet, int length)
{
- int i;
- int result = 0;
struct tsec_private *priv = (struct tsec_private *)dev->priv;
- tsec_t *regs = priv->regs;
+ struct tsec __iomem *regs = priv->regs;
+ uint16_t status;
+ int result = 0;
+ int i;
/* Find an empty buffer descriptor */
- for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
+ for (i = 0; in_be16(&txbd[tx_idx].status) & TXBD_READY; i++) {
if (i >= TOUT_LOOP) {
debug("%s: tsec: tx buffers full\n", dev->name);
return result;
}
}
- rtx.txbd[txIdx].bufPtr = (uint) packet;
- rtx.txbd[txIdx].length = length;
- rtx.txbd[txIdx].status |=
- (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT);
+ out_be32(&txbd[tx_idx].bufptr, (u32)packet);
+ out_be16(&txbd[tx_idx].length, length);
+ status = in_be16(&txbd[tx_idx].status);
+ out_be16(&txbd[tx_idx].status, status |
+ (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT));
/* Tell the DMA to go */
out_be32(®s->tstat, TSTAT_CLEAR_THALT);
/* Wait for buffer to be transmitted */
- for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
+ for (i = 0; in_be16(&txbd[tx_idx].status) & TXBD_READY; i++) {
if (i >= TOUT_LOOP) {
debug("%s: tsec: tx error\n", dev->name);
return result;
}
}
- txIdx = (txIdx + 1) % TX_BUF_CNT;
- result = rtx.txbd[txIdx].status & TXBD_STATS;
+ tx_idx = (tx_idx + 1) % TX_BUF_CNT;
+ result = in_be16(&txbd[tx_idx].status) & TXBD_STATS;
return result;
}
static int tsec_recv(struct eth_device *dev)
{
- int length;
struct tsec_private *priv = (struct tsec_private *)dev->priv;
- tsec_t *regs = priv->regs;
+ struct tsec __iomem *regs = priv->regs;
- while (!(rtx.rxbd[rxIdx].status & RXBD_EMPTY)) {
-
- length = rtx.rxbd[rxIdx].length;
+ while (!(in_be16(&rxbd[rx_idx].status) & RXBD_EMPTY)) {
+ int length = in_be16(&rxbd[rx_idx].length);
+ uint16_t status = in_be16(&rxbd[rx_idx].status);
/* Send the packet up if there were no errors */
- if (!(rtx.rxbd[rxIdx].status & RXBD_STATS)) {
- NetReceive(NetRxPackets[rxIdx], length - 4);
- } else {
- printf("Got error %x\n",
- (rtx.rxbd[rxIdx].status & RXBD_STATS));
- }
+ if (!(status & RXBD_STATS))
+ NetReceive(NetRxPackets[rx_idx], length - 4);
+ else
+ printf("Got error %x\n", (status & RXBD_STATS));
- rtx.rxbd[rxIdx].length = 0;
+ out_be16(&rxbd[rx_idx].length, 0);
+ status = RXBD_EMPTY;
/* Set the wrap bit if this is the last element in the list */
- rtx.rxbd[rxIdx].status =
- RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0);
+ if ((rx_idx + 1) == PKTBUFSRX)
+ status |= RXBD_WRAP;
+ out_be16(&rxbd[rx_idx].status, status);
- rxIdx = (rxIdx + 1) % PKTBUFSRX;
+ rx_idx = (rx_idx + 1) % PKTBUFSRX;
}
if (in_be32(®s->ievent) & IEVENT_BSY) {
@@ -453,7 +451,7 @@
static void tsec_halt(struct eth_device *dev)
{
struct tsec_private *priv = (struct tsec_private *)dev->priv;
- tsec_t *regs = priv->regs;
+ struct tsec __iomem *regs = priv->regs;
clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
setbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
@@ -475,11 +473,9 @@
*/
static int tsec_init(struct eth_device *dev, bd_t * bd)
{
- uint tempval;
- char tmpbuf[MAC_ADDR_LEN];
- int i;
struct tsec_private *priv = (struct tsec_private *)dev->priv;
- tsec_t *regs = priv->regs;
+ struct tsec __iomem *regs = priv->regs;
+ u32 tempval;
int ret;
/* Make sure the controller is stopped */
@@ -492,16 +488,16 @@
out_be32(®s->ecntrl, ECNTRL_INIT_SETTINGS);
/* Copy the station address into the address registers.
- * Backwards, because little endian MACS are dumb */
- for (i = 0; i < MAC_ADDR_LEN; i++)
- tmpbuf[MAC_ADDR_LEN - 1 - i] = dev->enetaddr[i];
-
- tempval = (tmpbuf[0] << 24) | (tmpbuf[1] << 16) | (tmpbuf[2] << 8) |
- tmpbuf[3];
+ * For a station address of 0x12345678ABCD in transmission
+ * order (BE), MACnADDR1 is set to 0xCDAB7856 and
+ * MACnADDR2 is set to 0x34120000.
+ */
+ tempval = (dev->enetaddr[5] << 24) | (dev->enetaddr[4] << 16) |
+ (dev->enetaddr[3] << 8) | dev->enetaddr[2];
out_be32(®s->macstnaddr1, tempval);
- tempval = *((uint *) (tmpbuf + 4));
+ tempval = (dev->enetaddr[1] << 24) | (dev->enetaddr[0] << 16);
out_be32(®s->macstnaddr2, tempval);
@@ -527,7 +523,7 @@
static phy_interface_t tsec_get_interface(struct tsec_private *priv)
{
- tsec_t *regs = priv->regs;
+ struct tsec __iomem *regs = priv->regs;
u32 ecntrl;
ecntrl = in_be32(®s->ecntrl);
@@ -576,7 +572,7 @@
{
struct tsec_private *priv = (struct tsec_private *)dev->priv;
struct phy_device *phydev;
- tsec_t *regs = priv->regs;
+ struct tsec __iomem *regs = priv->regs;
u32 supported = (SUPPORTED_10baseT_Half |
SUPPORTED_10baseT_Full |
SUPPORTED_100baseT_Half |
@@ -626,7 +622,6 @@
if (NULL == priv)
return 0;
- privlist[num_tsecs++] = priv;
priv->regs = tsec_info->regs;
priv->phyregs_sgmii = tsec_info->miiregs_sgmii;
@@ -684,7 +679,7 @@
{
struct fsl_pq_mdio_info info;
- info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
+ info.regs = TSEC_GET_MDIO_REGS_BASE(1);
info.name = DEFAULT_MII_NAME;
fsl_pq_mdio_init(bis, &info);
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index 236a753..6a017a8 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -43,11 +43,6 @@
#define ZYNQ_GEM_TXBUF_WRAP_MASK 0x40000000
#define ZYNQ_GEM_TXBUF_LAST_MASK 0x00008000 /* Last buffer */
-#define ZYNQ_GEM_TXSR_HRESPNOK_MASK 0x00000100 /* Transmit hresp not OK */
-#define ZYNQ_GEM_TXSR_URUN_MASK 0x00000040 /* Transmit underrun */
-/* Transmit buffs exhausted mid frame */
-#define ZYNQ_GEM_TXSR_BUFEXH_MASK 0x00000010
-
#define ZYNQ_GEM_NWCTRL_TXEN_MASK 0x00000008 /* Enable transmit */
#define ZYNQ_GEM_NWCTRL_RXEN_MASK 0x00000004 /* Enable receive */
#define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */
@@ -90,6 +85,11 @@
*/
#define PHY_DETECT_MASK 0x1808
+/* TX BD status masks */
+#define ZYNQ_GEM_TXBUF_FRMLEN_MASK 0x000007ff
+#define ZYNQ_GEM_TXBUF_EXHAUSTED 0x08000000
+#define ZYNQ_GEM_TXBUF_UNDERRUN 0x10000000
+
/* Device registers */
struct zynq_gem_regs {
u32 nwctrl; /* Network Control reg */
@@ -123,12 +123,18 @@
};
#define RX_BUF 3
+/* Page table entries are set to 1MB, or multiples of 1MB
+ * (not < 1MB). driver uses less bd's so use 1MB bdspace.
+ */
+#define BD_SPACE 0x100000
+/* BD separation space */
+#define BD_SEPRN_SPACE 64
/* Initialized, rxbd_current, rx_first_buf must be 0 after init */
struct zynq_gem_priv {
- struct emac_bd tx_bd;
- struct emac_bd rx_bd[RX_BUF];
- char rxbuffers[RX_BUF * PKTSIZE_ALIGN];
+ struct emac_bd *tx_bd;
+ struct emac_bd *rx_bd;
+ char *rxbuffers;
u32 rxbd_current;
u32 rx_first_buf;
int phyaddr;
@@ -299,20 +305,18 @@
readl(®s->stat[i]);
/* Setup RxBD space */
- memset(&(priv->rx_bd), 0, sizeof(priv->rx_bd));
- /* Create the RxBD ring */
- memset(&(priv->rxbuffers), 0, sizeof(priv->rxbuffers));
+ memset(priv->rx_bd, 0, RX_BUF * sizeof(struct emac_bd));
for (i = 0; i < RX_BUF; i++) {
priv->rx_bd[i].status = 0xF0000000;
priv->rx_bd[i].addr =
- (u32)((char *)&(priv->rxbuffers) +
+ ((u32)(priv->rxbuffers) +
(i * PKTSIZE_ALIGN));
}
/* WRAP bit to last BD */
priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK;
/* Write RxBDs to IP */
- writel((u32)&(priv->rx_bd), ®s->rxqbase);
+ writel((u32)priv->rx_bd, ®s->rxqbase);
/* Setup for DMA Configuration register */
writel(ZYNQ_GEM_DMACR_INIT, ®s->dmacr);
@@ -368,32 +372,35 @@
static int zynq_gem_send(struct eth_device *dev, void *ptr, int len)
{
- u32 status;
+ u32 addr, size;
struct zynq_gem_priv *priv = dev->priv;
struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
- const u32 mask = ZYNQ_GEM_TXSR_HRESPNOK_MASK | \
- ZYNQ_GEM_TXSR_URUN_MASK | ZYNQ_GEM_TXSR_BUFEXH_MASK;
/* setup BD */
- writel((u32)&(priv->tx_bd), ®s->txqbase);
+ writel((u32)priv->tx_bd, ®s->txqbase);
/* Setup Tx BD */
- memset((void *)&(priv->tx_bd), 0, sizeof(struct emac_bd));
+ memset(priv->tx_bd, 0, sizeof(struct emac_bd));
- priv->tx_bd.addr = (u32)ptr;
- priv->tx_bd.status = len | ZYNQ_GEM_TXBUF_LAST_MASK;
+ priv->tx_bd->addr = (u32)ptr;
+ priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) |
+ ZYNQ_GEM_TXBUF_LAST_MASK;
+
+ addr = (u32) ptr;
+ addr &= ~(ARCH_DMA_MINALIGN - 1);
+ size = roundup(len, ARCH_DMA_MINALIGN);
+ flush_dcache_range(addr, addr + size);
+ barrier();
/* Start transmit */
setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK);
- /* Read the stat register to know if the packet has been transmitted */
- status = readl(®s->txsr);
- if (status & mask)
- printf("Something has gone wrong here!? Status is 0x%x.\n",
- status);
+ /* Read TX BD status */
+ if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_UNDERRUN)
+ printf("TX underrun\n");
+ if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED)
+ printf("TX buffers exhausted in mid frame\n");
- /* Clear Tx status register before leaving . */
- writel(status, ®s->txsr);
return 0;
}
@@ -416,8 +423,12 @@
frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK;
if (frame_len) {
- NetReceive((u8 *) (current_bd->addr &
- ZYNQ_GEM_RXBUF_ADD_MASK), frame_len);
+ u32 addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK;
+ addr &= ~(ARCH_DMA_MINALIGN - 1);
+ u32 size = roundup(frame_len, ARCH_DMA_MINALIGN);
+ invalidate_dcache_range(addr, addr + size);
+
+ NetReceive((u8 *)addr, frame_len);
if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK)
priv->rx_first_buf = priv->rxbd_current;
@@ -471,6 +482,7 @@
{
struct eth_device *dev;
struct zynq_gem_priv *priv;
+ void *bd_space;
dev = calloc(1, sizeof(*dev));
if (dev == NULL)
@@ -483,6 +495,18 @@
}
priv = dev->priv;
+ /* Align rxbuffers to ARCH_DMA_MINALIGN */
+ priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN);
+ memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN);
+
+ /* Align bd_space to 1MB */
+ bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
+ mmu_set_region_dcache_behaviour((u32)bd_space, BD_SPACE, DCACHE_OFF);
+
+ /* Initialize the bd spaces for tx and rx bd's */
+ priv->tx_bd = (struct emac_bd *)bd_space;
+ priv->rx_bd = (struct emac_bd *)((u32)bd_space + BD_SEPRN_SPACE);
+
priv->phyaddr = phy_addr;
priv->emio = emio;
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index 99d51a6..6182a59 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -9,6 +9,7 @@
obj-$(CONFIG_PCI) += pci.o pci_auto.o
obj-$(CONFIG_PCI_INDIRECT_BRIDGE) += pci_indirect.o
obj-$(CONFIG_PCI_GT64120) += pci_gt64120.o
+obj-$(CONFIG_PCI_MSC01) += pci_msc01.o
obj-$(CONFIG_FTPCI100) += pci_ftpci100.o
obj-$(CONFIG_IXP_PCI) += pci_ixp.o
obj-$(CONFIG_SH4_PCI) += pci_sh4.o
diff --git a/drivers/pci/pci_msc01.c b/drivers/pci/pci_msc01.c
new file mode 100644
index 0000000..284ffa0
--- /dev/null
+++ b/drivers/pci/pci_msc01.c
@@ -0,0 +1,125 @@
+/*
+ * Copyright (C) 2013 Imagination Technologies
+ * Author: Paul Burton <paul.burton@imgtec.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <msc01.h>
+#include <pci.h>
+#include <pci_msc01.h>
+#include <asm/io.h>
+
+#define PCI_ACCESS_READ 0
+#define PCI_ACCESS_WRITE 1
+
+struct msc01_pci_controller {
+ struct pci_controller hose;
+ void *base;
+};
+
+static inline struct msc01_pci_controller *
+hose_to_msc01(struct pci_controller *hose)
+{
+ return container_of(hose, struct msc01_pci_controller, hose);
+}
+
+static int msc01_config_access(struct msc01_pci_controller *msc01,
+ unsigned char access_type, pci_dev_t bdf,
+ int where, u32 *data)
+{
+ const u32 aborts = MSC01_PCI_INTSTAT_MA_MSK | MSC01_PCI_INTSTAT_TA_MSK;
+ void *intstat = msc01->base + MSC01_PCI_INTSTAT_OFS;
+ void *cfgdata = msc01->base + MSC01_PCI_CFGDATA_OFS;
+ unsigned int bus = PCI_BUS(bdf);
+ unsigned int dev = PCI_DEV(bdf);
+ unsigned int devfn = PCI_DEV(bdf) << 3 | PCI_FUNC(bdf);
+
+ /* clear abort status */
+ __raw_writel(aborts, intstat);
+
+ /* setup address */
+ __raw_writel((bus << MSC01_PCI_CFGADDR_BNUM_SHF) |
+ (dev << MSC01_PCI_CFGADDR_DNUM_SHF) |
+ (devfn << MSC01_PCI_CFGADDR_FNUM_SHF) |
+ ((where / 4) << MSC01_PCI_CFGADDR_RNUM_SHF),
+ msc01->base + MSC01_PCI_CFGADDR_OFS);
+
+ /* perform access */
+ if (access_type == PCI_ACCESS_WRITE)
+ __raw_writel(*data, cfgdata);
+ else
+ *data = __raw_readl(cfgdata);
+
+ /* check for aborts */
+ if (__raw_readl(intstat) & aborts) {
+ /* clear abort status */
+ __raw_writel(aborts, intstat);
+ return -1;
+ }
+
+ return 0;
+}
+
+static int msc01_read_config_dword(struct pci_controller *hose, pci_dev_t dev,
+ int where, u32 *value)
+{
+ struct msc01_pci_controller *msc01 = hose_to_msc01(hose);
+
+ *value = 0xffffffff;
+ return msc01_config_access(msc01, PCI_ACCESS_READ, dev, where, value);
+}
+
+static int msc01_write_config_dword(struct pci_controller *hose, pci_dev_t dev,
+ int where, u32 value)
+{
+ struct msc01_pci_controller *gt = hose_to_msc01(hose);
+ u32 data = value;
+
+ return msc01_config_access(gt, PCI_ACCESS_WRITE, dev, where, &data);
+}
+
+void msc01_pci_init(void *base, unsigned long sys_bus, unsigned long sys_phys,
+ unsigned long sys_size, unsigned long mem_bus,
+ unsigned long mem_phys, unsigned long mem_size,
+ unsigned long io_bus, unsigned long io_phys,
+ unsigned long io_size)
+{
+ static struct msc01_pci_controller global_msc01;
+ struct msc01_pci_controller *msc01;
+ struct pci_controller *hose;
+
+ msc01 = &global_msc01;
+ msc01->base = base;
+
+ hose = &msc01->hose;
+
+ hose->first_busno = 0;
+ hose->last_busno = 0;
+
+ /* System memory space */
+ pci_set_region(&hose->regions[0], sys_bus, sys_phys, sys_size,
+ PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
+
+ /* PCI memory space */
+ pci_set_region(&hose->regions[1], mem_bus, mem_phys, mem_size,
+ PCI_REGION_MEM);
+
+ /* PCI I/O space */
+ pci_set_region(&hose->regions[2], io_bus, io_phys, io_size,
+ PCI_REGION_IO);
+
+ hose->region_count = 3;
+
+ pci_set_ops(hose,
+ pci_hose_read_config_byte_via_dword,
+ pci_hose_read_config_word_via_dword,
+ msc01_read_config_dword,
+ pci_hose_write_config_byte_via_dword,
+ pci_hose_write_config_word_via_dword,
+ msc01_write_config_dword);
+
+ pci_register_hose(hose);
+ hose->last_busno = pci_hose_scan(hose);
+}
diff --git a/drivers/qe/Makefile b/drivers/qe/Makefile
index b8c15f8..7f1bd06 100644
--- a/drivers/qe/Makefile
+++ b/drivers/qe/Makefile
@@ -4,5 +4,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(and $(CONFIG_QE),$(CONFIG_OF_LIBFDT)) += fdt.o
-obj-$(CONFIG_QE) += qe.o uccf.o uec.o uec_phy.o
+obj-y := qe.o uccf.o uec.o uec_phy.o
+obj-$(CONFIG_OF_LIBFDT) += fdt.o
diff --git a/drivers/rtc/mc146818.c b/drivers/rtc/mc146818.c
index 5f9d359..f7cf106 100644
--- a/drivers/rtc/mc146818.c
+++ b/drivers/rtc/mc146818.c
@@ -15,7 +15,7 @@
#include <command.h>
#include <rtc.h>
-#ifdef __I386__
+#if defined(__I386__) || defined(CONFIG_MALTA)
#include <asm/io.h>
#define in8(p) inb(p)
#define out8(p, v) outb(v, p)
diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c
index e80be8e..a3ad056 100644
--- a/drivers/spi/omap3_spi.c
+++ b/drivers/spi/omap3_spi.c
@@ -20,8 +20,7 @@
#include <asm/io.h>
#include "omap3_spi.h"
-#define WORD_LEN 8
-#define SPI_WAIT_TIMEOUT 3000000;
+#define SPI_WAIT_TIMEOUT 3000000
static void spi_reset(struct omap3_spi_slave *ds)
{
@@ -185,7 +184,7 @@
/* wordlength */
conf &= ~OMAP3_MCSPI_CHCONF_WL_MASK;
- conf |= (WORD_LEN - 1) << 7;
+ conf |= (ds->slave.wordlen - 1) << 7;
/* set chipselect polarity; manage with FORCE */
if (!(ds->mode & SPI_CS_HIGH))
@@ -223,7 +222,7 @@
spi_reset(ds);
}
-int omap3_spi_write(struct spi_slave *slave, unsigned int len, const u8 *txp,
+int omap3_spi_write(struct spi_slave *slave, unsigned int len, const void *txp,
unsigned long flags)
{
struct omap3_spi_slave *ds = to_omap3_spi(slave);
@@ -234,7 +233,8 @@
/* Enable the channel */
omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_EN);
- chconf &= ~OMAP3_MCSPI_CHCONF_TRM_MASK;
+ chconf &= ~(OMAP3_MCSPI_CHCONF_TRM_MASK | OMAP3_MCSPI_CHCONF_WL_MASK);
+ chconf |= (ds->slave.wordlen - 1) << 7;
chconf |= OMAP3_MCSPI_CHCONF_TRM_TX_ONLY;
chconf |= OMAP3_MCSPI_CHCONF_FORCE;
omap3_spi_write_chconf(ds,chconf);
@@ -250,7 +250,13 @@
}
}
/* Write the data */
- writel(txp[i], &ds->regs->channel[ds->slave.cs].tx);
+ unsigned int *tx = &ds->regs->channel[ds->slave.cs].tx;
+ if (ds->slave.wordlen > 16)
+ writel(((u32 *)txp)[i], tx);
+ else if (ds->slave.wordlen > 8)
+ writel(((u16 *)txp)[i], tx);
+ else
+ writel(((u8 *)txp)[i], tx);
}
/* wait to finish of transfer */
@@ -268,7 +274,7 @@
return 0;
}
-int omap3_spi_read(struct spi_slave *slave, unsigned int len, u8 *rxp,
+int omap3_spi_read(struct spi_slave *slave, unsigned int len, void *rxp,
unsigned long flags)
{
struct omap3_spi_slave *ds = to_omap3_spi(slave);
@@ -279,7 +285,8 @@
/* Enable the channel */
omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_EN);
- chconf &= ~OMAP3_MCSPI_CHCONF_TRM_MASK;
+ chconf &= ~(OMAP3_MCSPI_CHCONF_TRM_MASK | OMAP3_MCSPI_CHCONF_WL_MASK);
+ chconf |= (ds->slave.wordlen - 1) << 7;
chconf |= OMAP3_MCSPI_CHCONF_TRM_RX_ONLY;
chconf |= OMAP3_MCSPI_CHCONF_FORCE;
omap3_spi_write_chconf(ds,chconf);
@@ -302,7 +309,13 @@
omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_DIS);
/* Read the data */
- rxp[i] = readl(&ds->regs->channel[ds->slave.cs].rx);
+ unsigned int *rx = &ds->regs->channel[ds->slave.cs].rx;
+ if (ds->slave.wordlen > 16)
+ ((u32 *)rxp)[i] = readl(rx);
+ else if (ds->slave.wordlen > 8)
+ ((u16 *)rxp)[i] = (u16)readl(rx);
+ else
+ ((u8 *)rxp)[i] = (u8)readl(rx);
}
if (flags & SPI_XFER_END) {
@@ -314,8 +327,8 @@
}
/*McSPI Transmit Receive Mode*/
-int omap3_spi_txrx(struct spi_slave *slave,
- unsigned int len, const u8 *txp, u8 *rxp, unsigned long flags)
+int omap3_spi_txrx(struct spi_slave *slave, unsigned int len,
+ const void *txp, void *rxp, unsigned long flags)
{
struct omap3_spi_slave *ds = to_omap3_spi(slave);
int timeout = SPI_WAIT_TIMEOUT;
@@ -327,7 +340,8 @@
omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_EN);
/*set TRANSMIT-RECEIVE Mode*/
- chconf &= ~OMAP3_MCSPI_CHCONF_TRM_MASK;
+ chconf &= ~(OMAP3_MCSPI_CHCONF_TRM_MASK | OMAP3_MCSPI_CHCONF_WL_MASK);
+ chconf |= (ds->slave.wordlen - 1) << 7;
chconf |= OMAP3_MCSPI_CHCONF_FORCE;
omap3_spi_write_chconf(ds,chconf);
@@ -344,7 +358,13 @@
}
}
/* Write the data */
- writel(txp[i], &ds->regs->channel[ds->slave.cs].tx);
+ unsigned int *tx = &ds->regs->channel[ds->slave.cs].tx;
+ if (ds->slave.wordlen > 16)
+ writel(((u32 *)txp)[i], tx);
+ else if (ds->slave.wordlen > 8)
+ writel(((u16 *)txp)[i], tx);
+ else
+ writel(((u8 *)txp)[i], tx);
/*Read: wait for RX containing data (RXS == 1)*/
while (!(readl(&ds->regs->channel[ds->slave.cs].chstat) &
@@ -356,7 +376,13 @@
}
}
/* Read the data */
- rxp[i] = readl(&ds->regs->channel[ds->slave.cs].rx);
+ unsigned int *rx = &ds->regs->channel[ds->slave.cs].rx;
+ if (ds->slave.wordlen > 16)
+ ((u32 *)rxp)[i] = readl(rx);
+ else if (ds->slave.wordlen > 8)
+ ((u16 *)rxp)[i] = (u16)readl(rx);
+ else
+ ((u8 *)rxp)[i] = (u8)readl(rx);
}
/* Disable the channel */
omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_DIS);
@@ -375,14 +401,17 @@
{
struct omap3_spi_slave *ds = to_omap3_spi(slave);
unsigned int len;
- const u8 *txp = dout;
- u8 *rxp = din;
int ret = -1;
- if (bitlen % 8)
+ if (ds->slave.wordlen < 4 || ds->slave.wordlen > 32) {
+ printf("omap3_spi: invalid wordlen %d\n", ds->slave.wordlen);
+ return -1;
+ }
+
+ if (bitlen % ds->slave.wordlen)
return -1;
- len = bitlen / 8;
+ len = bitlen / ds->slave.wordlen;
if (bitlen == 0) { /* only change CS */
int chconf = readl(&ds->regs->channel[ds->slave.cs].chconf);
@@ -400,11 +429,11 @@
ret = 0;
} else {
if (dout != NULL && din != NULL)
- ret = omap3_spi_txrx(slave, len, txp, rxp, flags);
+ ret = omap3_spi_txrx(slave, len, dout, din, flags);
else if (dout != NULL)
- ret = omap3_spi_write(slave, len, txp, flags);
+ ret = omap3_spi_write(slave, len, dout, flags);
else if (din != NULL)
- ret = omap3_spi_read(slave, len, rxp, flags);
+ ret = omap3_spi_read(slave, len, din, flags);
}
return ret;
}
diff --git a/drivers/spi/omap3_spi.h b/drivers/spi/omap3_spi.h
index 01537b6..ab7cd84 100644
--- a/drivers/spi/omap3_spi.h
+++ b/drivers/spi/omap3_spi.h
@@ -99,11 +99,11 @@
return container_of(slave, struct omap3_spi_slave, slave);
}
-int omap3_spi_txrx(struct spi_slave *slave, unsigned int len, const u8 *txp,
- u8 *rxp, unsigned long flags);
-int omap3_spi_write(struct spi_slave *slave, unsigned int len, const u8 *txp,
+int omap3_spi_txrx(struct spi_slave *slave, unsigned int len, const void *txp,
+ void *rxp, unsigned long flags);
+int omap3_spi_write(struct spi_slave *slave, unsigned int len, const void *txp,
unsigned long flags);
-int omap3_spi_read(struct spi_slave *slave, unsigned int len, u8 *rxp,
+int omap3_spi_read(struct spi_slave *slave, unsigned int len, void *rxp,
unsigned long flags);
#endif /* _OMAP3_SPI_H_ */
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index ea39d1a..b76a26c 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -8,6 +8,18 @@
#include <malloc.h>
#include <spi.h>
+int spi_set_wordlen(struct spi_slave *slave, unsigned int wordlen)
+{
+ if (wordlen == 0 || wordlen > 32) {
+ printf("spi: invalid wordlen %d\n", wordlen);
+ return -1;
+ }
+
+ slave->wordlen = wordlen;
+
+ return 0;
+}
+
void *spi_do_alloc_slave(int offset, int size, unsigned int bus,
unsigned int cs)
{
@@ -20,6 +32,7 @@
slave = (struct spi_slave *)(ptr + offset);
slave->bus = bus;
slave->cs = cs;
+ slave->wordlen = SPI_DEFAULT_WORDLEN;
}
return ptr;
diff --git a/drivers/tpm/Makefile b/drivers/tpm/Makefile
index 4b8cbec..2f2353f 100644
--- a/drivers/tpm/Makefile
+++ b/drivers/tpm/Makefile
@@ -3,8 +3,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-$(shell mkdir -p $(obj)slb9635_i2c)
-
# TODO: Merge tpm_tis_lpc.c with tpm.c
obj-$(CONFIG_TPM_ATMEL_TWI) += tpm_atmel_twi.o
obj-$(CONFIG_TPM_TIS_I2C) += tpm.o
diff --git a/drivers/tpm/tis_i2c.c b/drivers/tpm/tis_i2c.c
deleted file mode 100644
index 22554e1..0000000
--- a/drivers/tpm/tis_i2c.c
+++ /dev/null
@@ -1,185 +0,0 @@
-/*
- * Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <config.h>
-#include <common.h>
-#include <fdtdec.h>
-#include <i2c.h>
-#include "slb9635_i2c/tpm.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* TPM configuration */
-struct tpm {
- int i2c_bus;
- int slave_addr;
- char inited;
- int old_bus;
-} tpm;
-
-
-static int tpm_select(void)
-{
- int ret;
-
- tpm.old_bus = i2c_get_bus_num();
- if (tpm.old_bus != tpm.i2c_bus) {
- ret = i2c_set_bus_num(tpm.i2c_bus);
- if (ret) {
- debug("%s: Fail to set i2c bus %d\n", __func__,
- tpm.i2c_bus);
- return -1;
- }
- }
- return 0;
-}
-
-static int tpm_deselect(void)
-{
- int ret;
-
- if (tpm.old_bus != i2c_get_bus_num()) {
- ret = i2c_set_bus_num(tpm.old_bus);
- if (ret) {
- debug("%s: Fail to restore i2c bus %d\n",
- __func__, tpm.old_bus);
- return -1;
- }
- }
- tpm.old_bus = -1;
- return 0;
-}
-
-/**
- * Decode TPM configuration.
- *
- * @param dev Returns a configuration of TPM device
- * @return 0 if ok, -1 on error
- */
-static int tpm_decode_config(struct tpm *dev)
-{
-#ifdef CONFIG_OF_CONTROL
- const void *blob = gd->fdt_blob;
- int node, parent;
- int i2c_bus;
-
- node = fdtdec_next_compatible(blob, 0, COMPAT_INFINEON_SLB9635_TPM);
- if (node < 0) {
- node = fdtdec_next_compatible(blob, 0,
- COMPAT_INFINEON_SLB9645_TPM);
- }
- if (node < 0) {
- debug("%s: Node not found\n", __func__);
- return -1;
- }
- parent = fdt_parent_offset(blob, node);
- if (parent < 0) {
- debug("%s: Cannot find node parent\n", __func__);
- return -1;
- }
- i2c_bus = i2c_get_bus_num_fdt(parent);
- if (i2c_bus < 0)
- return -1;
- dev->i2c_bus = i2c_bus;
- dev->slave_addr = fdtdec_get_addr(blob, node, "reg");
-#else
- dev->i2c_bus = CONFIG_INFINEON_TPM_I2C_BUS;
- dev->slave_addr = CONFIG_INFINEON_TPM_I2C_ADDR;
-#endif
- return 0;
-}
-
-int tis_init(void)
-{
- if (tpm.inited)
- return 0;
-
- if (tpm_decode_config(&tpm))
- return -1;
-
- if (tpm_select())
- return -1;
-
- /*
- * Probe TPM twice; the first probing might fail because TPM is asleep,
- * and the probing can wake up TPM.
- */
- if (i2c_probe(tpm.slave_addr) && i2c_probe(tpm.slave_addr)) {
- debug("%s: fail to probe i2c addr 0x%x\n", __func__,
- tpm.slave_addr);
- return -1;
- }
-
- tpm_deselect();
-
- tpm.inited = 1;
-
- return 0;
-}
-
-int tis_open(void)
-{
- int rc;
-
- if (!tpm.inited)
- return -1;
-
- if (tpm_select())
- return -1;
-
- rc = tpm_open(tpm.slave_addr);
-
- tpm_deselect();
-
- return rc;
-}
-
-int tis_close(void)
-{
- if (!tpm.inited)
- return -1;
-
- if (tpm_select())
- return -1;
-
- tpm_close();
-
- tpm_deselect();
-
- return 0;
-}
-
-int tis_sendrecv(const uint8_t *sendbuf, size_t sbuf_size,
- uint8_t *recvbuf, size_t *rbuf_len)
-{
- int len;
- uint8_t buf[4096];
-
- if (!tpm.inited)
- return -1;
-
- if (sizeof(buf) < sbuf_size)
- return -1;
-
- memcpy(buf, sendbuf, sbuf_size);
-
- if (tpm_select())
- return -1;
-
- len = tpm_transmit(buf, sbuf_size);
-
- tpm_deselect();
-
- if (len < 10) {
- *rbuf_len = 0;
- return -1;
- }
-
- memcpy(recvbuf, buf, len);
- *rbuf_len = len;
-
- return 0;
-}
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index fed1c9c..a7f5469 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -18,6 +18,7 @@
obj-$(CONFIG_L5F31188) += l5f31188.o
obj-$(CONFIG_MPC8XX_LCD) += mpc8xx_lcd.o
obj-$(CONFIG_PXA_LCD) += pxa_lcd.o
+obj-$(CONFIG_SCF0403_LCD) += scf0403_lcd.o
obj-$(CONFIG_S6E8AX0) += s6e8ax0.o
obj-$(CONFIG_S6E63D6) += s6e63d6.o
obj-$(CONFIG_LD9040) += ld9040.o
diff --git a/drivers/video/bcm2835.c b/drivers/video/bcm2835.c
index 58a6163..1f18231 100644
--- a/drivers/video/bcm2835.c
+++ b/drivers/video/bcm2835.c
@@ -14,6 +14,8 @@
/* Global variables that lcd.c expects to exist */
vidinfo_t panel_info;
+static u32 bcm2835_pitch;
+
struct msg_query {
struct bcm2835_mbox_hdr hdr;
struct bcm2835_mbox_tag_physical_w_h physical_w_h;
@@ -30,6 +32,7 @@
struct bcm2835_mbox_tag_virtual_offset virtual_offset;
struct bcm2835_mbox_tag_overscan overscan;
struct bcm2835_mbox_tag_allocate_buffer allocate_buffer;
+ struct bcm2835_mbox_tag_pitch pitch;
u32 end_tag;
};
@@ -80,6 +83,7 @@
msg_setup->overscan.body.req.right = 0;
BCM2835_MBOX_INIT_TAG(&msg_setup->allocate_buffer, ALLOCATE_BUFFER);
msg_setup->allocate_buffer.body.req.alignment = 0x100;
+ BCM2835_MBOX_INIT_TAG_NO_REQ(&msg_setup->pitch, GET_PITCH);
ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg_setup->hdr);
if (ret) {
@@ -90,6 +94,7 @@
w = msg_setup->physical_w_h.body.resp.width;
h = msg_setup->physical_w_h.body.resp.height;
+ bcm2835_pitch = msg_setup->pitch.body.resp.pitch;
debug("bcm2835: Final resolution is %d x %d\n", w, h);
@@ -103,3 +108,9 @@
void lcd_enable(void)
{
}
+
+int lcd_get_size(int *line_length)
+{
+ *line_length = bcm2835_pitch;
+ return *line_length * panel_info.vl_row;
+}
diff --git a/drivers/video/scf0403_lcd.c b/drivers/video/scf0403_lcd.c
new file mode 100644
index 0000000..2bc8bca
--- /dev/null
+++ b/drivers/video/scf0403_lcd.c
@@ -0,0 +1,296 @@
+/*
+ * scf0403.c -- support for DataImage SCF0403 LCD
+ *
+ * Copyright (c) 2013 Adapted from Linux driver:
+ * Copyright (c) 2012 Anders Electronics plc. All Rights Reserved.
+ * Copyright (c) 2012 CompuLab, Ltd
+ * Dmitry Lifshitz <lifshitz@compulab.co.il>
+ * Ilya Ledvich <ilya@compulab.co.il>
+ * Inspired by Alberto Panizzo <maramaopercheseimorto@gmail.com> &
+ * Marek Vasut work in l4f00242t03.c
+ *
+ * U-Boot port: Nikita Kiryanov <nikita@compulab.co.il>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/gpio.h>
+#include <spi.h>
+
+struct scf0403_cmd {
+ u16 cmd;
+ u16 *params;
+ int count;
+};
+
+struct scf0403_initseq_entry {
+ struct scf0403_cmd cmd;
+ int delay_ms;
+};
+
+struct scf0403_priv {
+ struct spi_slave *spi;
+ unsigned int reset_gpio;
+ u32 rddid;
+ struct scf0403_initseq_entry *init_seq;
+ int seq_size;
+};
+
+struct scf0403_priv priv;
+
+#define SCF0403852GGU04_ID 0x000080
+
+/* SCF0403526GGU20 model commands parameters */
+static u16 extcmd_params_sn20[] = {0xff, 0x98, 0x06};
+static u16 spiinttype_params_sn20[] = {0x60};
+static u16 bc_params_sn20[] = {
+ 0x01, 0x10, 0x61, 0x74, 0x01, 0x01, 0x1B,
+ 0x12, 0x71, 0x00, 0x00, 0x00, 0x01, 0x01,
+ 0x05, 0x00, 0xFF, 0xF2, 0x01, 0x00, 0x40,
+};
+static u16 bd_params_sn20[] = {0x01, 0x23, 0x45, 0x67, 0x01, 0x23, 0x45, 0x67};
+static u16 be_params_sn20[] = {
+ 0x01, 0x22, 0x22, 0xBA, 0xDC, 0x26, 0x28, 0x22, 0x22,
+};
+static u16 vcom_params_sn20[] = {0x74};
+static u16 vmesur_params_sn20[] = {0x7F, 0x0F, 0x00};
+static u16 powerctl_params_sn20[] = {0x03, 0x0b, 0x00};
+static u16 lvglvolt_params_sn20[] = {0x08};
+static u16 engsetting_params_sn20[] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x20};
+static u16 dispfunc_params_sn20[] = {0xa0};
+static u16 dvddvolt_params_sn20[] = {0x74};
+static u16 dispinv_params_sn20[] = {0x00, 0x00, 0x00};
+static u16 panelres_params_sn20[] = {0x82};
+static u16 framerate_params_sn20[] = {0x00, 0x13, 0x13};
+static u16 timing_params_sn20[] = {0x80, 0x05, 0x40, 0x28};
+static u16 powerctl2_params_sn20[] = {0x17, 0x75, 0x79, 0x20};
+static u16 memaccess_params_sn20[] = {0x00};
+static u16 pixfmt_params_sn20[] = {0x66};
+static u16 pgamma_params_sn20[] = {
+ 0x00, 0x03, 0x0b, 0x0c, 0x0e, 0x08, 0xc5, 0x04,
+ 0x08, 0x0c, 0x13, 0x11, 0x11, 0x14, 0x0c, 0x10,
+};
+static u16 ngamma_params_sn20[] = {
+ 0x00, 0x0d, 0x11, 0x0c, 0x0c, 0x04, 0x76, 0x03,
+ 0x08, 0x0b, 0x16, 0x10, 0x0d, 0x16, 0x0a, 0x00,
+};
+static u16 tearing_params_sn20[] = {0x00};
+
+/* SCF0403852GGU04 model commands parameters */
+static u16 memaccess_params_sn04[] = {0x08};
+static u16 pixfmt_params_sn04[] = {0x66};
+static u16 modectl_params_sn04[] = {0x01};
+static u16 dispfunc_params_sn04[] = {0x22, 0xe2, 0xFF, 0x04};
+static u16 vcom_params_sn04[] = {0x00, 0x6A};
+static u16 pgamma_params_sn04[] = {
+ 0x00, 0x07, 0x0d, 0x10, 0x13, 0x19, 0x0f, 0x0c,
+ 0x05, 0x08, 0x06, 0x13, 0x0f, 0x30, 0x20, 0x1f,
+};
+static u16 ngamma_params_sn04[] = {
+ 0x1F, 0x20, 0x30, 0x0F, 0x13, 0x06, 0x08, 0x05,
+ 0x0C, 0x0F, 0x19, 0x13, 0x10, 0x0D, 0x07, 0x00,
+};
+static u16 dispinv_params_sn04[] = {0x02};
+
+/* Common commands */
+static struct scf0403_cmd scf0403_cmd_slpout = {0x11, NULL, 0};
+static struct scf0403_cmd scf0403_cmd_dison = {0x29, NULL, 0};
+
+/* SCF0403852GGU04 init sequence */
+static struct scf0403_initseq_entry scf0403_initseq_sn04[] = {
+ {{0x36, memaccess_params_sn04, ARRAY_SIZE(memaccess_params_sn04)}, 0},
+ {{0x3A, pixfmt_params_sn04, ARRAY_SIZE(pixfmt_params_sn04)}, 0},
+ {{0xB6, dispfunc_params_sn04, ARRAY_SIZE(dispfunc_params_sn04)}, 0},
+ {{0xC5, vcom_params_sn04, ARRAY_SIZE(vcom_params_sn04)}, 0},
+ {{0xE0, pgamma_params_sn04, ARRAY_SIZE(pgamma_params_sn04)}, 0},
+ {{0xE1, ngamma_params_sn04, ARRAY_SIZE(ngamma_params_sn04)}, 20},
+ {{0xB0, modectl_params_sn04, ARRAY_SIZE(modectl_params_sn04)}, 0},
+ {{0xB4, dispinv_params_sn04, ARRAY_SIZE(dispinv_params_sn04)}, 100},
+};
+
+/* SCF0403526GGU20 init sequence */
+static struct scf0403_initseq_entry scf0403_initseq_sn20[] = {
+ {{0xff, extcmd_params_sn20, ARRAY_SIZE(extcmd_params_sn20)}, 0},
+ {{0xba, spiinttype_params_sn20, ARRAY_SIZE(spiinttype_params_sn20)}, 0},
+ {{0xbc, bc_params_sn20, ARRAY_SIZE(bc_params_sn20)}, 0},
+ {{0xbd, bd_params_sn20, ARRAY_SIZE(bd_params_sn20)}, 0},
+ {{0xbe, be_params_sn20, ARRAY_SIZE(be_params_sn20)}, 0},
+ {{0xc7, vcom_params_sn20, ARRAY_SIZE(vcom_params_sn20)}, 0},
+ {{0xed, vmesur_params_sn20, ARRAY_SIZE(vmesur_params_sn20)}, 0},
+ {{0xc0, powerctl_params_sn20, ARRAY_SIZE(powerctl_params_sn20)}, 0},
+ {{0xfc, lvglvolt_params_sn20, ARRAY_SIZE(lvglvolt_params_sn20)}, 0},
+ {{0xb6, dispfunc_params_sn20, ARRAY_SIZE(dispfunc_params_sn20)}, 0},
+ {{0xdf, engsetting_params_sn20, ARRAY_SIZE(engsetting_params_sn20)}, 0},
+ {{0xf3, dvddvolt_params_sn20, ARRAY_SIZE(dvddvolt_params_sn20)}, 0},
+ {{0xb4, dispinv_params_sn20, ARRAY_SIZE(dispinv_params_sn20)}, 0},
+ {{0xf7, panelres_params_sn20, ARRAY_SIZE(panelres_params_sn20)}, 0},
+ {{0xb1, framerate_params_sn20, ARRAY_SIZE(framerate_params_sn20)}, 0},
+ {{0xf2, timing_params_sn20, ARRAY_SIZE(timing_params_sn20)}, 0},
+ {{0xc1, powerctl2_params_sn20, ARRAY_SIZE(powerctl2_params_sn20)}, 0},
+ {{0x36, memaccess_params_sn20, ARRAY_SIZE(memaccess_params_sn20)}, 0},
+ {{0x3a, pixfmt_params_sn20, ARRAY_SIZE(pixfmt_params_sn20)}, 0},
+ {{0xe0, pgamma_params_sn20, ARRAY_SIZE(pgamma_params_sn20)}, 0},
+ {{0xe1, ngamma_params_sn20, ARRAY_SIZE(ngamma_params_sn20)}, 0},
+ {{0x35, tearing_params_sn20, ARRAY_SIZE(tearing_params_sn20)}, 0},
+};
+
+static void scf0403_gpio_reset(unsigned int gpio)
+{
+ if (!gpio_is_valid(gpio))
+ return;
+
+ gpio_set_value(gpio, 1);
+ mdelay(100);
+ gpio_set_value(gpio, 0);
+ mdelay(40);
+ gpio_set_value(gpio, 1);
+ mdelay(100);
+}
+
+static int scf0403_spi_read_rddid(struct spi_slave *spi, u32 *rddid)
+{
+ int error = 0;
+ u8 ids_buf = 0x00;
+ u16 dummy_buf = 0x00;
+ u16 cmd = 0x04;
+
+ error = spi_set_wordlen(spi, 9);
+ if (error)
+ return error;
+
+ /* Here 9 bits required to transmit a command */
+ error = spi_xfer(spi, 9, &cmd, NULL, SPI_XFER_ONCE);
+ if (error)
+ return error;
+
+ /*
+ * Here 8 + 1 bits required to arrange extra clock cycle
+ * before the first data bit.
+ * According to the datasheet - first parameter is the dummy data.
+ */
+ error = spi_xfer(spi, 9, NULL, &dummy_buf, SPI_XFER_ONCE);
+ if (error)
+ return error;
+
+ error = spi_set_wordlen(spi, 8);
+ if (error)
+ return error;
+
+ /* Read rest of the data */
+ error = spi_xfer(spi, 8, NULL, &ids_buf, SPI_XFER_ONCE);
+ if (error)
+ return error;
+
+ *rddid = ids_buf;
+
+ return 0;
+}
+
+static int scf0403_spi_transfer(struct spi_slave *spi, struct scf0403_cmd *cmd)
+{
+ int i, error;
+ u32 command = cmd->cmd;
+ u32 msg;
+
+ error = spi_set_wordlen(spi, 9);
+ if (error)
+ return error;
+
+ error = spi_xfer(spi, 9, &command, NULL, SPI_XFER_ONCE);
+ if (error)
+ return error;
+
+ for (i = 0; i < cmd->count; i++) {
+ msg = (cmd->params[i] | 0x100);
+ error = spi_xfer(spi, 9, &msg, NULL, SPI_XFER_ONCE);
+ if (error)
+ return error;
+ }
+
+ return 0;
+}
+
+static void scf0403_lcd_init(struct scf0403_priv *priv)
+{
+ int i;
+
+ /* reset LCD */
+ scf0403_gpio_reset(priv->reset_gpio);
+
+ for (i = 0; i < priv->seq_size; i++) {
+ if (scf0403_spi_transfer(priv->spi, &priv->init_seq[i].cmd) < 0)
+ puts("SPI transfer failed\n");
+
+ mdelay(priv->init_seq[i].delay_ms);
+ }
+}
+
+static int scf0403_request_reset_gpio(unsigned gpio)
+{
+ int err = gpio_request(gpio, "lcd reset");
+
+ if (err)
+ return err;
+
+ err = gpio_direction_output(gpio, 0);
+ if (err)
+ gpio_free(gpio);
+
+ return err;
+}
+
+int scf0403_init(int reset_gpio)
+{
+ int error;
+
+ if (gpio_is_valid(reset_gpio)) {
+ error = scf0403_request_reset_gpio(reset_gpio);
+ if (error) {
+ printf("Failed requesting reset GPIO%d: %d\n",
+ reset_gpio, error);
+ return error;
+ }
+ }
+
+ priv.reset_gpio = reset_gpio;
+ priv.spi = spi_setup_slave(3, 0, 1000000, SPI_MODE_0);
+ error = spi_claim_bus(priv.spi);
+ if (error)
+ goto bus_claim_fail;
+
+ /* reset LCD */
+ scf0403_gpio_reset(reset_gpio);
+
+ error = scf0403_spi_read_rddid(priv.spi, &priv.rddid);
+ if (error) {
+ puts("IDs read failed\n");
+ goto readid_fail;
+ }
+
+ if (priv.rddid == SCF0403852GGU04_ID) {
+ priv.init_seq = scf0403_initseq_sn04;
+ priv.seq_size = ARRAY_SIZE(scf0403_initseq_sn04);
+ } else {
+ priv.init_seq = scf0403_initseq_sn20;
+ priv.seq_size = ARRAY_SIZE(scf0403_initseq_sn20);
+ }
+
+ scf0403_lcd_init(&priv);
+
+ /* Start operation */
+ scf0403_spi_transfer(priv.spi, &scf0403_cmd_dison);
+ mdelay(100);
+ scf0403_spi_transfer(priv.spi, &scf0403_cmd_slpout);
+ spi_release_bus(priv.spi);
+
+ return 0;
+
+readid_fail:
+ spi_release_bus(priv.spi);
+bus_claim_fail:
+ if (gpio_is_valid(priv.reset_gpio))
+ gpio_free(priv.reset_gpio);
+
+ return error;
+}
diff --git a/examples/api/Makefile b/examples/api/Makefile
index 33cc91b..cad10a3 100644
--- a/examples/api/Makefile
+++ b/examples/api/Makefile
@@ -14,25 +14,22 @@
include $(TOPDIR)/config.mk
# Resulting ELF and binary exectuables will be named demo and demo.bin
-OUTPUT-$(CONFIG_API) = $(obj)demo
-OUTPUT = $(OUTPUT-y)
+OUTPUT = $(obj)demo
# Source files located in the examples/api directory
-SOBJ_FILES-$(CONFIG_API) += crt0.o
-COBJ_FILES-$(CONFIG_API) += demo.o
-COBJ_FILES-$(CONFIG_API) += glue.o
-COBJ_FILES-$(CONFIG_API) += libgenwrap.o
+SOBJ_FILES-y += crt0.o
+COBJ_FILES-y += demo.o
+COBJ_FILES-y += glue.o
+COBJ_FILES-y += libgenwrap.o
# Source files which exist outside the examples/api directory
-EXT_COBJ_FILES-$(CONFIG_API) += lib/crc32.o
-EXT_COBJ_FILES-$(CONFIG_API) += lib/ctype.o
-EXT_COBJ_FILES-$(CONFIG_API) += lib/div64.o
-EXT_COBJ_FILES-$(CONFIG_API) += lib/string.o
-EXT_COBJ_FILES-$(CONFIG_API) += lib/time.o
-EXT_COBJ_FILES-$(CONFIG_API) += lib/vsprintf.o
-ifeq ($(ARCH),powerpc)
-EXT_SOBJ_FILES-$(CONFIG_API) += arch/powerpc/lib/ppcstring.o
-endif
+EXT_COBJ_FILES-y += lib/crc32.o
+EXT_COBJ_FILES-y += lib/ctype.o
+EXT_COBJ_FILES-y += lib/div64.o
+EXT_COBJ_FILES-y += lib/string.o
+EXT_COBJ_FILES-y += lib/time.o
+EXT_COBJ_FILES-y += lib/vsprintf.o
+EXT_SOBJ_FILES-$(CONFIG_PPC) += arch/powerpc/lib/ppcstring.o
# Create a list of source files so their dependencies can be auto-generated
SRCS += $(addprefix $(SRCTREE)/,$(EXT_COBJ_FILES-y:.o=.c))
@@ -46,8 +43,6 @@
OBJS += $(addprefix $(obj),$(notdir $(EXT_COBJ_FILES-y)))
OBJS += $(addprefix $(obj),$(notdir $(EXT_SOBJ_FILES-y)))
-CPPFLAGS += -I..
-
all: $(obj).depend $(OUTPUT)
#########################################################################
diff --git a/examples/standalone/Makefile b/examples/standalone/Makefile
index 4afedea..f4f102b 100644
--- a/examples/standalone/Makefile
+++ b/examples/standalone/Makefile
@@ -8,7 +8,6 @@
include $(TOPDIR)/config.mk
ELF-$(ARCH) :=
-ELF-$(BOARD) :=
ELF-$(CPU) :=
ELF-y := hello_world
@@ -20,14 +19,13 @@
ELF-mpc8xx += test_burst timer
ELF-mpc8260 += mem_to_mem_idma2intr
ELF-ppc += sched
-ELF-oxc += eepro100_eeprom
#
# Some versions of make do not handle trailing white spaces properly;
# leading to build failures. The problem was found with GNU Make 3.80.
# Using 'strip' as a workaround for the problem.
#
-ELF := $(strip $(ELF-y) $(ELF-$(ARCH)) $(ELF-$(BOARD)) $(ELF-$(CPU)))
+ELF := $(strip $(ELF-y) $(ELF-$(ARCH)) $(ELF-$(CPU)))
SREC := $(addsuffix .srec,$(ELF))
BIN := $(addsuffix .bin,$(ELF))
@@ -54,8 +52,6 @@
gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
-CPPFLAGS += -I..
-
# For PowerPC there's no need to compile standalone applications as a
# relocatable executable. The relocation data is not needed, and
# also causes the entry point of the standalone application to be
diff --git a/examples/standalone/eepro100_eeprom.c b/examples/standalone/eepro100_eeprom.c
deleted file mode 100644
index 3c7f380..0000000
--- a/examples/standalone/eepro100_eeprom.c
+++ /dev/null
@@ -1,214 +0,0 @@
-/*
- * Copyright 1998-2001 by Donald Becker.
- * This software may be used and distributed according to the terms of
- * the GNU General Public License (GPL), incorporated herein by reference.
- * Contact the author for use under other terms.
- *
- * This program must be compiled with "-O"!
- * See the bottom of this file for the suggested compile-command.
- *
- * The author may be reached as becker@scyld.com, or C/O
- * Scyld Computing Corporation
- * 410 Severn Ave., Suite 210
- * Annapolis MD 21403
- *
- * Common-sense licensing statement: Using any portion of this program in
- * your own program means that you must give credit to the original author
- * and release the resulting code under the GPL.
- */
-
-/* avoid unnecessary memcpy function */
-#define _PPC_STRING_H_
-
-#include <common.h>
-#include <exports.h>
-
-static int reset_eeprom(unsigned long ioaddr, unsigned char *hwaddr);
-
-int eepro100_eeprom(int argc, char * const argv[])
-{
- int ret = 0;
-
- unsigned char hwaddr1[6] = { 0x00, 0x00, 0x02, 0x03, 0x04, 0x05 };
- unsigned char hwaddr2[6] = { 0x00, 0x00, 0x02, 0x03, 0x04, 0x06 };
-
- app_startup(argv);
-
-#if defined(CONFIG_OXC)
- ret |= reset_eeprom(0x80000000, hwaddr1);
- ret |= reset_eeprom(0x81000000, hwaddr2);
-#endif
-
- return ret;
-}
-
-/* Default EEPROM for i82559 */
-static unsigned short default_eeprom[64] = {
- 0x0100, 0x0302, 0x0504, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
- 0xffff, 0xffff, 0x40c0, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff,
- 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
- 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
- 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
- 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
- 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
- 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff
-};
-
-static unsigned short eeprom[256];
-
-static int eeprom_size = 64;
-static int eeprom_addr_size = 6;
-
-static int debug = 0;
-
-static inline unsigned short swap16(unsigned short x)
-{
- return (((x & 0xff) << 8) | ((x & 0xff00) >> 8));
-}
-
-static inline void outw(short data, long addr)
-{
- *(volatile short *)(addr) = swap16(data);
-}
-
-static inline short inw(long addr)
-{
- return swap16(*(volatile short *)(addr));
-}
-
-void *memcpy(void *dst, const void *src, unsigned int len)
-{
- char *ret = dst;
- while (len-- > 0) {
- *ret++ = *((char *)src);
- src++;
- }
- return (void *)ret;
-}
-
-/* The EEPROM commands include the alway-set leading bit. */
-#define EE_WRITE_CMD (5)
-#define EE_READ_CMD (6)
-#define EE_ERASE_CMD (7)
-
-/* Serial EEPROM section. */
-#define EE_SHIFT_CLK 0x01 /* EEPROM shift clock. */
-#define EE_CS 0x02 /* EEPROM chip select. */
-#define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */
-#define EE_DATA_READ 0x08 /* EEPROM chip data out. */
-#define EE_ENB (0x4800 | EE_CS)
-#define EE_WRITE_0 0x4802
-#define EE_WRITE_1 0x4806
-#define EE_OFFSET 14
-
-/* Delay between EEPROM clock transitions. */
-#define eeprom_delay(ee_addr) inw(ee_addr)
-
-/* Wait for the EEPROM to finish the previous operation. */
-static int eeprom_busy_poll(long ee_ioaddr)
-{
- int i;
- outw(EE_ENB, ee_ioaddr);
- for (i = 0; i < 10000; i++) /* Typical 2000 ticks */
- if (inw(ee_ioaddr) & EE_DATA_READ)
- break;
- return i;
-}
-
-/* This executes a generic EEPROM command, typically a write or write enable.
- It returns the data output from the EEPROM, and thus may also be used for
- reads. */
-static int do_eeprom_cmd(long ioaddr, int cmd, int cmd_len)
-{
- unsigned retval = 0;
- long ee_addr = ioaddr + EE_OFFSET;
-
- if (debug > 1)
- printf(" EEPROM op 0x%x: ", cmd);
-
- outw(EE_ENB | EE_SHIFT_CLK, ee_addr);
-
- /* Shift the command bits out. */
- do {
- short dataval = (cmd & (1 << cmd_len)) ? EE_WRITE_1 : EE_WRITE_0;
- outw(dataval, ee_addr);
- eeprom_delay(ee_addr);
- if (debug > 2)
- printf("%X", inw(ee_addr) & 15);
- outw(dataval | EE_SHIFT_CLK, ee_addr);
- eeprom_delay(ee_addr);
- retval = (retval << 1) | ((inw(ee_addr) & EE_DATA_READ) ? 1 : 0);
- } while (--cmd_len >= 0);
-#if 0
- outw(EE_ENB, ee_addr);
-#endif
- /* Terminate the EEPROM access. */
- outw(EE_ENB & ~EE_CS, ee_addr);
- if (debug > 1)
- printf(" EEPROM result is 0x%5.5x.\n", retval);
- return retval;
-}
-
-static int read_eeprom(long ioaddr, int location, int addr_len)
-{
- return do_eeprom_cmd(ioaddr, ((EE_READ_CMD << addr_len) | location)
- << 16 , 3 + addr_len + 16) & 0xffff;
-}
-
-static void write_eeprom(long ioaddr, int index, int value, int addr_len)
-{
- long ee_ioaddr = ioaddr + EE_OFFSET;
- int i;
-
- /* Poll for previous op finished. */
- eeprom_busy_poll(ee_ioaddr); /* Typical 0 ticks */
- /* Enable programming modes. */
- do_eeprom_cmd(ioaddr, (0x4f << (addr_len-4)), 3 + addr_len);
- /* Do the actual write. */
- do_eeprom_cmd(ioaddr,
- (((EE_WRITE_CMD<<addr_len) | index)<<16) | (value & 0xffff),
- 3 + addr_len + 16);
- /* Poll for write finished. */
- i = eeprom_busy_poll(ee_ioaddr); /* Typical 2000 ticks */
- if (debug)
- printf(" Write finished after %d ticks.\n", i);
- /* Disable programming. This command is not instantaneous, so we check
- for busy before the next op. */
- do_eeprom_cmd(ioaddr, (0x40 << (addr_len-4)), 3 + addr_len);
- eeprom_busy_poll(ee_ioaddr);
-}
-
-static int reset_eeprom(unsigned long ioaddr, unsigned char *hwaddr)
-{
- unsigned short checksum = 0;
- int size_test;
- int i;
-
- printf("Resetting i82559 EEPROM @ 0x%08lX ... ", ioaddr);
-
- size_test = do_eeprom_cmd(ioaddr, (EE_READ_CMD << 8) << 16, 27);
- eeprom_addr_size = (size_test & 0xffe0000) == 0xffe0000 ? 8 : 6;
- eeprom_size = 1 << eeprom_addr_size;
-
- memcpy(eeprom, default_eeprom, sizeof default_eeprom);
-
- for (i = 0; i < 3; i++)
- eeprom[i] = (hwaddr[i*2+1]<<8) + hwaddr[i*2];
-
- /* Recalculate the checksum. */
- for (i = 0; i < eeprom_size - 1; i++)
- checksum += eeprom[i];
- eeprom[i] = 0xBABA - checksum;
-
- for (i = 0; i < eeprom_size; i++)
- write_eeprom(ioaddr, i, eeprom[i], eeprom_addr_size);
-
- for (i = 0; i < eeprom_size; i++)
- if (read_eeprom(ioaddr, i, eeprom_addr_size) != eeprom[i]) {
- printf("failed\n");
- return 1;
- }
-
- printf("done\n");
- return 0;
-}
diff --git a/fs/Makefile b/fs/Makefile
index bdcd746..34dc035 100644
--- a/fs/Makefile
+++ b/fs/Makefile
@@ -6,15 +6,20 @@
# SPDX-License-Identifier: GPL-2.0+
#
+ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_SPL_FAT_SUPPORT) += fat/
+else
obj-y += fs.o
-obj-y += cbfs/
-obj-y += cramfs/
-obj-y += ext4/
-obj-y += fdos/
-obj-y += jffs2/
-obj-y += reiserfs/
-obj-y += sandbox/
-obj-y += ubifs/
-obj-y += yaffs2/
-obj-y += zfs/
+obj-$(CONFIG_CMD_CBFS) += cbfs/
+obj-$(CONFIG_CMD_CRAMFS) += cramfs/
+obj-$(CONFIG_FS_EXT4) += ext4/
+obj-y += fat/
+obj-$(CONFIG_CMD_FDOS) += fdos/
+obj-$(CONFIG_CMD_JFFS2) += jffs2/
+obj-$(CONFIG_CMD_REISER) += reiserfs/
+obj-$(CONFIG_SANDBOX) += sandbox/
+obj-$(CONFIG_CMD_UBIFS) += ubifs/
+obj-$(CONFIG_YAFFS2) += yaffs2/
+obj-$(CONFIG_CMD_ZFS) += zfs/
+endif
diff --git a/fs/cbfs/Makefile b/fs/cbfs/Makefile
index 6f33d28..a106e05 100644
--- a/fs/cbfs/Makefile
+++ b/fs/cbfs/Makefile
@@ -3,4 +3,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(CONFIG_CMD_CBFS) := cbfs.o
+obj-y := cbfs.o
diff --git a/fs/cramfs/Makefile b/fs/cramfs/Makefile
index e2b2c73..12d73a3 100644
--- a/fs/cramfs/Makefile
+++ b/fs/cramfs/Makefile
@@ -5,5 +5,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(CONFIG_CMD_CRAMFS) := cramfs.o
-obj-$(CONFIG_CMD_CRAMFS) += uncompress.o
+obj-y := cramfs.o
+obj-y += uncompress.o
diff --git a/fs/ext4/Makefile b/fs/ext4/Makefile
index 0f5d399..8d15bda 100644
--- a/fs/ext4/Makefile
+++ b/fs/ext4/Makefile
@@ -9,5 +9,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(CONFIG_FS_EXT4) := ext4fs.o ext4_common.o dev.o
+obj-y := ext4fs.o ext4_common.o dev.o
obj-$(CONFIG_EXT4_WRITE) += ext4_write.o ext4_journal.o crc16.o
diff --git a/fs/fdos/Makefile b/fs/fdos/Makefile
index 95480af..2f8b5ad 100644
--- a/fs/fdos/Makefile
+++ b/fs/fdos/Makefile
@@ -10,4 +10,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(CONFIG_CMD_FDOS) := fat.o vfat.o dev.o fdos.o fs.o subdir.o
+obj-y := fat.o vfat.o dev.o fdos.o fs.o subdir.o
diff --git a/fs/jffs2/Makefile b/fs/jffs2/Makefile
index 02e481f..4cb0600 100644
--- a/fs/jffs2/Makefile
+++ b/fs/jffs2/Makefile
@@ -5,11 +5,9 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifdef CONFIG_CMD_JFFS2
obj-$(CONFIG_JFFS2_LZO) += compr_lzo.o
obj-y += compr_rtime.o
obj-y += compr_rubin.o
obj-y += compr_zlib.o
obj-y += jffs2_1pass.o
obj-y += mini_inflate.o
-endif
diff --git a/fs/reiserfs/Makefile b/fs/reiserfs/Makefile
index 55f70b1..5a692f0 100644
--- a/fs/reiserfs/Makefile
+++ b/fs/reiserfs/Makefile
@@ -9,4 +9,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(CONFIG_CMD_REISER) := reiserfs.o dev.o mode_string.o
+obj-y := reiserfs.o dev.o mode_string.o
diff --git a/fs/sandbox/Makefile b/fs/sandbox/Makefile
index faa7c16..ca238f6 100644
--- a/fs/sandbox/Makefile
+++ b/fs/sandbox/Makefile
@@ -10,4 +10,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(CONFIG_SANDBOX) := sandboxfs.o
+obj-y := sandboxfs.o
diff --git a/fs/ubifs/Makefile b/fs/ubifs/Makefile
index 47d5a8f..389b0e3 100644
--- a/fs/ubifs/Makefile
+++ b/fs/ubifs/Makefile
@@ -9,10 +9,10 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(CONFIG_CMD_UBIFS) := ubifs.o io.o super.o sb.o master.o lpt.o
-obj-$(CONFIG_CMD_UBIFS) += lpt_commit.o scan.o lprops.o
-obj-$(CONFIG_CMD_UBIFS) += tnc.o tnc_misc.o debug.o crc16.o budget.o
-obj-$(CONFIG_CMD_UBIFS) += log.o orphan.o recovery.o replay.o
+obj-y := ubifs.o io.o super.o sb.o master.o lpt.o
+obj-y += lpt_commit.o scan.o lprops.o
+obj-y += tnc.o tnc_misc.o debug.o crc16.o budget.o
+obj-y += log.o orphan.o recovery.o replay.o
# SEE README.arm-unaligned-accesses
$(obj)super.o: CFLAGS += $(PLATFORM_NO_UNALIGNED)
diff --git a/fs/yaffs2/Makefile b/fs/yaffs2/Makefile
index 077af78..d811287 100644
--- a/fs/yaffs2/Makefile
+++ b/fs/yaffs2/Makefile
@@ -16,7 +16,7 @@
#
# $Id: Makefile,v 1.15 2007/07/18 19:40:38 charles Exp $
-obj-$(CONFIG_YAFFS2) := \
+obj-y := \
yaffs_allocator.o yaffs_attribs.o yaffs_bitmap.o yaffs_uboot_glue.o\
yaffs_checkptrw.o yaffs_ecc.o yaffs_error.o \
yaffsfs.o yaffs_guts.o yaffs_nameval.o yaffs_nand.o\
diff --git a/fs/zfs/Makefile b/fs/zfs/Makefile
index 7090416..fa58b7f 100644
--- a/fs/zfs/Makefile
+++ b/fs/zfs/Makefile
@@ -5,4 +5,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(CONFIG_CMD_ZFS) := dev.o zfs.o zfs_fletcher.o zfs_sha256.o zfs_lzjb.o
+obj-y := dev.o zfs.o zfs_fletcher.o zfs_sha256.o zfs_lzjb.o
diff --git a/include/common.h b/include/common.h
index 409515f..8ca67f6 100644
--- a/include/common.h
+++ b/include/common.h
@@ -923,7 +923,7 @@
{
}
-static inline phys_addr_t map_to_sysmem(void *ptr)
+static inline phys_addr_t map_to_sysmem(const void *ptr)
{
return (phys_addr_t)(uintptr_t)ptr;
}
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/common_timing_params.h b/include/common_timing_params.h
similarity index 100%
rename from arch/powerpc/cpu/mpc8xxx/ddr/common_timing_params.h
rename to include/common_timing_params.h
diff --git a/include/configs/ASH405.h b/include/configs/ASH405.h
index 9460be3..2f53407 100644
--- a/include/configs/ASH405.h
+++ b/include/configs/ASH405.h
@@ -143,6 +143,8 @@
#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
#define CONFIG_SYS_NAND_QUIET 1
+#define CONFIG_SYS_NAND_MAX_OOBFREE 2
+#define CONFIG_SYS_NAND_MAX_ECCPOS 56
/*-----------------------------------------------------------------------
* PCI stuff
diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h
index 268f66e..b2a5c19 100644
--- a/include/configs/B4860QDS.h
+++ b/include/configs/B4860QDS.h
@@ -193,7 +193,7 @@
#define CONFIG_DDR_SPD
#define CONFIG_SYS_DDR_RAW_TIMING
-#define CONFIG_FSL_DDR3
+#define CONFIG_SYS_FSL_DDR3
#define CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SYS_SPD_BUS_NUM 0
diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h
index 036f264..499d8c2 100644
--- a/include/configs/BSC9131RDB.h
+++ b/include/configs/BSC9131RDB.h
@@ -80,7 +80,7 @@
#define CONFIG_SYS_MEMTEST_END 0x01ffffff
/* DDR Setup */
-#define CONFIG_FSL_DDR3
+#define CONFIG_SYS_FSL_DDR3
#undef CONFIG_SYS_DDR_RAW_TIMING
#undef CONFIG_DDR_SPD
#define CONFIG_SYS_SPD_BUS_NUM 0
diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h
index 75889b3..a6601fe 100644
--- a/include/configs/BSC9132QDS.h
+++ b/include/configs/BSC9132QDS.h
@@ -134,7 +134,7 @@
#define CONFIG_SYS_MEMTEST_END 0x01ffffff
/* DDR Setup */
-#define CONFIG_FSL_DDR3
+#define CONFIG_SYS_FSL_DDR3
#define CONFIG_SYS_SPD_BUS_NUM 0
#define SPD_EEPROM_ADDRESS1 0x54 /* I2C access */
#define SPD_EEPROM_ADDRESS2 0x56 /* I2C access */
diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h
index 08156c5..1cfb2c2 100644
--- a/include/configs/C29XPCIE.h
+++ b/include/configs/C29XPCIE.h
@@ -103,7 +103,7 @@
#define CONFIG_PANIC_HANG
/* DDR Setup */
-#define CONFIG_FSL_DDR3
+#define CONFIG_SYS_FSL_DDR3
#define CONFIG_DDR_SPD
#define CONFIG_SYS_SPD_BUS_NUM 0
#define SPD_EEPROM_ADDRESS 0x50
@@ -191,13 +191,14 @@
| CSPR_MSEL_NAND \
| CSPR_V)
#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
+#define CONFIG_SYS_NAND_OOBSIZE 0x00000280 /* 640b */
#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
- | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \
- | CSOR_NAND_PGS_2K /* Page Size = 2k */ \
- | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
- | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
+ | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
+ | CSOR_NAND_PGS_8K /* Page Size = 8K */ \
+ | CSOR_NAND_SPRZ_CSOR_EXT /*oob in csor_ext*/\
+ | CSOR_NAND_PB(128)) /*128 Pages Per Block*/
#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x01) | \
FTIM0_NAND_TWP(0x0c) | \
FTIM0_NAND_TWCHT(0x08) | \
@@ -224,6 +225,7 @@
#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CSOR1_EXT CONFIG_SYS_NAND_OOBSIZE
#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
diff --git a/include/configs/HWW1U1A.h b/include/configs/HWW1U1A.h
index f3f2136..bbfee7d 100644
--- a/include/configs/HWW1U1A.h
+++ b/include/configs/HWW1U1A.h
@@ -255,7 +255,7 @@
/* -------------------------------------------------------------------- */
/* FreeScale DDR2/3 SDRAM Controller */
-#define CONFIG_FSL_DDR2 /* Our SDRAM slot is DDR2 */
+#define CONFIG_SYS_FSL_DDR2 /* Our SDRAM slot is DDR2 */
#define CONFIG_DDR_ECC /* Enable ECC by default */
#define CONFIG_DDR_SPD /* Detect DDR config from SPD EEPROM */
#define CONFIG_SPD_EEPROM /* ...why 2 config variables for this? */
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index 3f742a2..a80a696 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -62,11 +62,11 @@
#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
/*
- * define CONFIG_FSL_DDR2 to use unified DDR driver
+ * define CONFIG_SYS_FSL_DDR2 to use unified DDR driver
* undefine it to use old spd_sdram.c
*/
-#define CONFIG_FSL_DDR2
-#ifdef CONFIG_FSL_DDR2
+#define CONFIG_SYS_FSL_DDR2
+#ifdef CONFIG_SYS_FSL_DDR2
#define CONFIG_SYS_SPD_BUS_NUM 0
#define SPD_EEPROM_ADDRESS1 0x52
#define SPD_EEPROM_ADDRESS2 0x51
diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index 8197f89..9ab1bc1 100644
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/MPC8536DS.h
@@ -122,7 +122,7 @@
/* DDR Setup */
#define CONFIG_VERY_BIG_RAM
-#define CONFIG_FSL_DDR2
+#define CONFIG_SYS_FSL_DDR2
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#define CONFIG_DDR_SPD
diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h
index 6689368..046b14b 100644
--- a/include/configs/MPC8540ADS.h
+++ b/include/configs/MPC8540ADS.h
@@ -78,7 +78,7 @@
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
/* DDR Setup */
-#define CONFIG_FSL_DDR1
+#define CONFIG_SYS_FSL_DDR1
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_SPD
#undef CONFIG_FSL_DDR_INTERACTIVE
diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h
index e24c597..eca3b53 100644
--- a/include/configs/MPC8541CDS.h
+++ b/include/configs/MPC8541CDS.h
@@ -51,7 +51,7 @@
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
/* DDR Setup */
-#define CONFIG_FSL_DDR1
+#define CONFIG_SYS_FSL_DDR1
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_SPD
#undef CONFIG_FSL_DDR_INTERACTIVE
diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
index 2e76df6..8132ec0 100644
--- a/include/configs/MPC8544DS.h
+++ b/include/configs/MPC8544DS.h
@@ -63,7 +63,7 @@
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
/* DDR Setup */
-#define CONFIG_FSL_DDR2
+#define CONFIG_SYS_FSL_DDR2
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#define CONFIG_DDR_SPD
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index 9ff048a..6acd54d 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -75,7 +75,7 @@
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
/* DDR Setup */
-#define CONFIG_FSL_DDR2
+#define CONFIG_SYS_FSL_DDR2
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_SPD
diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h
index 7f0f927..5ffdd01 100644
--- a/include/configs/MPC8555CDS.h
+++ b/include/configs/MPC8555CDS.h
@@ -51,7 +51,7 @@
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
/* DDR Setup */
-#define CONFIG_FSL_DDR1
+#define CONFIG_SYS_FSL_DDR1
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_SPD
#undef CONFIG_FSL_DDR_INTERACTIVE
diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h
index b7c4a60..bb9ae2d 100644
--- a/include/configs/MPC8560ADS.h
+++ b/include/configs/MPC8560ADS.h
@@ -75,7 +75,7 @@
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
/* DDR Setup */
-#define CONFIG_FSL_DDR1
+#define CONFIG_SYS_FSL_DDR1
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_SPD
#undef CONFIG_FSL_DDR_INTERACTIVE
diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h
index c9a1539..7406ac3 100644
--- a/include/configs/MPC8568MDS.h
+++ b/include/configs/MPC8568MDS.h
@@ -60,7 +60,7 @@
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
/* DDR Setup */
-#define CONFIG_FSL_DDR2
+#define CONFIG_SYS_FSL_DDR2
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_SPD
diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h
index 341f6a8..df5572b 100644
--- a/include/configs/MPC8569MDS.h
+++ b/include/configs/MPC8569MDS.h
@@ -98,7 +98,7 @@
#endif
/* DDR Setup */
-#define CONFIG_FSL_DDR3
+#define CONFIG_SYS_FSL_DDR3
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_SPD
diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h
index c751144..63480ec 100644
--- a/include/configs/MPC8572DS.h
+++ b/include/configs/MPC8572DS.h
@@ -106,7 +106,7 @@
/* DDR Setup */
#define CONFIG_VERY_BIG_RAM
-#define CONFIG_FSL_DDR2
+#define CONFIG_SYS_FSL_DDR2
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#define CONFIG_DDR_SPD
@@ -322,6 +322,8 @@
#define CONFIG_CMD_NAND 1
#define CONFIG_NAND_FSL_ELBC 1
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
+#define CONFIG_SYS_NAND_MAX_OOBFREE 5
+#define CONFIG_SYS_NAND_MAX_ECCPOS 56
/* NAND boot: 4K NAND loader config */
#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
index 97f5c87..41ebe31 100644
--- a/include/configs/MPC8610HPCD.h
+++ b/include/configs/MPC8610HPCD.h
@@ -92,7 +92,7 @@
#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW
/* DDR Setup */
-#define CONFIG_FSL_DDR2
+#define CONFIG_SYS_FSL_DDR2
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM /* Use SPD for DDR */
#define CONFIG_DDR_SPD
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index 8ed5050..0e666ba 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -108,7 +108,7 @@
/*
* DDR Setup
*/
-#define CONFIG_FSL_DDR2
+#define CONFIG_SYS_FSL_DDR2
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#define CONFIG_DDR_SPD
diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h
index c1cfbd4..eab386a 100644
--- a/include/configs/P1010RDB.h
+++ b/include/configs/P1010RDB.h
@@ -178,7 +178,7 @@
#define CONFIG_PANIC_HANG /* do not reset board on panic */
/* DDR Setup */
-#define CONFIG_FSL_DDR3
+#define CONFIG_SYS_FSL_DDR3
#define CONFIG_SYS_DDR_RAW_TIMING
#define CONFIG_DDR_SPD
#define CONFIG_SYS_SPD_BUS_NUM 1
@@ -313,6 +313,13 @@
#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
#endif
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITION
+#define CONFIG_CMD_MTDPARTS
+#define MTDIDS_DEFAULT "nand0=ff800000.flash"
+#define MTDPARTS_DEFAULT \
+ "mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
+
#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
| CSPR_PORT_SIZE_8 \
| CSPR_MSEL_NAND \
diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h
index 1470526..262c3e5 100644
--- a/include/configs/P1022DS.h
+++ b/include/configs/P1022DS.h
@@ -177,7 +177,7 @@
/* DDR Setup */
#define CONFIG_DDR_SPD
#define CONFIG_VERY_BIG_RAM
-#define CONFIG_FSL_DDR3
+#define CONFIG_SYS_FSL_DDR3
#ifdef CONFIG_DDR_ECC
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
diff --git a/include/configs/P1023RDB.h b/include/configs/P1023RDB.h
index e49523e..7de6814 100644
--- a/include/configs/P1023RDB.h
+++ b/include/configs/P1023RDB.h
@@ -74,7 +74,7 @@
#define CONFIG_CHIP_SELECTS_PER_CTRL 1
#define CONFIG_DDR_SPD
-#define CONFIG_FSL_DDR3
+#define CONFIG_SYS_FSL_DDR3
#define CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SYS_SDRAM_SIZE 512u /* DDR is 512M */
#define CONFIG_SYS_SPD_BUS_NUM 0
diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h
index 282f5c1..b592c19 100644
--- a/include/configs/P1_P2_RDB.h
+++ b/include/configs/P1_P2_RDB.h
@@ -141,7 +141,7 @@
#endif
/* DDR Setup */
-#define CONFIG_FSL_DDR2
+#define CONFIG_SYS_FSL_DDR2
#undef CONFIG_FSL_DDR_INTERACTIVE
#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
diff --git a/include/configs/P2020COME.h b/include/configs/P2020COME.h
index 9cc219e..15d2a43 100644
--- a/include/configs/P2020COME.h
+++ b/include/configs/P2020COME.h
@@ -105,7 +105,7 @@
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
/* DDR Setup */
-#define CONFIG_FSL_DDR3
+#define CONFIG_SYS_FSL_DDR3
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#define CONFIG_DDR_SPD
diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h
index 8a29eaa..9d3d9b3 100644
--- a/include/configs/P2020DS.h
+++ b/include/configs/P2020DS.h
@@ -109,9 +109,9 @@
/* DDR Setup */
#define CONFIG_VERY_BIG_RAM
#ifdef CONFIG_DDR2
-#define CONFIG_FSL_DDR2
+#define CONFIG_SYS_FSL_DDR2
#else
-#define CONFIG_FSL_DDR3 1
+#define CONFIG_SYS_FSL_DDR3 1
#endif
/* ECC will be enabled based on perf_mode environment variable */
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index 0df6f1a..b238574 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -175,7 +175,7 @@
#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
#define CONFIG_DDR_SPD
-#define CONFIG_FSL_DDR3
+#define CONFIG_SYS_FSL_DDR3
#define CONFIG_SYS_SPD_BUS_NUM 0
#define SPD_EEPROM_ADDRESS 0x52
diff --git a/include/configs/P4080DS.h b/include/configs/P4080DS.h
index b0cd7d5..2f89008 100644
--- a/include/configs/P4080DS.h
+++ b/include/configs/P4080DS.h
@@ -17,6 +17,12 @@
#define CONFIG_MMC
#define CONFIG_PCIE3
+#define CONFIG_CMD_SATA
+#define CONFIG_SATA_SIL
+#define CONFIG_SYS_SATA_MAX_DEVICE 2
+#define CONFIG_LIBATA
+#define CONFIG_LBA48
+
#define CONFIG_SYS_SRIO
#define CONFIG_SRIO1 /* SRIO port 1 */
#define CONFIG_SRIO2 /* SRIO port 2 */
diff --git a/include/configs/PN62.h b/include/configs/PN62.h
deleted file mode 100644
index 2a82f94..0000000
--- a/include/configs/PN62.h
+++ /dev/null
@@ -1,285 +0,0 @@
-/*
- * (C) Copyright 2002
- * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC824X 1
-#define CONFIG_MPC8240 1
-#define CONFIG_PN62 1
-
-#define CONFIG_SYS_TEXT_BASE 0xFFF00000
-
-#define CONFIG_CONS_INDEX 1
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_BSP
-
-#undef CONFIG_CMD_FLASH
-#undef CONFIG_CMD_IMLS
-#undef CONFIG_CMD_LOADS
-#undef CONFIG_CMD_SAVEENV
-#undef CONFIG_CMD_SOURCE
-
-
-#define CONFIG_BAUDRATE 19200 /* console baudrate */
-
-#define CONFIG_BOOTDELAY 1 /* autoboot after n seconds */
-
-#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
-
-#define CONFIG_SERVERIP 10.0.0.201
-#define CONFIG_IPADDR 10.0.0.200
-#define CONFIG_ROOTPATH "/opt/eldk/ppc_82xx"
-#define CONFIG_NETMASK 255.255.255.0
-#undef CONFIG_BOOTARGS
-#if 0
-/* Boot Linux with NFS root filesystem */
-#define CONFIG_BOOTCOMMAND \
- "setenv verify y;" \
- "setenv bootargs console=ttyS0,19200 mem=31M quiet " \
- "root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
- "ip=${ipaddr}:${serverip}::${netmask}:pn62:eth0:off;" \
- "loadp 100000; bootm"
- /* "tftpboot 100000 uImage; bootm" */
-#else
-/* Boot Linux with RAMdisk based filesystem (initrd, BusyBox) */
-#define CONFIG_BOOTCOMMAND \
- "setenv verify n;" \
- "setenv bootargs console=ttyS0,19200 mem=31M quiet " \
- "root=/dev/ram rw " \
- "ip=${ipaddr}:${serverip}::${netmask}:pn62:eth0:off;" \
- "loadp 200000; bootm"
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP 1 /* undef to save memory */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
-
-#define CONFIG_PRAM 1024 /* reserve 1 MB protected RAM */
-
-#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() on init */
-
-#define CONFIG_HAS_ETH1 1 /* add support for eth1addr */
-
-#define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */
-
-/*
- * PCI stuff
- */
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_PCI_PNP /* we need Plug 'n Play */
-#if 0
-#define CONFIG_PCI_SCAN_SHOW /* show PCI auto-scan at boot */
-#endif
-
-/*
- * Networking stuff
- */
-
-#define CONFIG_PCNET /* there are 2 AMD PCnet 79C973 */
-#define CONFIG_PCNET_79C973
-
-#define _IO_BASE 0xfe000000 /* points to PCI I/O space */
-
-
-/*
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_MAX_RAM_SIZE 0x10000000
-
-#define CONFIG_SYS_RESET_ADDRESS 0xfff00100
-
-#undef CONFIG_SYS_RAMBOOT
-#define CONFIG_SYS_MONITOR_LEN 0x00030000
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-
-
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-
-#define CONFIG_SYS_NO_FLASH 1 /* There is no FLASH memory */
-
-#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
-#define CONFIG_ENV_OFFSET 0x00004000 /* Offset of Environment Sector */
-#define CONFIG_ENV_SIZE 0x00002000 /* Total Size of Environment Sector */
-
-#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */
-
-#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x01f00000 /* 0 ... 32 MB in DRAM */
-
-/*
- * Serial port configuration
- */
-
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-
-#define CONFIG_SYS_NS16550_CLK 1843200
-
-#define CONFIG_SYS_NS16550_COM1 0xff800008
-#define CONFIG_SYS_NS16550_COM2 0xff800000
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
-#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 3
-
-#define CONFIG_SYS_EUMB_ADDR 0xFCE00000
-
-/* MCCR1 */
-#define CONFIG_SYS_ROMNAL 3 /* rom/flash next access time */
-#define CONFIG_SYS_ROMFAL 7 /* rom/flash access time */
-
-/* MCCR2 */
-#define CONFIG_SYS_ASRISE 6 /* ASRISE in clocks */
-#define CONFIG_SYS_ASFALL 12 /* ASFALL in clocks */
-#define CONFIG_SYS_REFINT 5600 /* REFINT in clocks */
-
-/* MCCR3 */
-#define CONFIG_SYS_BSTOPRE 0x3cf /* Burst To Precharge */
-#define CONFIG_SYS_REFREC 2 /* Refresh to activate interval */
-#define CONFIG_SYS_RDLAT 3 /* data latency from read command */
-
-/* MCCR4 */
-#define CONFIG_SYS_PRETOACT 1 /* Precharge to activate interval */
-#define CONFIG_SYS_ACTTOPRE 3 /* Activate to Precharge interval */
-#define CONFIG_SYS_ACTORW 2 /* Activate to R/W */
-#define CONFIG_SYS_SDMODE_CAS_LAT 2 /* SDMODE CAS latency */
-#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE Wrap type */
-#define CONFIG_SYS_SDMODE_BURSTLEN 2 /* SDMODE Burst length 2=4, 3=8 */
-#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
-
-/* Memory bank settings:
- *
- * only bits 20-29 are actually used from these vales to set the
- * start/qend address the upper two bits will be 0, and the lower 20
- * bits will be set to 0x00000 for a start address, or 0xfffff for an
- * end address
- */
-#define CONFIG_SYS_BANK0_START 0x00000000
-#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1)
-#define CONFIG_SYS_BANK0_ENABLE 1
-#define CONFIG_SYS_BANK1_START 0x00000000
-#define CONFIG_SYS_BANK1_END 0x00000000
-#define CONFIG_SYS_BANK1_ENABLE 0
-#define CONFIG_SYS_BANK2_START 0x00000000
-#define CONFIG_SYS_BANK2_END 0x00000000
-#define CONFIG_SYS_BANK2_ENABLE 0
-#define CONFIG_SYS_BANK3_START 0x00000000
-#define CONFIG_SYS_BANK3_END 0x00000000
-#define CONFIG_SYS_BANK3_ENABLE 0
-#define CONFIG_SYS_BANK4_START 0x00000000
-#define CONFIG_SYS_BANK4_END 0x00000000
-#define CONFIG_SYS_BANK4_ENABLE 0
-#define CONFIG_SYS_BANK5_START 0x00000000
-#define CONFIG_SYS_BANK5_END 0x00000000
-#define CONFIG_SYS_BANK5_ENABLE 0
-#define CONFIG_SYS_BANK6_START 0x00000000
-#define CONFIG_SYS_BANK6_END 0x00000000
-#define CONFIG_SYS_BANK6_ENABLE 0
-#define CONFIG_SYS_BANK7_START 0x00000000
-#define CONFIG_SYS_BANK7_END 0x00000000
-#define CONFIG_SYS_BANK7_ENABLE 0
-
-/*
- * Memory bank enable bitmask, specifying which of the banks defined above
- * are actually present. MSB is for bank #7, LSB is for bank #0.
- */
-#define CONFIG_SYS_BANK_ENABLE 0x01
-
-#define CONFIG_SYS_ODCR 0xff /* configures line driver impedances, */
- /* see 8240 book for bit definitions */
-#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 retains the */
- /* currently accessed page in memory */
- /* see 8240 book for details */
-
-/* SDRAM 0 - 256MB */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-
-/* PCI memory space */
-#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-/* Config addrs, etc */
-#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8240 CPU */
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h
index 2738242..43a5778 100644
--- a/include/configs/T1040QDS.h
+++ b/include/configs/T1040QDS.h
@@ -32,6 +32,8 @@
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/t1040qds/t1040_pbi.cfg
+#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/t1040qds/t1040_rcw.cfg
#endif
/* High Level Configuration Options */
@@ -168,7 +170,7 @@
#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
#define CONFIG_DDR_SPD
-#define CONFIG_FSL_DDR3
+#define CONFIG_SYS_FSL_DDR3
#define CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SYS_SPD_BUS_NUM 0
diff --git a/include/configs/T1040RDB.h b/include/configs/T1040RDB.h
new file mode 100644
index 0000000..7931231
--- /dev/null
+++ b/include/configs/T1040RDB.h
@@ -0,0 +1,690 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * T1040 RDB board configuration file
+ */
+#define CONFIG_T104xRDB
+#define CONFIG_T1040RDB
+#define CONFIG_PHYS_64BIT
+
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
+#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#endif
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE
+#define CONFIG_E500 /* BOOKE e500 family */
+#define CONFIG_E500MC /* BOOKE e500mc family */
+#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
+#define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */
+#define CONFIG_MP /* support multiple processors */
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xeff80000
+#endif
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
+#endif
+
+#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
+#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
+#define CONFIG_FSL_IFC /* Enable IFC Support */
+#define CONFIG_PCI /* Enable PCI/PCIE */
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_PCIE1 /* PCIE controler 1 */
+#define CONFIG_PCIE2 /* PCIE controler 2 */
+#define CONFIG_PCIE3 /* PCIE controler 3 */
+#define CONFIG_PCIE4 /* PCIE controler 4 */
+
+#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
+
+#define CONFIG_FSL_LAW /* Use common FSL init code */
+
+#define CONFIG_ENV_OVERWRITE
+
+#ifdef CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_IS_NOWHERE
+#else
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#endif
+
+#ifndef CONFIG_SYS_NO_FLASH
+#if defined(CONFIG_SPIFLASH)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_BUS 0
+#define CONFIG_ENV_SPI_CS 0
+#define CONFIG_ENV_SPI_MAX_HZ 10000000
+#define CONFIG_ENV_SPI_MODE 0
+#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
+#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
+#define CONFIG_ENV_SECT_SIZE 0x10000
+#elif defined(CONFIG_SDCARD)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_OFFSET (512 * 1105)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
+#endif
+#else /* CONFIG_SYS_NO_FLASH */
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
+#endif
+
+#define CONFIG_SYS_CLK_FREQ 100000000
+#define CONFIG_DDR_CLK_FREQ 66666666
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_SYS_CACHE_STASHING
+#define CONFIG_BACKSIDE_L2_CACHE
+#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
+#define CONFIG_BTB /* toggle branch predition */
+#define CONFIG_DDR_ECC
+#ifdef CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
+#endif
+
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#define CONFIG_ADDR_MAP
+#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
+
+#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x00400000
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_PANIC_HANG /* do not reset board on panic */
+
+/*
+ * Config the L3 Cache as L3 SRAM
+ */
+#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
+
+#define CONFIG_SYS_DCSRBAR 0xf0000000
+#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+
+/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+#define CONFIG_DDR_SPD
+#define CONFIG_SYS_DDR_RAW_TIMING
+#define CONFIG_SYS_FSL_DDR3
+
+#define CONFIG_SYS_SPD_BUS_NUM 0
+#define SPD_EEPROM_ADDRESS 0x51
+
+#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
+
+/*
+ * IFC Definitions
+ */
+#define CONFIG_SYS_FLASH_BASE 0xe8000000
+#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
+
+#define CONFIG_SYS_NOR_CSPR_EXT (0xf)
+#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
+ CSPR_PORT_SIZE_16 | \
+ CSPR_MSEL_NOR | \
+ CSPR_V)
+#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
+/* NOR Flash Timing Params */
+#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
+#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
+ FTIM0_NOR_TEADC(0x5) | \
+ FTIM0_NOR_TEAHC(0x5))
+#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
+ FTIM1_NOR_TRAD_NOR(0x1A) |\
+ FTIM1_NOR_TSEQRAD_NOR(0x13))
+#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
+ FTIM2_NOR_TCH(0x4) | \
+ FTIM2_NOR_TWPH(0x0E) | \
+ FTIM2_NOR_TWP(0x1c))
+#define CONFIG_SYS_NOR_FTIM3 0x0
+
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
+
+/* CPLD on IFC */
+#define CONFIG_SYS_CPLD_BASE 0xffdf0000
+#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
+#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
+ | CSPR_PORT_SIZE_8 \
+ | CSPR_MSEL_GPCM \
+ | CSPR_V)
+#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
+#define CONFIG_SYS_CSOR2 0x0
+/* CPLD Timing parameters for IFC CS2 */
+#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
+ FTIM0_GPCM_TEADC(0x0e) | \
+ FTIM0_GPCM_TEAHC(0x0e))
+#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
+ FTIM1_GPCM_TRAD(0x1f))
+#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
+ FTIM2_GPCM_TCH(0x0) | \
+ FTIM2_GPCM_TWP(0x1f))
+#define CONFIG_SYS_CS2_FTIM3 0x0
+
+/* NAND Flash on IFC */
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_BASE 0xff800000
+#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
+
+#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
+#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+ | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
+ | CSPR_MSEL_NAND /* MSEL = NAND */ \
+ | CSPR_V)
+#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
+
+#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
+ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
+ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
+ | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
+ | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
+ | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \
+ | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* ONFI NAND Flash mode0 Timing Params */
+#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
+ FTIM0_NAND_TWP(0x18) | \
+ FTIM0_NAND_TWCHT(0x07) | \
+ FTIM0_NAND_TWH(0x0a))
+#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
+ FTIM1_NAND_TWBE(0x39) | \
+ FTIM1_NAND_TRR(0x0e) | \
+ FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
+ FTIM2_NAND_TREH(0x0a) | \
+ FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3 0x0
+
+#define CONFIG_SYS_NAND_DDR_LAW 11
+#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+
+#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
+
+#if defined(CONFIG_NAND)
+#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT
+#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
+#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
+#else
+#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
+#endif
+
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+
+#if defined(CONFIG_RAMBOOT_PBL)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_BOARD_EARLY_INIT_R
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_HWCONFIG
+
+/* define to use L1 as initial stack */
+#define CONFIG_L1_INIT_RAM
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000
+/* The assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+ ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
+
+/* Serial Port - controlled on board with jumper J8
+ * open - index 2
+ * shorted - index 1
+ */
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
+
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
+#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
+#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
+#define CONFIG_SERIAL_MULTI /* Enable both serial ports */
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
+#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */
+#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
+#define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000
+
+/* I2C bus multiplexer */
+#define I2C_MUX_PCA_ADDR 0x70
+#define I2C_MUX_CH_DEFAULT 0x8
+
+
+/*
+ * eSPI - Enhanced SPI
+ */
+#define CONFIG_FSL_ESPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED 10000000
+#define CONFIG_SF_DEFAULT_MODE 0
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+#ifdef CONFIG_PCI
+/* controller 1, direct to uli, tgtid 3, Base address 20000 */
+#ifdef CONFIG_PCIE1
+#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
+#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
+#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
+#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
+#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
+#endif
+
+/* controller 2, Slot 2, tgtid 2, Base address 201000 */
+#ifdef CONFIG_PCIE2
+#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
+#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
+#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
+#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
+#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
+#endif
+
+/* controller 3, Slot 1, tgtid 1, Base address 202000 */
+#ifdef CONFIG_PCIE3
+#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
+#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
+#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
+#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
+#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
+#endif
+
+/* controller 4, Base address 203000 */
+#ifdef CONFIG_PCIE4
+#define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
+#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
+#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
+#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
+#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
+#endif
+
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_E1000
+
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CONFIG_DOS_PARTITION
+#endif /* CONFIG_PCI */
+
+/* SATA */
+#define CONFIG_FSL_SATA_V2
+#ifdef CONFIG_FSL_SATA_V2
+#define CONFIG_LIBATA
+#define CONFIG_FSL_SATA
+
+#define CONFIG_SYS_SATA_MAX_DEVICE 1
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
+#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
+
+#define CONFIG_LBA48
+#define CONFIG_CMD_SATA
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#endif
+
+/*
+* USB
+*/
+#define CONFIG_HAS_FSL_DR_USB
+
+#ifdef CONFIG_HAS_FSL_DR_USB
+#define CONFIG_USB_EHCI
+
+#ifdef CONFIG_USB_EHCI
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_CMD_EXT2
+#endif
+#endif
+
+#define CONFIG_MMC
+
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+/* Qman/Bman */
+#ifndef CONFIG_NOBQFMAN
+#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
+#define CONFIG_SYS_BMAN_NUM_PORTALS 25
+#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
+#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
+#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
+#define CONFIG_SYS_QMAN_NUM_PORTALS 25
+#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
+#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
+#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
+
+#define CONFIG_SYS_DPAA_FMAN
+#define CONFIG_SYS_DPAA_PME
+
+/* Default address of microcode for the Linux Fman driver */
+#if defined(CONFIG_SPIFLASH)
+/*
+ * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
+ * env, so we got 0x110000.
+ */
+#define CONFIG_SYS_QE_FW_IN_SPIFLASH
+#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000
+#elif defined(CONFIG_SDCARD)
+/*
+ * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
+ * about 545KB (1089 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
+ */
+#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
+#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
+#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#else
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
+#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000
+#endif
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
+#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+#endif /* CONFIG_NOBQFMAN */
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_FMAN_ENET
+#define CONFIG_PHY_VITESSE
+#define CONFIG_PHY_REALTEK
+#endif
+
+#ifdef CONFIG_FMAN_ENET
+#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
+#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
+#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
+#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
+
+#define CONFIG_MII /* MII PHY management */
+#define CONFIG_ETHPRIME "FM1@DTSEC1"
+#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
+#endif
+
+/*
+ * Environment
+ */
+#define CONFIG_LOADS_ECHO /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_ERRATA
+#define CONFIG_CMD_GREPENV
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SETEXPR
+
+#ifdef CONFIG_PCI
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_CMDLINE_EDITING /* Command-line editing */
+#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
+#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ROOTPATH "/opt/nfsroot"
+#define CONFIG_BOOTFILE "uImage"
+#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR 1000000
+
+#define CONFIG_BOOTDELAY 10 /*-1 disables auto-boot*/
+
+#define CONFIG_BAUDRATE 115200
+
+#define __USB_PHY_TYPE utmi
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
+ "bank_intlv=cs0_cs1;" \
+ "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
+ "netdev=eth0\0" \
+ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
+ "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
+ "tftpflash=tftpboot $loadaddr $uboot && " \
+ "protect off $ubootaddr +$filesize && " \
+ "erase $ubootaddr +$filesize && " \
+ "cp.b $loadaddr $ubootaddr $filesize && " \
+ "protect on $ubootaddr +$filesize && " \
+ "cmp.b $loadaddr $ubootaddr $filesize\0" \
+ "consoledev=ttyS0\0" \
+ "ramdiskaddr=2000000\0" \
+ "ramdiskfile=t1040rdb/ramdisk.uboot\0" \
+ "fdtaddr=c00000\0" \
+ "fdtfile=t1040rdb/t1040rdb.dtb\0" \
+ "bdev=sda3\0" \
+ "c=ffe\0"
+
+#define CONFIG_LINUX \
+ "setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "setenv ramdiskaddr 0x02000000;" \
+ "setenv fdtaddr 0x00c00000;" \
+ "setenv loadaddr 0x1000000;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_HDBOOT \
+ "setenv bootargs root=/dev/$bdev rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_NFSBOOTCOMMAND \
+ "setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$serverip:$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+ "setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $ramdiskaddr $ramdiskfile;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND CONFIG_LINUX
+
+#ifdef CONFIG_SECURE_BOOT
+#include <asm/fsl_secure_boot.h>
+#endif
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/T1042RDB_PI.h b/include/configs/T1042RDB_PI.h
new file mode 100644
index 0000000..eff08e3
--- /dev/null
+++ b/include/configs/T1042RDB_PI.h
@@ -0,0 +1,694 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * T1042RDB_PI board configuration file
+ */
+#define CONFIG_T104xRDB
+#define CONFIG_T1042RDB_PI
+#define CONFIG_PHYS_64BIT
+
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
+#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#endif
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE
+#define CONFIG_E500 /* BOOKE e500 family */
+#define CONFIG_E500MC /* BOOKE e500mc family */
+#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
+#define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */
+#define CONFIG_MP /* support multiple processors */
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xeff80000
+#endif
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
+#endif
+
+#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
+#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
+#define CONFIG_FSL_IFC /* Enable IFC Support */
+#define CONFIG_PCI /* Enable PCI/PCIE */
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_PCIE1 /* PCIE controler 1 */
+#define CONFIG_PCIE2 /* PCIE controler 2 */
+#define CONFIG_PCIE3 /* PCIE controler 3 */
+#define CONFIG_PCIE4 /* PCIE controler 4 */
+
+#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
+
+#define CONFIG_FSL_LAW /* Use common FSL init code */
+
+#define CONFIG_ENV_OVERWRITE
+
+#ifdef CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_IS_NOWHERE
+#else
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#endif
+
+#ifndef CONFIG_SYS_NO_FLASH
+#if defined(CONFIG_SPIFLASH)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_BUS 0
+#define CONFIG_ENV_SPI_CS 0
+#define CONFIG_ENV_SPI_MAX_HZ 10000000
+#define CONFIG_ENV_SPI_MODE 0
+#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
+#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
+#define CONFIG_ENV_SECT_SIZE 0x10000
+#elif defined(CONFIG_SDCARD)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_OFFSET (512 * 1105)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
+#endif
+#else /* CONFIG_SYS_NO_FLASH */
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
+#endif
+
+#define CONFIG_SYS_CLK_FREQ 100000000
+#define CONFIG_DDR_CLK_FREQ 66666666
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_SYS_CACHE_STASHING
+#define CONFIG_BACKSIDE_L2_CACHE
+#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
+#define CONFIG_BTB /* toggle branch predition */
+#define CONFIG_DDR_ECC
+#ifdef CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
+#endif
+
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#define CONFIG_ADDR_MAP
+#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
+
+#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x00400000
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_PANIC_HANG /* do not reset board on panic */
+
+/*
+ * Config the L3 Cache as L3 SRAM
+ */
+#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
+
+#define CONFIG_SYS_DCSRBAR 0xf0000000
+#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+
+/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+#define CONFIG_DDR_SPD
+#define CONFIG_SYS_DDR_RAW_TIMING
+#define CONFIG_SYS_FSL_DDR3
+
+#define CONFIG_SYS_SPD_BUS_NUM 0
+#define SPD_EEPROM_ADDRESS 0x51
+
+#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
+
+/*
+ * IFC Definitions
+ */
+#define CONFIG_SYS_FLASH_BASE 0xe8000000
+#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
+
+#define CONFIG_SYS_NOR_CSPR_EXT (0xf)
+#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
+ CSPR_PORT_SIZE_16 | \
+ CSPR_MSEL_NOR | \
+ CSPR_V)
+#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
+/* NOR Flash Timing Params */
+#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
+#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
+ FTIM0_NOR_TEADC(0x5) | \
+ FTIM0_NOR_TEAHC(0x5))
+#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
+ FTIM1_NOR_TRAD_NOR(0x1A) |\
+ FTIM1_NOR_TSEQRAD_NOR(0x13))
+#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
+ FTIM2_NOR_TCH(0x4) | \
+ FTIM2_NOR_TWPH(0x0E) | \
+ FTIM2_NOR_TWP(0x1c))
+#define CONFIG_SYS_NOR_FTIM3 0x0
+
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
+
+/* CPLD on IFC */
+#define CONFIG_SYS_CPLD_BASE 0xffdf0000
+#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
+#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
+ | CSPR_PORT_SIZE_8 \
+ | CSPR_MSEL_GPCM \
+ | CSPR_V)
+#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
+#define CONFIG_SYS_CSOR2 0x0
+/* CPLD Timing parameters for IFC CS2 */
+#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
+ FTIM0_GPCM_TEADC(0x0e) | \
+ FTIM0_GPCM_TEAHC(0x0e))
+#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
+ FTIM1_GPCM_TRAD(0x1f))
+#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
+ FTIM2_GPCM_TCH(0x0) | \
+ FTIM2_GPCM_TWP(0x1f))
+#define CONFIG_SYS_CS2_FTIM3 0x0
+
+/* NAND Flash on IFC */
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_BASE 0xff800000
+#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
+
+#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
+#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+ | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
+ | CSPR_MSEL_NAND /* MSEL = NAND */ \
+ | CSPR_V)
+#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
+
+#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
+ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
+ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
+ | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
+ | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
+ | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \
+ | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* ONFI NAND Flash mode0 Timing Params */
+#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
+ FTIM0_NAND_TWP(0x18) | \
+ FTIM0_NAND_TWCHT(0x07) | \
+ FTIM0_NAND_TWH(0x0a))
+#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
+ FTIM1_NAND_TWBE(0x39) | \
+ FTIM1_NAND_TRR(0x0e) | \
+ FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
+ FTIM2_NAND_TREH(0x0a) | \
+ FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3 0x0
+
+#define CONFIG_SYS_NAND_DDR_LAW 11
+#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+
+#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
+
+#if defined(CONFIG_NAND)
+#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT
+#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
+#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
+#else
+#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
+#endif
+
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+
+#if defined(CONFIG_RAMBOOT_PBL)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_BOARD_EARLY_INIT_R
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_HWCONFIG
+
+/* define to use L1 as initial stack */
+#define CONFIG_L1_INIT_RAM
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000
+/* The assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+ ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
+
+/* Serial Port - controlled on board with jumper J8
+ * open - index 2
+ * shorted - index 1
+ */
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
+
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
+#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
+#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
+#define CONFIG_SERIAL_MULTI /* Enable both serial ports */
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
+#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */
+#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
+#define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000
+
+/* I2C bus multiplexer */
+#define I2C_MUX_PCA_ADDR 0x70
+
+/*
+ * RTC configuration
+ */
+#define RTC
+#define CONFIG_RTC_DS1337 1
+#define CONFIG_SYS_I2C_RTC_ADDR 0x68
+
+/*DVI encoder*/
+#define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75
+
+/*
+ * eSPI - Enhanced SPI
+ */
+#define CONFIG_FSL_ESPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED 10000000
+#define CONFIG_SF_DEFAULT_MODE 0
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+#ifdef CONFIG_PCI
+/* controller 1, direct to uli, tgtid 3, Base address 20000 */
+#ifdef CONFIG_PCIE1
+#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
+#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
+#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
+#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
+#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
+#endif
+
+/* controller 2, Slot 2, tgtid 2, Base address 201000 */
+#ifdef CONFIG_PCIE2
+#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
+#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
+#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
+#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
+#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
+#endif
+
+/* controller 3, Slot 1, tgtid 1, Base address 202000 */
+#ifdef CONFIG_PCIE3
+#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
+#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
+#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
+#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
+#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
+#endif
+
+/* controller 4, Base address 203000 */
+#ifdef CONFIG_PCIE4
+#define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
+#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
+#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
+#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
+#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
+#endif
+
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_E1000
+
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CONFIG_DOS_PARTITION
+#endif /* CONFIG_PCI */
+
+/* SATA */
+#define CONFIG_FSL_SATA_V2
+#ifdef CONFIG_FSL_SATA_V2
+#define CONFIG_LIBATA
+#define CONFIG_FSL_SATA
+
+#define CONFIG_SYS_SATA_MAX_DEVICE 1
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
+#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
+
+#define CONFIG_LBA48
+#define CONFIG_CMD_SATA
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#endif
+
+/*
+* USB
+*/
+#define CONFIG_HAS_FSL_DR_USB
+
+#ifdef CONFIG_HAS_FSL_DR_USB
+#define CONFIG_USB_EHCI
+
+#ifdef CONFIG_USB_EHCI
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_CMD_EXT2
+#endif
+#endif
+
+#define CONFIG_MMC
+
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+/* Qman/Bman */
+#ifndef CONFIG_NOBQFMAN
+#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
+#define CONFIG_SYS_BMAN_NUM_PORTALS 25
+#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
+#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
+#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
+#define CONFIG_SYS_QMAN_NUM_PORTALS 25
+#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
+#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
+#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
+
+#define CONFIG_SYS_DPAA_FMAN
+#define CONFIG_SYS_DPAA_PME
+
+/* Default address of microcode for the Linux Fman driver */
+#if defined(CONFIG_SPIFLASH)
+/*
+ * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
+ * env, so we got 0x110000.
+ */
+#define CONFIG_SYS_QE_FW_IN_SPIFLASH
+#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000
+#elif defined(CONFIG_SDCARD)
+/*
+ * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
+ * about 545KB (1089 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
+ */
+#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
+#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
+#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#else
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
+#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000
+#endif
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
+#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+#endif /* CONFIG_NOBQFMAN */
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_FMAN_ENET
+#define CONFIG_PHY_VITESSE
+#define CONFIG_PHY_REALTEK
+#endif
+
+#ifdef CONFIG_FMAN_ENET
+#define CONFIG_MII /* MII PHY management */
+#define CONFIG_ETHPRIME "FM1@DTSEC1"
+#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
+#endif
+
+/*
+ * Environment
+ */
+#define CONFIG_LOADS_ECHO /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_ERRATA
+#define CONFIG_CMD_GREPENV
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SETEXPR
+
+#ifdef CONFIG_PCI
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_CMDLINE_EDITING /* Command-line editing */
+#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
+#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ROOTPATH "/opt/nfsroot"
+#define CONFIG_BOOTFILE "uImage"
+#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR 1000000
+
+#define CONFIG_BOOTDELAY 10 /*-1 disables auto-boot*/
+
+#define CONFIG_BAUDRATE 115200
+
+#define __USB_PHY_TYPE utmi
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
+ "bank_intlv=cs0_cs1;" \
+ "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
+ "netdev=eth0\0" \
+ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
+ "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
+ "tftpflash=tftpboot $loadaddr $uboot && " \
+ "protect off $ubootaddr +$filesize && " \
+ "erase $ubootaddr +$filesize && " \
+ "cp.b $loadaddr $ubootaddr $filesize && " \
+ "protect on $ubootaddr +$filesize && " \
+ "cmp.b $loadaddr $ubootaddr $filesize\0" \
+ "consoledev=ttyS0\0" \
+ "ramdiskaddr=2000000\0" \
+ "ramdiskfile=t1040rdb_pi/ramdisk.uboot\0" \
+ "fdtaddr=c00000\0" \
+ "fdtfile=t1040rdb_pi/t1040rdb_pi.dtb\0" \
+ "bdev=sda3\0" \
+ "c=ffe\0"
+
+#define CONFIG_LINUX \
+ "setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "setenv ramdiskaddr 0x02000000;" \
+ "setenv fdtaddr 0x00c00000;" \
+ "setenv loadaddr 0x1000000;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_HDBOOT \
+ "setenv bootargs root=/dev/$bdev rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_NFSBOOTCOMMAND \
+ "setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$serverip:$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+ "setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $ramdiskaddr $ramdiskfile;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND CONFIG_LINUX
+
+#ifdef CONFIG_SECURE_BOOT
+#include <asm/fsl_secure_boot.h>
+#endif
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/T2080QDS.h b/include/configs/T2080QDS.h
new file mode 100644
index 0000000..ad09816
--- /dev/null
+++ b/include/configs/T2080QDS.h
@@ -0,0 +1,805 @@
+/*
+ * Copyright 2011-2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * T2080 QDS board configuration file
+ */
+
+#ifndef __T2080QDS_H
+#define __T2080QDS_H
+
+#define CONFIG_T2080QDS
+#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
+#define CONFIG_MMC
+#define CONFIG_SPI_FLASH
+#define CONFIG_USB_EHCI
+#define CONFIG_FSL_SATA_V2
+#define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */
+#define CONFIG_SRIO1 /* SRIO port 1 */
+#define CONFIG_SRIO2 /* SRIO port 2 */
+
+/* High Level Configuration Options */
+#define CONFIG_PHYS_64BIT
+#define CONFIG_BOOKE
+#define CONFIG_E500 /* BOOKE e500 family */
+#define CONFIG_E500MC /* BOOKE e500mc family */
+#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
+#define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */
+#define CONFIG_MP /* support multiple processors */
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_ADDR_MAP 1
+#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
+#endif
+
+#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
+#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
+#define CONFIG_FSL_IFC /* Enable IFC Support */
+#define CONFIG_FSL_LAW /* Use common FSL init code */
+#define CONFIG_ENV_OVERWRITE
+
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
+#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/t2080qds/t2080_pbi.cfg
+#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/t2080qds/t2080_rcw.cfg
+#endif
+
+#define CONFIG_SRIO_PCIE_BOOT_MASTER
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+/* Set 1M boot space */
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
+ (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
+#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#define CONFIG_SYS_NO_FLASH
+#endif
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xeff80000
+#endif
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
+#endif
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_SYS_CACHE_STASHING
+#define CONFIG_BTB /* toggle branch predition */
+#define CONFIG_DDR_ECC
+#ifdef CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
+#endif
+
+#ifdef CONFIG_SYS_NO_FLASH
+#if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+#else
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#endif
+
+#if defined(CONFIG_SPIFLASH)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_BUS 0
+#define CONFIG_ENV_SPI_CS 0
+#define CONFIG_ENV_SPI_MAX_HZ 10000000
+#define CONFIG_ENV_SPI_MODE 0
+#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
+#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
+#define CONFIG_ENV_SECT_SIZE 0x10000
+#elif defined(CONFIG_SDCARD)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_OFFSET (512 * 1105)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+#define CONFIG_ENV_IS_IN_REMOTE
+#define CONFIG_ENV_ADDR 0xffe20000
+#define CONFIG_ENV_SIZE 0x2000
+#elif defined(CONFIG_ENV_IS_NOWHERE)
+#define CONFIG_ENV_SIZE 0x2000
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
+#endif
+
+#ifndef __ASSEMBLY__
+unsigned long get_board_sys_clk(void);
+unsigned long get_board_ddr_clk(void);
+#endif
+
+#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
+#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
+
+/*
+ * Config the L3 Cache as L3 SRAM
+ */
+#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
+
+#define CONFIG_SYS_DCSRBAR 0xf0000000
+#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM 0
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
+#define CONFIG_DDR_SPD
+#define CONFIG_SYS_FSL_DDR3
+#define CONFIG_FSL_DDR_INTERACTIVE
+#define CONFIG_SYS_SPD_BUS_NUM 0
+#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
+#define SPD_EEPROM_ADDRESS1 0x51
+#define SPD_EEPROM_ADDRESS2 0x52
+#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
+#define CTRL_INTLV_PREFERED cacheline
+
+/*
+ * IFC Definitions
+ */
+#define CONFIG_SYS_FLASH_BASE 0xe0000000
+#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
+#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
+ + 0x8000000) | \
+ CSPR_PORT_SIZE_16 | \
+ CSPR_MSEL_NOR | \
+ CSPR_V)
+#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
+#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+ CSPR_PORT_SIZE_16 | \
+ CSPR_MSEL_NOR | \
+ CSPR_V)
+#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
+/* NOR Flash Timing Params */
+#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
+
+#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
+ FTIM0_NOR_TEADC(0x5) | \
+ FTIM0_NOR_TEAHC(0x5))
+#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
+ FTIM1_NOR_TRAD_NOR(0x1A) |\
+ FTIM1_NOR_TSEQRAD_NOR(0x13))
+#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
+ FTIM2_NOR_TCH(0x4) | \
+ FTIM2_NOR_TWPH(0x0E) | \
+ FTIM2_NOR_TWP(0x1c))
+#define CONFIG_SYS_NOR_FTIM3 0x0
+
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
+ + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
+
+#define CONFIG_FSL_QIXIS /* use common QIXIS code */
+#define QIXIS_BASE 0xffdf0000
+#define QIXIS_LBMAP_SWITCH 6
+#define QIXIS_LBMAP_MASK 0x0f
+#define QIXIS_LBMAP_SHIFT 0
+#define QIXIS_LBMAP_DFLTBANK 0x00
+#define QIXIS_LBMAP_ALTBANK 0x04
+#define QIXIS_RST_CTL_RESET 0x83
+#define QIXIS_RST_FORCE_MEM 0x1
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
+#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
+#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
+
+#define CONFIG_SYS_CSPR3_EXT (0xf)
+#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
+ | CSPR_PORT_SIZE_8 \
+ | CSPR_MSEL_GPCM \
+ | CSPR_V)
+#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024)
+#define CONFIG_SYS_CSOR3 0x0
+/* QIXIS Timing parameters for IFC CS3 */
+#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
+ FTIM0_GPCM_TEADC(0x0e) | \
+ FTIM0_GPCM_TEAHC(0x0e))
+#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
+ FTIM1_GPCM_TRAD(0x3f))
+#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
+ FTIM2_GPCM_TCH(0x0) | \
+ FTIM2_GPCM_TWP(0x1f))
+#define CONFIG_SYS_CS3_FTIM3 0x0
+
+/* NAND Flash on IFC */
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_BASE 0xff800000
+#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
+
+#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
+#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+ | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
+ | CSPR_MSEL_NAND /* MSEL = NAND */ \
+ | CSPR_V)
+#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
+
+#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
+ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
+ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
+ | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
+ | CSOR_NAND_PGS_2K /* Page Size = 2K */\
+ | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\
+ | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* ONFI NAND Flash mode0 Timing Params */
+#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
+ FTIM0_NAND_TWP(0x18) | \
+ FTIM0_NAND_TWCHT(0x07) | \
+ FTIM0_NAND_TWH(0x0a))
+#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
+ FTIM1_NAND_TWBE(0x39) | \
+ FTIM1_NAND_TRR(0x0e) | \
+ FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
+ FTIM2_NAND_TREH(0x0a) | \
+ FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3 0x0
+
+#define CONFIG_SYS_NAND_DDR_LAW 11
+#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
+
+#if defined(CONFIG_NAND)
+#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
+#else
+#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
+#endif
+#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
+#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
+
+#if defined(CONFIG_RAMBOOT_PBL)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
+#define CONFIG_MISC_INIT_R
+#define CONFIG_HWCONFIG
+
+/* define to use L1 as initial stack */
+#define CONFIG_L1_INIT_RAM
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000
+/* The assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+ ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
+#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
+#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
+
+/*
+ * I2C
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
+#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
+#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
+#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
+#define CONFIG_SYS_FSL_I2C_SPEED 100000
+#define CONFIG_SYS_FSL_I2C2_SPEED 100000
+#define CONFIG_SYS_FSL_I2C3_SPEED 100000
+#define CONFIG_SYS_FSL_I2C4_SPEED 100000
+#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
+#define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */
+#define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */
+#define I2C_MUX_CH_DEFAULT 0x8
+
+
+/*
+ * RapidIO
+ */
+#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
+#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
+#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
+#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
+#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
+/*
+ * for slave u-boot IMAGE instored in master memory space,
+ * PHYS must be aligned based on the SIZE
+ */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
+/*
+ * for slave UCODE and ENV instored in master memory space,
+ * PHYS must be aligned based on the SIZE
+ */
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
+
+/* slave core release by master*/
+#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
+#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
+
+/*
+ * SRIO_PCIE_BOOT - SLAVE
+ */
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
+#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
+ (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
+#endif
+
+/*
+ * eSPI - Enhanced SPI
+ */
+#ifdef CONFIG_SPI_FLASH
+#define CONFIG_FSL_ESPI
+#define CONFIG_SPI_FLASH_SST
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED 10000000
+#define CONFIG_SF_DEFAULT_MODE 0
+#endif
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+#define CONFIG_PCI /* Enable PCI/PCIE */
+#define CONFIG_PCIE1 /* PCIE controler 1 */
+#define CONFIG_PCIE2 /* PCIE controler 2 */
+#define CONFIG_PCIE3 /* PCIE controler 3 */
+#define CONFIG_PCIE4 /* PCIE controler 4 */
+#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
+/* controller 1, direct to uli, tgtid 3, Base address 20000 */
+#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
+#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
+#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
+#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
+#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
+
+/* controller 2, Slot 2, tgtid 2, Base address 201000 */
+#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
+#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
+#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
+#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
+
+/* controller 3, Slot 1, tgtid 1, Base address 202000 */
+#define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
+#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
+#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
+#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
+#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
+
+/* controller 4, Base address 203000 */
+#define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000
+#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
+#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
+#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
+
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata LSZ ADD */
+#define CONFIG_NET_MULTI
+#define CONFIG_E1000
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CONFIG_DOS_PARTITION
+#endif
+
+/* Qman/Bman */
+#ifndef CONFIG_NOBQFMAN
+#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
+#define CONFIG_SYS_BMAN_NUM_PORTALS 18
+#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
+#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
+#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
+#define CONFIG_SYS_QMAN_NUM_PORTALS 18
+#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
+#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
+#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
+
+#define CONFIG_SYS_DPAA_FMAN
+#define CONFIG_SYS_DPAA_PME
+#define CONFIG_SYS_PMAN
+#define CONFIG_SYS_DPAA_DCE
+#define CONFIG_SYS_DPAA_RMAN /* RMan */
+#define CONFIG_SYS_INTERLAKEN
+
+/* Default address of microcode for the Linux Fman driver */
+#if defined(CONFIG_SPIFLASH)
+/*
+ * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
+ * env, so we got 0x110000.
+ */
+#define CONFIG_SYS_QE_FW_IN_SPIFLASH
+#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000
+#elif defined(CONFIG_SDCARD)
+/*
+ * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
+ * about 545KB (1089 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
+ */
+#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
+#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
+#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+/*
+ * Slave has no ucode locally, it can fetch this from remote. When implementing
+ * in two corenet boards, slave's ucode could be stored in master's memory
+ * space, the address can be mapped from slave TLB->slave LAW->
+ * slave SRIO or PCIE outbound window->master inbound window->
+ * master LAW->the ucode address in master's memory space.
+ */
+#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
+#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000
+#else
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
+#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000
+#endif
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
+#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+#endif /* CONFIG_NOBQFMAN */
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_FMAN_ENET
+#define CONFIG_PHYLIB_10G
+#define CONFIG_PHY_VITESSE
+#define CONFIG_PHY_REALTEK
+#define CONFIG_PHY_TERANETICS
+#define RGMII_PHY1_ADDR 0x1
+#define RGMII_PHY2_ADDR 0x2
+#define FM1_10GEC1_PHY_ADDR 0x3
+#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
+#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
+#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
+#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
+#endif
+
+#ifdef CONFIG_FMAN_ENET
+#define CONFIG_MII /* MII PHY management */
+#define CONFIG_ETHPRIME "FM1@DTSEC3"
+#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
+#endif
+
+/*
+ * SATA
+ */
+#ifdef CONFIG_FSL_SATA_V2
+#define CONFIG_LIBATA
+#define CONFIG_FSL_SATA
+#define CONFIG_SYS_SATA_MAX_DEVICE 2
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
+#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
+#define CONFIG_SATA2
+#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
+#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
+#define CONFIG_LBA48
+#define CONFIG_CMD_SATA
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#endif
+
+/*
+ * USB
+ */
+#ifdef CONFIG_USB_EHCI
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_CMD_EXT2
+#define CONFIG_HAS_FSL_DR_USB
+#endif
+
+/*
+ * SDHC
+ */
+#ifdef CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+/*
+ * Environment
+ */
+#define CONFIG_LOADS_ECHO /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_ERRATA
+#define CONFIG_CMD_GREPENV
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_BDI
+
+#ifdef CONFIG_PCI
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_CMDLINE_EDITING /* Command-line editing */
+#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
+#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ROOTPATH "/opt/nfsroot"
+#define CONFIG_BOOTFILE "uImage"
+#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR 1000000
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
+#define __USB_PHY_TYPE utmi
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "hwconfig=fsl_ddr:" \
+ "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
+ "bank_intlv=auto;" \
+ "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
+ "netdev=eth0\0" \
+ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
+ "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
+ "tftpflash=tftpboot $loadaddr $uboot && " \
+ "protect off $ubootaddr +$filesize && " \
+ "erase $ubootaddr +$filesize && " \
+ "cp.b $loadaddr $ubootaddr $filesize && " \
+ "protect on $ubootaddr +$filesize && " \
+ "cmp.b $loadaddr $ubootaddr $filesize\0" \
+ "consoledev=ttyS0\0" \
+ "ramdiskaddr=2000000\0" \
+ "ramdiskfile=t2080qds/ramdisk.uboot\0" \
+ "fdtaddr=c00000\0" \
+ "fdtfile=t2080qds/t2080qds.dtb\0" \
+ "bdev=sda3\0" \
+ "c=ffe\0"
+
+/*
+ * For emulation this causes u-boot to jump to the start of the
+ * proof point app code automatically
+ */
+#define CONFIG_PROOF_POINTS \
+ "setenv bootargs root=/dev/$bdev rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "cpu 1 release 0x29000000 - - -;" \
+ "cpu 2 release 0x29000000 - - -;" \
+ "cpu 3 release 0x29000000 - - -;" \
+ "cpu 4 release 0x29000000 - - -;" \
+ "cpu 5 release 0x29000000 - - -;" \
+ "cpu 6 release 0x29000000 - - -;" \
+ "cpu 7 release 0x29000000 - - -;" \
+ "go 0x29000000"
+
+#define CONFIG_HVBOOT \
+ "setenv bootargs config-addr=0x60000000; " \
+ "bootm 0x01000000 - 0x00f00000"
+
+#define CONFIG_ALU \
+ "setenv bootargs root=/dev/$bdev rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "cpu 1 release 0x01000000 - - -;" \
+ "cpu 2 release 0x01000000 - - -;" \
+ "cpu 3 release 0x01000000 - - -;" \
+ "cpu 4 release 0x01000000 - - -;" \
+ "cpu 5 release 0x01000000 - - -;" \
+ "cpu 6 release 0x01000000 - - -;" \
+ "cpu 7 release 0x01000000 - - -;" \
+ "go 0x01000000"
+
+#define CONFIG_LINUX \
+ "setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "setenv ramdiskaddr 0x02000000;" \
+ "setenv fdtaddr 0x00c00000;" \
+ "setenv loadaddr 0x1000000;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_HDBOOT \
+ "setenv bootargs root=/dev/$bdev rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_NFSBOOTCOMMAND \
+ "setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$serverip:$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+ "setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $ramdiskaddr $ramdiskfile;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND CONFIG_LINUX
+
+#ifdef CONFIG_SECURE_BOOT
+#include <asm/fsl_secure_boot.h>
+#undef CONFIG_CMD_USB
+#endif
+
+#endif /* __T2080QDS_H */
diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h
index 3777ccb..c96df54 100644
--- a/include/configs/T4240QDS.h
+++ b/include/configs/T4240QDS.h
@@ -229,6 +229,8 @@
#define CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
+#define CONFIG_SYS_NAND_MAX_OOBFREE 2
+#define CONFIG_SYS_NAND_MAX_ECCPOS 256
#if defined(CONFIG_NAND)
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
diff --git a/include/configs/alpr.h b/include/configs/alpr.h
index 2bf1986..61fdeba 100644
--- a/include/configs/alpr.h
+++ b/include/configs/alpr.h
@@ -324,6 +324,8 @@
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE + 0, CONFIG_SYS_NAND_BASE + 2, \
CONFIG_SYS_NAND_BASE + 4, CONFIG_SYS_NAND_BASE + 6 }
#define CONFIG_SYS_NAND_QUIET_TEST 1 /* don't warn upon unknown NAND flash */
+#define CONFIG_SYS_NAND_MAX_OOBFREE 2
+#define CONFIG_SYS_NAND_MAX_ECCPOS 56
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index e8a6ca1..8af4d6a 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -182,7 +182,6 @@
#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
#define CONFIG_BAUDRATE 115200
-/* I2C Configuration */
#define CONFIG_CMD_EEPROM
#define CONFIG_ENV_EEPROM_IS_ON_I2C
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
@@ -224,6 +223,8 @@
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds"
#ifdef CONFIG_NAND
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_NAND_OMAP_ELM
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
CONFIG_SYS_NAND_PAGE_SIZE)
@@ -241,7 +242,8 @@
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 14
-
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
#endif
diff --git a/include/configs/am335x_igep0033.h b/include/configs/am335x_igep0033.h
index 2c69d4e..115d1b3 100644
--- a/include/configs/am335x_igep0033.h
+++ b/include/configs/am335x_igep0033.h
@@ -187,6 +187,7 @@
/* NAND support */
#define CONFIG_NAND
#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_NAND_OMAP_ELM
#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
#define CONFIG_SYS_NAND_BASE (0x08000000) /* phys address CS0 */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
@@ -263,6 +264,7 @@
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 14
+#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h
index c5e67bf..468fb43 100644
--- a/include/configs/am3517_crane.h
+++ b/include/configs/am3517_crane.h
@@ -142,10 +142,10 @@
#undef CONFIG_CMD_IMLS /* List all found images */
#define CONFIG_SYS_NO_FLASH
-#define CONFIG_HARD_I2C 1
-#define CONFIG_SYS_I2C_SPEED 100000
-#define CONFIG_SYS_I2C_SLAVE 1
-#define CONFIG_DRIVER_OMAP34XX_I2C 1
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
+#define CONFIG_SYS_I2C_OMAP34XX
#undef CONFIG_CMD_NET
#undef CONFIG_CMD_NFS
@@ -340,6 +340,7 @@
10, 11, 12, 13}
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 3
+#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h
index 5e259f5..1fa477a 100644
--- a/include/configs/am3517_evm.h
+++ b/include/configs/am3517_evm.h
@@ -136,10 +136,10 @@
#undef CONFIG_CMD_IMLS /* List all found images */
#define CONFIG_SYS_NO_FLASH
-#define CONFIG_HARD_I2C 1
-#define CONFIG_SYS_I2C_SPEED 100000
-#define CONFIG_SYS_I2C_SLAVE 1
-#define CONFIG_DRIVER_OMAP34XX_I2C 1
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
+#define CONFIG_SYS_I2C_OMAP34XX
/*
* Ethernet
@@ -344,6 +344,7 @@
10, 11, 12, 13}
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 3
+#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
diff --git a/include/configs/bct-brettl2.h b/include/configs/bct-brettl2.h
index ce09c2e..5b09b45 100644
--- a/include/configs/bct-brettl2.h
+++ b/include/configs/bct-brettl2.h
@@ -111,8 +111,8 @@
* it linked after the configuration sector.
*/
# define LDS_BOARD_TEXT \
- arch/blackfin/lib/libblackfin.o (.text*); \
- arch/blackfin/cpu/libblackfin.o (.text*); \
+ arch/blackfin/lib/built-in.o (.text*); \
+ arch/blackfin/cpu/built-in.o (.text*); \
. = DEFINED(env_offset) ? env_offset : .; \
common/env_embedded.o (.text*);
#endif
diff --git a/include/configs/bf533-stamp.h b/include/configs/bf533-stamp.h
index 7144c63..a22c868 100644
--- a/include/configs/bf533-stamp.h
+++ b/include/configs/bf533-stamp.h
@@ -155,8 +155,8 @@
* it linked after the configuration sector.
*/
# define LDS_BOARD_TEXT \
- arch/blackfin/lib/libblackfin.o (.text*); \
- arch/blackfin/cpu/libblackfin.o (.text*); \
+ arch/blackfin/lib/built-in.o (.text*); \
+ arch/blackfin/cpu/built-in.o (.text*); \
. = DEFINED(env_offset) ? env_offset : .; \
common/env_embedded.o (.text*);
#endif
diff --git a/include/configs/bf537-pnav.h b/include/configs/bf537-pnav.h
index 62bd3bf..3aa3d50 100644
--- a/include/configs/bf537-pnav.h
+++ b/include/configs/bf537-pnav.h
@@ -111,8 +111,8 @@
* it linked after the configuration sector.
*/
# define LDS_BOARD_TEXT \
- arch/blackfin/lib/libblackfin.o (.text*); \
- arch/blackfin/cpu/libblackfin.o (.text*); \
+ arch/blackfin/lib/built-in.o (.text*); \
+ arch/blackfin/cpu/built-in.o (.text*); \
. = DEFINED(env_offset) ? env_offset : .; \
common/env_embedded.o (.text*);
#endif
diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h
index 25cebf8..02945be 100644
--- a/include/configs/bf537-stamp.h
+++ b/include/configs/bf537-stamp.h
@@ -118,8 +118,8 @@
* it linked after the configuration sector.
*/
# define LDS_BOARD_TEXT \
- arch/blackfin/lib/libblackfin.o (.text*); \
- arch/blackfin/cpu/libblackfin.o (.text*); \
+ arch/blackfin/lib/built-in.o (.text*); \
+ arch/blackfin/cpu/built-in.o (.text*); \
. = DEFINED(env_offset) ? env_offset : .; \
common/env_embedded.o (.text*);
#endif
diff --git a/include/configs/bf538f-ezkit.h b/include/configs/bf538f-ezkit.h
index 77822e7..ffb0caf 100644
--- a/include/configs/bf538f-ezkit.h
+++ b/include/configs/bf538f-ezkit.h
@@ -115,8 +115,8 @@
* it linked after the configuration sector.
*/
# define LDS_BOARD_TEXT \
- arch/blackfin/lib/libblackfin.o (.text*); \
- arch/blackfin/cpu/libblackfin.o (.text*); \
+ arch/blackfin/lib/built-in.o (.text*); \
+ arch/blackfin/cpu/built-in.o (.text*); \
. = DEFINED(env_offset) ? env_offset : .; \
common/env_embedded.o (.text*);
#endif
diff --git a/include/configs/cm-bf537e.h b/include/configs/cm-bf537e.h
index 77f47d9..8f10eba 100644
--- a/include/configs/cm-bf537e.h
+++ b/include/configs/cm-bf537e.h
@@ -112,8 +112,8 @@
* it linked after the configuration sector.
*/
# define LDS_BOARD_TEXT \
- arch/blackfin/lib/libblackfin.o (.text*); \
- arch/blackfin/cpu/libblackfin.o (.text*); \
+ arch/blackfin/lib/built-in.o (.text*); \
+ arch/blackfin/cpu/built-in.o (.text*); \
. = DEFINED(env_offset) ? env_offset : .; \
common/env_embedded.o (.text*);
#endif
diff --git a/include/configs/cm-bf537u.h b/include/configs/cm-bf537u.h
index 55e61d6..a1c8e8a 100644
--- a/include/configs/cm-bf537u.h
+++ b/include/configs/cm-bf537u.h
@@ -110,8 +110,8 @@
* it linked after the configuration sector.
*/
# define LDS_BOARD_TEXT \
- arch/blackfin/lib/libblackfin.o (.text*); \
- arch/blackfin/cpu/libblackfin.o (.text*); \
+ arch/blackfin/lib/built-in.o (.text*); \
+ arch/blackfin/cpu/built-in.o (.text*); \
. = DEFINED(env_offset) ? env_offset : .; \
common/env_embedded.o (.text*);
#endif
diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h
index a490fc3..e72187e 100644
--- a/include/configs/cm_t35.h
+++ b/include/configs/cm_t35.h
@@ -141,10 +141,10 @@
#undef CONFIG_CMD_IMLS /* List all found images */
#define CONFIG_SYS_NO_FLASH
-#define CONFIG_HARD_I2C
-#define CONFIG_SYS_I2C_SPEED 100000
-#define CONFIG_SYS_I2C_SLAVE 1
-#define CONFIG_DRIVER_OMAP34XX_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
+#define CONFIG_SYS_I2C_OMAP34XX
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_I2C_MULTI_BUS
@@ -326,5 +326,8 @@
#define CONFIG_SPLASH_SCREEN
#define CONFIG_CMD_BMP
#define CONFIG_BMP_16BPP
+#define CONFIG_SCF0403_LCD
+
+#define CONFIG_OMAP3_SPI
#endif /* __CONFIG_H */
diff --git a/include/configs/controlcenterd.h b/include/configs/controlcenterd.h
index 413f086..46d4f98 100644
--- a/include/configs/controlcenterd.h
+++ b/include/configs/controlcenterd.h
@@ -138,7 +138,7 @@
#define CONFIG_SYS_SDRAM_SIZE 1024
#define CONFIG_VERY_BIG_RAM
-#define CONFIG_FSL_DDR3
+#define CONFIG_SYS_FSL_DDR3
#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index 562caa5..665295c 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -173,7 +173,7 @@
#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
#define CONFIG_DDR_SPD
-#define CONFIG_FSL_DDR3
+#define CONFIG_SYS_FSL_DDR3
#define CONFIG_SYS_SPD_BUS_NUM 1
#define SPD_EEPROM_ADDRESS1 0x51
diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h
index 8343891..4f43ba9 100644
--- a/include/configs/devkit8000.h
+++ b/include/configs/devkit8000.h
@@ -90,10 +90,10 @@
#define CONFIG_DOS_PARTITION 1
/* I2C */
-#define CONFIG_HARD_I2C 1
-#define CONFIG_SYS_I2C_SPEED 100000
-#define CONFIG_SYS_I2C_SLAVE 1
-#define CONFIG_DRIVER_OMAP34XX_I2C 1
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
+#define CONFIG_SYS_I2C_OMAP34XX
/* TWL4030 */
#define CONFIG_TWL4030_POWER 1
@@ -327,6 +327,7 @@
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 3
+#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
diff --git a/include/configs/dig297.h b/include/configs/dig297.h
index c19c4c7..5049afc 100644
--- a/include/configs/dig297.h
+++ b/include/configs/dig297.h
@@ -123,10 +123,10 @@
#undef CONFIG_CMD_NFS /* NFS support */
#define CONFIG_SYS_NO_FLASH
-#define CONFIG_HARD_I2C
-#define CONFIG_SYS_I2C_SPEED 100000
-#define CONFIG_SYS_I2C_SLAVE 1
-#define CONFIG_DRIVER_OMAP34XX_I2C 1
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
+#define CONFIG_SYS_I2C_OMAP34XX
/*
* TWL4030
diff --git a/include/configs/dnp5370.h b/include/configs/dnp5370.h
index f2f4102..d0e72e3 100644
--- a/include/configs/dnp5370.h
+++ b/include/configs/dnp5370.h
@@ -85,8 +85,8 @@
#define ENV_IS_EMBEDDED
#define LDS_BOARD_TEXT \
- arch/blackfin/lib/libblackfin.o (.text*); \
- arch/blackfin/cpu/libblackfin.o (.text*); \
+ arch/blackfin/lib/built-in.o (.text*); \
+ arch/blackfin/cpu/built-in.o (.text*); \
. = DEFINED(env_offset) ? env_offset : .; \
common/env_embedded.o (.text*);
diff --git a/include/configs/ecovec.h b/include/configs/ecovec.h
index 335e9cd..3483cf1 100644
--- a/include/configs/ecovec.h
+++ b/include/configs/ecovec.h
@@ -58,18 +58,17 @@
/* I2C */
#define CONFIG_CMD_I2C
-#define CONFIG_SH_I2C 1
-#define CONFIG_HARD_I2C 1
-#define CONFIG_I2C_MULTI_BUS 1
-#define CONFIG_SYS_MAX_I2C_BUS 2
-#define CONFIG_SYS_I2C_MODULE 1
-#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SH
#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 2
+#define CONFIG_SYS_I2C_SH_BASE0 0xA4470000
+#define CONFIG_SYS_I2C_SH_SPEED0 100000
+#define CONFIG_SYS_I2C_SH_BASE1 0xA4750000
+#define CONFIG_SYS_I2C_SH_SPEED1 100000
#define CONFIG_SH_I2C_DATA_HIGH 4
#define CONFIG_SH_I2C_DATA_LOW 5
#define CONFIG_SH_I2C_CLOCK 41666666
-#define CONFIG_SH_I2C_BASE0 0xA4470000
-#define CONFIG_SH_I2C_BASE1 0xA4750000
/* Ether */
#define CONFIG_SH_ETHER 1
diff --git a/include/configs/highbank.h b/include/configs/highbank.h
index b86eb43..7dbee3c 100644
--- a/include/configs/highbank.h
+++ b/include/configs/highbank.h
@@ -8,7 +8,6 @@
#define __CONFIG_H
#define CONFIG_SYS_DCACHE_OFF
-#define CONFIG_L2_OFF
#define CONFIG_SYS_THUMB_BUILD
#define CONFIG_SYS_NO_FLASH
diff --git a/include/configs/ibf-dsp561.h b/include/configs/ibf-dsp561.h
index 5291755..ac5ca9a 100644
--- a/include/configs/ibf-dsp561.h
+++ b/include/configs/ibf-dsp561.h
@@ -95,8 +95,8 @@
* it linked after the configuration sector.
*/
# define LDS_BOARD_TEXT \
- arch/blackfin/lib/libblackfin.o (.text*); \
- arch/blackfin/cpu/libblackfin.o (.text*); \
+ arch/blackfin/lib/built-in.o (.text*); \
+ arch/blackfin/cpu/built-in.o (.text*); \
. = DEFINED(env_offset) ? env_offset : .; \
common/env_embedded.o (.text*);
#endif
diff --git a/include/configs/km/kmp204x-common.h b/include/configs/km/kmp204x-common.h
index 2d5320b..7700b38 100644
--- a/include/configs/km/kmp204x-common.h
+++ b/include/configs/km/kmp204x-common.h
@@ -111,7 +111,7 @@
#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
#define CONFIG_DDR_SPD
-#define CONFIG_FSL_DDR3
+#define CONFIG_SYS_FSL_DDR3
#define CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SYS_SPD_BUS_NUM 0
diff --git a/include/configs/kzm9g.h b/include/configs/kzm9g.h
index 1afd487..f183279 100644
--- a/include/configs/kzm9g.h
+++ b/include/configs/kzm9g.h
@@ -22,7 +22,6 @@
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_L2_OFF
#define CONFIG_OF_LIBFDT
#include <config_cmd_default.h>
@@ -139,21 +138,22 @@
/* I2C */
#define CONFIG_CMD_I2C
-#define CONFIG_SH_I2C 1
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SH
+#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 5
+#define CONFIG_SYS_I2C_SH_BASE0 0xE6820000
+#define CONFIG_SYS_I2C_SH_SPEED0 100000
+#define CONFIG_SYS_I2C_SH_BASE1 0xE6822000
+#define CONFIG_SYS_I2C_SH_SPEED1 100000
+#define CONFIG_SYS_I2C_SH_BASE2 0xE6824000
+#define CONFIG_SYS_I2C_SH_SPEED2 100000
+#define CONFIG_SYS_I2C_SH_BASE3 0xE6826000
+#define CONFIG_SYS_I2C_SH_SPEED3 100000
+#define CONFIG_SYS_I2C_SH_BASE4 0xE6828000
+#define CONFIG_SYS_I2C_SH_SPEED4 100000
#define CONFIG_SH_I2C_8BIT
-#define CONFIG_HARD_I2C
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_SYS_MAX_I2C_BUS (5)
-#define CONFIG_SYS_I2C_MODULE
-#define CONFIG_SYS_I2C_SPEED (100000) /* 100 kHz */
-#define CONFIG_SYS_I2C_SLAVE (0x7F)
-#define CONFIG_SH_I2C_DATA_HIGH (4)
-#define CONFIG_SH_I2C_DATA_LOW (5)
-#define CONFIG_SH_I2C_CLOCK (104000000) /* 104 MHz */
-#define CONFIG_SH_I2C_BASE0 (0xE6820000)
-#define CONFIG_SH_I2C_BASE1 (0xE6822000)
-#define CONFIG_SH_I2C_BASE2 (0xE6824000)
-#define CONFIG_SH_I2C_BASE3 (0xE6826000)
-#define CONFIG_SH_I2C_BASE4 (0xE6828000)
+#define CONFIG_SH_I2C_DATA_HIGH 4
+#define CONFIG_SH_I2C_DATA_LOW 5
+#define CONFIG_SH_I2C_CLOCK 104000000 /* 104 MHz */
#endif /* __KZM9G_H */
diff --git a/include/configs/qemu-malta.h b/include/configs/malta.h
similarity index 66%
rename from include/configs/qemu-malta.h
rename to include/configs/malta.h
index 03514d1..cc574ed 100644
--- a/include/configs/qemu-malta.h
+++ b/include/configs/malta.h
@@ -4,8 +4,8 @@
* SPDX-License-Identifier: GPL-2.0
*/
-#ifndef _QEMU_MALTA_CONFIG_H
-#define _QEMU_MALTA_CONFIG_H
+#ifndef _MALTA_CONFIG_H
+#define _MALTA_CONFIG_H
#include <asm/addrspace.h>
#include <asm/malta.h>
@@ -13,12 +13,21 @@
/*
* System configuration
*/
-#define CONFIG_QEMU_MALTA
+#define CONFIG_MALTA
+
+#define CONFIG_MEMSIZE_IN_BYTES
#define CONFIG_PCI
#define CONFIG_PCI_GT64120
+#define CONFIG_PCI_MSC01
#define CONFIG_PCI_PNP
#define CONFIG_PCNET
+#define CONFIG_PCNET_79C973
+#define PCNET_HAS_PROM
+
+#define CONFIG_MISC_INIT_R
+#define CONFIG_RTC_MC146818
+#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0
/*
* CPU Configuration
@@ -26,17 +35,13 @@
#define CONFIG_SYS_MHZ 250 /* arbitrary value */
#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
-#define CONFIG_SYS_DCACHE_SIZE 16384 /* arbitrary value */
-#define CONFIG_SYS_ICACHE_SIZE 16384 /* arbitrary value */
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* arbitrary value */
-
#define CONFIG_SWAP_IO_SPACE
/*
* Memory map
*/
-#define CONFIG_SYS_TEXT_BASE 0xbfc00000 /* Rom version */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_TEXT_BASE 0xbe000000 /* Rom version */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
#define CONFIG_SYS_MEM_SIZE (256 * 1024 * 1024)
@@ -49,14 +54,15 @@
#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024)
+#define CONFIG_SYS_BOOTM_LEN (64 * 1024 * 1024)
/*
* Console configuration
*/
#if defined(CONFIG_SYS_LITTLE_ENDIAN)
-#define CONFIG_SYS_PROMPT "qemu-maltael # "
+#define CONFIG_SYS_PROMPT "maltael # "
#else
-#define CONFIG_SYS_PROMPT "qemu-malta # "
+#define CONFIG_SYS_PROMPT "malta # "
#endif
#define CONFIG_SYS_CBSIZE 256
@@ -75,17 +81,12 @@
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK 115200
-#define CONFIG_SYS_NS16550_COM1 CKSEG1ADDR(MALTA_UART_BASE)
+#define CONFIG_SYS_NS16550_CLK (115200 * 16)
+#define CONFIG_SYS_NS16550_COM1 CKSEG1ADDR(MALTA_GT_UART0_BASE)
+#define CONFIG_SYS_NS16550_COM2 CKSEG1ADDR(MALTA_MSC01_UART0_BASE)
#define CONFIG_CONS_INDEX 1
/*
- * Environment
- */
-#define CONFIG_ENV_IS_NOWHERE
-#define CONFIG_ENV_SIZE 0x10000
-
-/*
* Flash configuration
*/
#define CONFIG_SYS_FLASH_BASE (KSEG1 | MALTA_FLASH_BASE)
@@ -96,6 +97,15 @@
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
/*
+ * Environment
+ */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE 0x20000
+#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
+#define CONFIG_ENV_ADDR \
+ (CONFIG_SYS_FLASH_BASE + (4 << 20) - CONFIG_ENV_SIZE)
+
+/*
* Commands
*/
#include <config_cmd_default.h>
@@ -105,9 +115,11 @@
#undef CONFIG_CMD_LOADS
#undef CONFIG_CMD_NFS
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING
#define CONFIG_SYS_LONGHELP /* verbose help, undef to save memory */
-#endif /* _QEMU_MALTA_CONFIG_H */
+#endif /* _MALTA_CONFIG_H */
diff --git a/include/configs/mcx.h b/include/configs/mcx.h
index 4619dfb..dcd29ce 100644
--- a/include/configs/mcx.h
+++ b/include/configs/mcx.h
@@ -137,10 +137,10 @@
#undef CONFIG_CMD_IMLS /* List all found images */
#define CONFIG_SYS_NO_FLASH
-#define CONFIG_HARD_I2C
-#define CONFIG_SYS_I2C_SPEED 100000
-#define CONFIG_SYS_I2C_SLAVE 1
-#define CONFIG_DRIVER_OMAP34XX_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
+#define CONFIG_SYS_I2C_OMAP34XX
/* RTC */
#define CONFIG_RTC_DS1337
@@ -353,7 +353,6 @@
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_NAND_SIMPLE
-#define CONFIG_SPL_NAND_SOFTECC
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBDISK_SUPPORT
@@ -395,6 +394,7 @@
56, 57, 58, 59, 60, 61, 62, 63}
#define CONFIG_SYS_NAND_ECCSIZE 256
#define CONFIG_SYS_NAND_ECCBYTES 3
+#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
diff --git a/include/configs/mpq101.h b/include/configs/mpq101.h
index 6d0d392..ec09e15 100644
--- a/include/configs/mpq101.h
+++ b/include/configs/mpq101.h
@@ -52,7 +52,7 @@
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
/* DDR Setup */
-#define CONFIG_FSL_DDR2
+#define CONFIG_SYS_FSL_DDR2
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
diff --git a/include/configs/mx51_efikamx.h b/include/configs/mx51_efikamx.h
index 8a44ef5..0f2a4ef 100644
--- a/include/configs/mx51_efikamx.h
+++ b/include/configs/mx51_efikamx.h
@@ -29,7 +29,6 @@
#define CONFIG_SYS_TEXT_BASE 0x97800000
-#define CONFIG_L2_OFF
#define CONFIG_SYS_ICACHE_OFF
#define CONFIG_SYS_DCACHE_OFF
diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h
index 4332779..e0c0fac 100644
--- a/include/configs/nokia_rx51.h
+++ b/include/configs/nokia_rx51.h
@@ -157,10 +157,10 @@
#undef CONFIG_CMD_SETGETDCR /* DCR support on 4xx */
#define CONFIG_OMAP3_SPI
-#define CONFIG_HARD_I2C
-#define CONFIG_SYS_I2C_SPEED 100000
-#define CONFIG_SYS_I2C_SLAVE 1
-#define CONFIG_DRIVER_OMAP34XX_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
+#define CONFIG_SYS_I2C_OMAP34XX
/*
* TWL4030
diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
index c662cc0..3acb854 100644
--- a/include/configs/omap3_beagle.h
+++ b/include/configs/omap3_beagle.h
@@ -158,11 +158,10 @@
#undef CONFIG_CMD_IMLS /* List all found images */
#define CONFIG_SYS_NO_FLASH
-#define CONFIG_HARD_I2C 1
-#define CONFIG_SYS_I2C_SPEED 100000
-#define CONFIG_SYS_I2C_SLAVE 1
-#define CONFIG_I2C_MULTI_BUS 1
-#define CONFIG_DRIVER_OMAP34XX_I2C 1
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
+#define CONFIG_SYS_I2C_OMAP34XX
#define CONFIG_VIDEO_OMAP3 /* DSS Support */
/*
@@ -429,6 +428,7 @@
10, 11, 12, 13}
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 3
+#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
index 3ace8bb..b7638fb 100644
--- a/include/configs/omap3_evm.h
+++ b/include/configs/omap3_evm.h
@@ -107,6 +107,7 @@
10, 11, 12, 13}
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 3
+#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
diff --git a/include/configs/omap3_evm_common.h b/include/configs/omap3_evm_common.h
index 3eae288..43616e2 100644
--- a/include/configs/omap3_evm_common.h
+++ b/include/configs/omap3_evm_common.h
@@ -87,11 +87,10 @@
/*
* I2C
*/
-#define CONFIG_HARD_I2C
-#define CONFIG_DRIVER_OMAP34XX_I2C
-
-#define CONFIG_SYS_I2C_SPEED 100000
-#define CONFIG_SYS_I2C_SLAVE 1
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
+#define CONFIG_SYS_I2C_OMAP34XX
/*
* PISMO support
diff --git a/include/configs/omap3_evm_quick_nand.h b/include/configs/omap3_evm_quick_nand.h
index 9ecd70d..4427e88 100644
--- a/include/configs/omap3_evm_quick_nand.h
+++ b/include/configs/omap3_evm_quick_nand.h
@@ -86,6 +86,7 @@
10, 11, 12, 13}
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 3
+#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h
index ac36ac6..71062a6 100644
--- a/include/configs/omap3_igep00x0.h
+++ b/include/configs/omap3_igep00x0.h
@@ -124,10 +124,10 @@
#undef CONFIG_CMD_IMLS /* List all found images */
#define CONFIG_SYS_NO_FLASH
-#define CONFIG_HARD_I2C 1
-#define CONFIG_SYS_I2C_SPEED 100000
-#define CONFIG_SYS_I2C_SLAVE 1
-#define CONFIG_DRIVER_OMAP34XX_I2C 1
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_OMAP34XX
+#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
/*
* TWL4030
@@ -362,6 +362,7 @@
10, 11, 12, 13}
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 3
+#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
#endif
diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h
index 0c096f4..bedd6f9 100644
--- a/include/configs/omap3_logic.h
+++ b/include/configs/omap3_logic.h
@@ -118,12 +118,10 @@
/*
* I2C
*/
-#define CONFIG_HARD_I2C
-#define CONFIG_DRIVER_OMAP34XX_I2C
-
-#define CONFIG_SYS_I2C_SPEED 100000
-#define CONFIG_SYS_I2C_SLAVE 1
-#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
+#define CONFIG_SYS_I2C_OMAP34XX
/*
* TWL4030
diff --git a/include/configs/omap3_mvblx.h b/include/configs/omap3_mvblx.h
index 45da2e0..8d11010 100644
--- a/include/configs/omap3_mvblx.h
+++ b/include/configs/omap3_mvblx.h
@@ -128,11 +128,10 @@
#define CONFIG_CMD_PING
#define CONFIG_CMD_FPGA
-#define CONFIG_HARD_I2C 1
-#define CONFIG_SYS_I2C_SPEED 100000
-#define CONFIG_SYS_I2C_SLAVE 0
-#define CONFIG_DRIVER_OMAP34XX_I2C 1
-#define CONFIG_I2C_MULTI_BUS 1
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
+#define CONFIG_SYS_I2C_OMAP34XX
/*
* TWL4030
diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h
index 4641694..e0f0262 100644
--- a/include/configs/omap3_overo.h
+++ b/include/configs/omap3_overo.h
@@ -98,11 +98,10 @@
#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
#define CONFIG_SYS_NO_FLASH
-#define CONFIG_HARD_I2C
-#define CONFIG_SYS_I2C_SPEED 100000
-#define CONFIG_SYS_I2C_SLAVE 1
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_DRIVER_OMAP34XX_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
+#define CONFIG_SYS_I2C_OMAP34XX
/*
* TWL4030
@@ -325,6 +324,7 @@
10, 11, 12, 13}
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 3
+#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h
index 3cce0de..eacdfaa 100644
--- a/include/configs/omap3_pandora.h
+++ b/include/configs/omap3_pandora.h
@@ -111,10 +111,10 @@
#undef CONFIG_CMD_NFS /* NFS support */
#define CONFIG_SYS_NO_FLASH
-#define CONFIG_HARD_I2C 1
-#define CONFIG_SYS_I2C_SPEED 100000
-#define CONFIG_SYS_I2C_SLAVE 1
-#define CONFIG_DRIVER_OMAP34XX_I2C 1
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
+#define CONFIG_SYS_I2C_OMAP34XX
/*
* TWL4030
diff --git a/include/configs/omap3_sdp3430.h b/include/configs/omap3_sdp3430.h
index 697a3f3..6f1304d 100644
--- a/include/configs/omap3_sdp3430.h
+++ b/include/configs/omap3_sdp3430.h
@@ -114,10 +114,10 @@
/*
* I2C for power management setup
*/
-#define CONFIG_HARD_I2C 1
-#define CONFIG_SYS_I2C_SPEED 100000
-#define CONFIG_SYS_I2C_SLAVE 1
-#define CONFIG_DRIVER_OMAP34XX_I2C 1
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
+#define CONFIG_SYS_I2C_OMAP34XX
/* OMITTED: single 1 Gbit MT29F1G NAND flash */
diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h
index 8591f98..1dd53fa 100644
--- a/include/configs/omap3_zoom1.h
+++ b/include/configs/omap3_zoom1.h
@@ -118,10 +118,10 @@
#undef CONFIG_CMD_NFS /* NFS support */
#define CONFIG_SYS_NO_FLASH
-#define CONFIG_HARD_I2C 1
-#define CONFIG_SYS_I2C_SPEED 100000
-#define CONFIG_SYS_I2C_SLAVE 1
-#define CONFIG_DRIVER_OMAP34XX_I2C 1
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
+#define CONFIG_SYS_I2C_OMAP34XX
/*
* TWL4030
diff --git a/include/configs/omap3_zoom2.h b/include/configs/omap3_zoom2.h
index cb8c7ec..f749740 100644
--- a/include/configs/omap3_zoom2.h
+++ b/include/configs/omap3_zoom2.h
@@ -138,10 +138,10 @@
#undef CONFIG_CMD_NFS /* NFS support */
#define CONFIG_SYS_NO_FLASH
-#define CONFIG_HARD_I2C 1
-#define CONFIG_SYS_I2C_SPEED 100000
-#define CONFIG_SYS_I2C_SLAVE 1
-#define CONFIG_DRIVER_OMAP34XX_I2C 1
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
+#define CONFIG_SYS_I2C_OMAP34XX
/*
* TWL4030
diff --git a/include/configs/origen.h b/include/configs/origen.h
index bad34b3..f46b833 100644
--- a/include/configs/origen.h
+++ b/include/configs/origen.h
@@ -22,8 +22,6 @@
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_BOARD_EARLY_INIT_F
-/* Keep L2 Cache Disabled */
-#define CONFIG_L2_OFF 1
#define CONFIG_SYS_DCACHE_OFF 1
#define CONFIG_SYS_SDRAM_BASE 0x40000000
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 91a6782..57ed019 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -325,7 +325,7 @@
#endif
/* DDR Setup */
-#define CONFIG_FSL_DDR3
+#define CONFIG_SYS_FSL_DDR3
#define CONFIG_SYS_DDR_RAW_TIMING
#define CONFIG_DDR_SPD
#define CONFIG_SYS_SPD_BUS_NUM 1
diff --git a/include/configs/p1_twr.h b/include/configs/p1_twr.h
index 76189e1..9837100 100644
--- a/include/configs/p1_twr.h
+++ b/include/configs/p1_twr.h
@@ -89,7 +89,7 @@
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
/* DDR Setup */
-#define CONFIG_FSL_DDR3
+#define CONFIG_SYS_FSL_DDR3
#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M
#define CONFIG_CHIP_SELECTS_PER_CTRL 1
diff --git a/include/configs/pcm051.h b/include/configs/pcm051.h
index 4970b13..6f41ee7 100644
--- a/include/configs/pcm051.h
+++ b/include/configs/pcm051.h
@@ -172,11 +172,10 @@
/* I2C Configuration */
#define CONFIG_I2C
#define CONFIG_CMD_I2C
-#define CONFIG_HARD_I2C
-#define CONFIG_SYS_I2C_SPEED 100000
-#define CONFIG_SYS_I2C_SLAVE 1
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_DRIVER_OMAP24XX_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
+#define CONFIG_SYS_I2C_OMAP24XX
#define CONFIG_CMD_EEPROM
#define CONFIG_ENV_EEPROM_IS_ON_I2C
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h
index 0884ad3..a4edc62 100644
--- a/include/configs/sandbox.h
+++ b/include/configs/sandbox.h
@@ -75,7 +75,6 @@
#define CONFIG_SYS_LOAD_ADDR 0x00000000
#define CONFIG_SYS_MEMTEST_START 0x00100000
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x1000)
-#define CONFIG_PHYS_64BIT
#define CONFIG_SYS_FDT_LOAD_ADDR 0x1000000
/* Size of our emulated memory */
diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h
index 6d97060..bdb8eb5 100644
--- a/include/configs/sbc8548.h
+++ b/include/configs/sbc8548.h
@@ -102,7 +102,7 @@
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
/* DDR Setup */
-#define CONFIG_FSL_DDR2
+#define CONFIG_SYS_FSL_DDR2
#undef CONFIG_FSL_DDR_INTERACTIVE
#undef CONFIG_DDR_ECC /* only for ECC DDR module */
/*
diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h
index 7db0eb8..4569fd4 100644
--- a/include/configs/siemens-am33x-common.h
+++ b/include/configs/siemens-am33x-common.h
@@ -131,11 +131,10 @@
/* I2C Configuration */
#define CONFIG_I2C
#define CONFIG_CMD_I2C
-#define CONFIG_HARD_I2C
-#define CONFIG_SYS_I2C_SLAVE 1
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_DRIVER_OMAP24XX_I2C
-
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED OMAP_I2C_STANDARD
+#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
+#define CONFIG_SYS_I2C_OMAP24XX
/* Defines for SPL */
#define CONFIG_SPL
@@ -196,6 +195,7 @@
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 14
+#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
#define CONFIG_SYS_NAND_ECCSTEPS 4
#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \
@@ -456,6 +456,7 @@
"\0"
#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_NAND_OMAP_ELM
#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
#define CONFIG_SYS_NAND_BASE (0x08000000) /* physical address */
/* to access nand at */
diff --git a/include/configs/smdkv310.h b/include/configs/smdkv310.h
index e2e8efe..1388f49 100644
--- a/include/configs/smdkv310.h
+++ b/include/configs/smdkv310.h
@@ -25,9 +25,6 @@
/* Mach Type */
#define CONFIG_MACH_TYPE MACH_TYPE_SMDKV310
-/* Keep L2 Cache Disabled */
-#define CONFIG_L2_OFF 1
-
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define CONFIG_SYS_TEXT_BASE 0x43E00000
diff --git a/include/configs/snowball.h b/include/configs/snowball.h
index 00d6fa5..9a069f3 100644
--- a/include/configs/snowball.h
+++ b/include/configs/snowball.h
@@ -23,7 +23,6 @@
* (easy to change)
*/
#define CONFIG_U8500
-#define CONFIG_L2_OFF
#define CONFIG_SYS_MEMTEST_START 0x00000000
#define CONFIG_SYS_MEMTEST_END 0x1FFFFFFF
diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h
index 980636c..608578a 100644
--- a/include/configs/socfpga_cyclone5.h
+++ b/include/configs/socfpga_cyclone5.h
@@ -16,7 +16,6 @@
#define CONFIG_SOCFPGA_VIRTUAL_TARGET
#define CONFIG_ARMV7
-#define CONFIG_L2_OFF
#define CONFIG_SYS_DCACHE_OFF
#undef CONFIG_USE_IRQ
diff --git a/include/configs/socrates.h b/include/configs/socrates.h
index b6fbe23..0e6b864 100644
--- a/include/configs/socrates.h
+++ b/include/configs/socrates.h
@@ -80,7 +80,7 @@
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
/* DDR Setup */
-#define CONFIG_FSL_DDR2
+#define CONFIG_SYS_FSL_DDR2
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#define CONFIG_DDR_SPD
diff --git a/include/configs/spieval.h b/include/configs/spieval.h
deleted file mode 100644
index 07668de..0000000
--- a/include/configs/spieval.h
+++ /dev/null
@@ -1,494 +0,0 @@
-/*
- * (C) Copyright 2003-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004-2005
- * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
-#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
-#define CONFIG_TQM5200 1 /* ... on TQM5200 module */
-#undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */
-#define CONFIG_STK52XX 1 /* ... on a STK52XX base board */
-#define CONFIG_STK52XX_REV100 1 /* define for revision 100 baseboards */
-
-#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
-
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE 6 /* console is on PSC6 */
-#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-
-#ifdef CONFIG_STK52XX
-#undef CONFIG_PS2KBD /* AT-PS/2 Keyboard */
-#define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */
-#define CONFIG_PS2SERIAL 6 /* .. on PSC6 */
-#define CONFIG_PS2MULT_DELAY (CONFIG_SYS_HZ/2) /* Initial delay */
-#define CONFIG_BOARD_EARLY_INIT_R
-#endif /* CONFIG_STK52XX */
-
-/*
- * PCI Mapping:
- * 0x40000000 - 0x4fffffff - PCI Memory
- * 0x50000000 - 0x50ffffff - PCI IO Space
- */
-#ifdef CONFIG_STK52XX
-#define CONFIG_PCI 1
-#define CONFIG_PCI_PNP 1
-/* #define CONFIG_PCI_SCAN_SHOW 1 */
-
-#define CONFIG_PCI_MEM_BUS 0x40000000
-#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
-#define CONFIG_PCI_MEM_SIZE 0x10000000
-
-#define CONFIG_PCI_IO_BUS 0x50000000
-#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
-#define CONFIG_PCI_IO_SIZE 0x01000000
-
-#define CONFIG_EEPRO100 1
-#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
-#define CONFIG_NS8382X 1
-#endif /* CONFIG_STK52XX */
-
-/*
- * Video console
- */
-#if 1
-#define CONFIG_VIDEO
-#define CONFIG_VIDEO_SM501
-#define CONFIG_VIDEO_SM501_32BPP
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_CONSOLE_EXTRA_INFO
-#define CONFIG_VIDEO_SW_CURSOR
-#define CONFIG_SPLASH_SCREEN
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#endif
-
-/* Partitions */
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-#define CONFIG_ISO_PARTITION
-
-/* USB */
-#ifdef CONFIG_STK52XX
-#define CONFIG_USB_OHCI
-#define CONFIG_USB_STORAGE
-#endif
-
-/* POST support */
-#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
- CONFIG_SYS_POST_CPU | \
- CONFIG_SYS_POST_I2C)
-
-#ifdef CONFIG_POST
-/* preserve space for the post_word at end of on-chip SRAM */
-#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
-#endif
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_ECHO
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_SNTP
-
-#if defined(CONFIG_MINIFAP) || defined(CONFIG_STK52XX)
- #define CONFIG_CMD_IDE
- #define CONFIG_CMD_FAT
- #define CONFIG_CMD_EXT2
-#endif
-
-#ifdef CONFIG_STK52XX
- #define CONFIG_CMD_USB
- #define CONFIG_CMD_FAT
-#endif
-
-#ifdef CONFIG_VIDEO
- #define CONFIG_CMD_BMP
-#endif
-
-#ifdef CONFIG_PCI
- #define CONFIG_CMD_PCI
- #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
-#endif
-
-#ifdef CONFIG_POST
-#define CONFIG_CMD_DIAG
-#endif
-
-
-#define CONFIG_TIMESTAMP /* display image timestamps */
-
-#if (CONFIG_SYS_TEXT_BASE == 0xFC000000) /* Boot low */
-# define CONFIG_SYS_LOWBOOT 1
-#endif
-
-/*
- * Autobooting
- */
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-
-#define CONFIG_PREBOOT "echo;" \
- "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
- "echo"
-
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "rootpath=/opt/eldk/ppc_6xx\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "flash_self=run ramargs addip;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "flash_nfs=run nfsargs addip;" \
- "bootm ${kernel_addr}\0" \
- "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
- "bootfile=/tftpboot/tqm5200/uImage\0" \
- "load=tftp 200000 ${u-boot}\0" \
- "u-boot=/tftpboot/tqm5200/u-boot.bin\0" \
- "update=protect off FC000000 FC05FFFF;" \
- "erase FC000000 FC05FFFF;" \
- "cp.b 200000 FC000000 ${filesize};" \
- "protect on FC000000 FC05FFFF\0" \
- ""
-
-#define CONFIG_BOOTCOMMAND "run net_nfs"
-
-/*
- * IPB Bus clocking configuration.
- */
-#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
-
-#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
-/*
- * PCI Bus clocking configuration
- *
- * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
- * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
- * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
- */
-#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
-#endif
-
-/*
- * I2C configuration
- */
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#ifdef CONFIG_TQM5200_REV100
-#define CONFIG_SYS_I2C_MODULE 1 /* Select I2C module #1 for rev. 100 board */
-#else
-#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #2 for all other revs */
-#endif
-
-/*
- * I2C clock frequency
- *
- * Please notice, that the resulting clock frequency could differ from the
- * configured value. This is because the I2C clock is derived from system
- * clock over a frequency divider with only a few divider values. U-boot
- * calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated
- * approximation allways lies below the configured value, never above.
- */
-#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-
-/*
- * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
- * also). For other EEPROMs configuration should be verified. On Mini-FAP the
- * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
- * same configuration could be used.
- */
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
-
-/*
- * HW-Monitor configuration on Mini-FAP
- */
-#if defined (CONFIG_MINIFAP)
-#define CONFIG_SYS_I2C_HWMON_ADDR 0x2C
-#endif
-
-/* List of I2C addresses to be verified by POST */
-#if defined (CONFIG_MINIFAP)
-#undef CONFIG_SYS_POST_I2C_ADDRS
-#define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_EEPROM_ADDR, \
- CONFIG_SYS_I2C_HWMON_ADDR, \
- CONFIG_SYS_I2C_SLAVE}
-#endif
-
-/*
- * Flash configuration
- */
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE /* 0xFC000000 */
-
-/* use CFI flash driver if no module variant is spezified */
-#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START }
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MByte */
-#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
-#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */
-
-#if !defined(CONFIG_SYS_LOWBOOT)
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00760000 + 0x00800000)
-#else /* CONFIG_SYS_LOWBOOT */
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000)
-#endif /* CONFIG_SYS_LOWBOOT */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks
- (= chip selects) */
-#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
-
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_SIZE 0x10000
-#define CONFIG_ENV_SECT_SIZE 0x20000
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_MBAR 0xF0000000
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
-
-/* Use ON-Chip SRAM until RAM will be available */
-#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
-#ifdef CONFIG_POST
-/* preserve space for the post_word at end of on-chip SRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE
-#else
-#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
-#endif
-
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-# define CONFIG_SYS_RAMBOOT 1
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC5xxx_FEC 1
-/*
- * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
- */
-/* #define CONFIG_FEC_10MBIT 1 */
-#define CONFIG_PHY_ADDR 0x00
-
-/*
- * GPIO configuration
- *
- * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1):
- * Bit 0 (mask: 0x80000000): 1
- * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
- * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
- * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
- * Use for REV200 STK52XX boards. Do not use with REV100 modules
- * (because, there I2C1 is used as I2C bus)
- * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
- * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030)
- * 000 -> All PSC2 pins are GIOPs
- * 001 -> CAN1/2 on PSC2 pins
- * Use for REV100 STK52xx boards
- * use PSC6:
- * on STK52xx:
- * use as UART. Pins PSC6_0 to PSC6_3 are used.
- * Bits 9:11 (mask: 0x00700000):
- * 101 -> PSC6 : Extended POST test is not available
- * on MINI-FAP and TQM5200_IB:
- * use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000):
- * 000 -> PSC6 could not be used as UART, CODEC or IrDA
- * GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST
- * tests.
- */
-#if defined (CONFIG_MINIFAP)
-# define CONFIG_SYS_GPS_PORT_CONFIG 0x91000004
-#elif defined (CONFIG_STK52XX)
-# if defined (CONFIG_STK52XX_REV100)
-# define CONFIG_SYS_GPS_PORT_CONFIG 0x81500014
-# else /* STK52xx REV200 and above */
-# if defined (CONFIG_TQM5200_REV100)
-# error TQM5200 REV100 not supported on STK52XX REV200 or above
-# else/* TQM5200 REV200 and above */
-# define CONFIG_SYS_GPS_PORT_CONFIG 0x91500004
-# endif
-# endif
-#else /* TMQ5200 Inbetriebnahme-Board */
-# define CONFIG_SYS_GPS_PORT_CONFIG 0x81000004
-#endif
-
-/*
- * RTC configuration
- */
-#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-/* Enable an alternate, more extensive memory test */
-#define CONFIG_SYS_ALT_MEMTEST
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-/*
- * Enable loopw command.
- */
-#define CONFIG_LOOPW
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
-#define CONFIG_SYS_HID0_FINAL HID0_ICE
-
-#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
-#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
-#define CONFIG_SYS_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
-#else
-#define CONFIG_SYS_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
-#endif
-#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
-
-#define CONFIG_LAST_STAGE_INIT
-
-/*
- * SRAM - Do not map below 2 GB in address space, because this area is used
- * for SDRAM autosizing.
- */
-#define CONFIG_SYS_CS2_START 0xE5000000
-#define CONFIG_SYS_CS2_SIZE 0x100000 /* 1 MByte */
-#define CONFIG_SYS_CS2_CFG 0x0004D930
-
-/*
- * Grafic controller - Do not map below 2 GB in address space, because this
- * area is used for SDRAM autosizing.
- */
-#define SM501_FB_BASE 0xE0000000
-#define CONFIG_SYS_CS1_START (SM501_FB_BASE)
-#define CONFIG_SYS_CS1_SIZE 0x4000000 /* 64 MByte */
-#define CONFIG_SYS_CS1_CFG 0x8F48FF70
-#define SM501_MMIO_BASE CONFIG_SYS_CS1_START + 0x03E00000
-
-#define CONFIG_SYS_CS_BURST 0x00000000
-#define CONFIG_SYS_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */
-
-#define CONFIG_SYS_RESET_ADDRESS 0xff000000
-
-/*-----------------------------------------------------------------------
- * USB stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_USB_CLOCK 0x0001BBBB
-#define CONFIG_USB_CONFIG 0x00001000
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff Supports IDE harddisk
- *-----------------------------------------------------------------------
- */
-
-#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
-
-#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
-#undef CONFIG_IDE_LED /* LED for ide not supported */
-
-#define CONFIG_IDE_RESET /* reset for ide supported */
-#define CONFIG_IDE_PREINIT
-
-#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
-#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-
-#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
-
-/* Offset for data I/O */
-#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
-
-/* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
-
-/* Offset for alternate registers */
-#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
-
-/* Interval between registers */
-#define CONFIG_SYS_ATA_STRIDE 4
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h
index 9b3f0cc..ee1f1f3 100644
--- a/include/configs/stxgp3.h
+++ b/include/configs/stxgp3.h
@@ -98,7 +98,7 @@
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
/* DDR Setup */
-#define CONFIG_FSL_DDR1
+#define CONFIG_SYS_FSL_DDR1
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_SPD
#undef CONFIG_FSL_DDR_INTERACTIVE
diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h
index 805814f..63dd767 100644
--- a/include/configs/stxssa.h
+++ b/include/configs/stxssa.h
@@ -112,7 +112,7 @@
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
/* DDR Setup */
-#define CONFIG_FSL_DDR1
+#define CONFIG_SYS_FSL_DDR1
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_SPD
#undef CONFIG_FSL_DDR_INTERACTIVE
diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h
index 3f54f14..d9b0ed0 100644
--- a/include/configs/t4qds.h
+++ b/include/configs/t4qds.h
@@ -87,7 +87,7 @@
#define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
#define CONFIG_DDR_SPD
-#define CONFIG_FSL_DDR3
+#define CONFIG_SYS_FSL_DDR3
/*
diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h
index 683bc54..439fc47 100644
--- a/include/configs/tam3517-common.h
+++ b/include/configs/tam3517-common.h
@@ -117,14 +117,13 @@
#undef CONFIG_CMD_IMLS
#define CONFIG_SYS_NO_FLASH
-#define CONFIG_HARD_I2C
-#define CONFIG_SYS_I2C_SPEED 400000
-#define CONFIG_SYS_I2C_SLAVE 1
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED 400000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
+#define CONFIG_SYS_I2C_OMAP34XX
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
-#define CONFIG_DRIVER_OMAP34XX_I2C
-
/*
* Board NAND Info.
@@ -225,7 +224,6 @@
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_CONSOLE
#define CONFIG_SPL_NAND_SIMPLE
-#define CONFIG_SPL_NAND_SOFTECC
#define CONFIG_SPL_NAND_WORKSPACE 0x8f07f000 /* below BSS */
#define CONFIG_SPL_LIBCOMMON_SUPPORT
@@ -262,6 +260,7 @@
56, 57, 58, 59, 60, 61, 62, 63}
#define CONFIG_SYS_NAND_ECCSIZE 256
#define CONFIG_SYS_NAND_ECCBYTES 3
+#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
@@ -369,7 +368,7 @@
#define TAM3517_READ_EEPROM(info, ret) \
do { \
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); \
+ i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); \
if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, \
(void *)info, sizeof(*info))) \
ret = 1; \
diff --git a/include/configs/tcm-bf537.h b/include/configs/tcm-bf537.h
index 2adb071..627836a 100644
--- a/include/configs/tcm-bf537.h
+++ b/include/configs/tcm-bf537.h
@@ -112,8 +112,8 @@
* it linked after the configuration sector.
*/
# define LDS_BOARD_TEXT \
- arch/blackfin/lib/libblackfin.o (.text*); \
- arch/blackfin/cpu/libblackfin.o (.text*); \
+ arch/blackfin/lib/built-in.o (.text*); \
+ arch/blackfin/cpu/built-in.o (.text*); \
. = DEFINED(env_offset) ? env_offset : .; \
common/env_embedded.o (.text*);
#endif
diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h
index 84269ad..99b60fc 100644
--- a/include/configs/ti_armv7_common.h
+++ b/include/configs/ti_armv7_common.h
@@ -59,12 +59,11 @@
/* I2C IP block */
#define CONFIG_I2C
-#define CONFIG_HARD_I2C
-#define CONFIG_SYS_I2C_SPEED 100000
-#define CONFIG_SYS_I2C_SLAVE 1
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_DRIVER_OMAP24XX_I2C
#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
+#define CONFIG_SYS_I2C_OMAP24XX
/* MMC/SD IP block */
#define CONFIG_MMC
diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h
index d57394e..cc4001f 100644
--- a/include/configs/tricorder.h
+++ b/include/configs/tricorder.h
@@ -98,11 +98,11 @@
#define CONFIG_DOS_PARTITION
/* I2C */
-#define CONFIG_HARD_I2C
-#define CONFIG_SYS_I2C_SPEED 100000
-#define CONFIG_SYS_I2C_SLAVE 1
-#define CONFIG_DRIVER_OMAP34XX_I2C 1
-#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
+#define CONFIG_SYS_I2C_OMAP34XX
+
/* EEPROM */
#define CONFIG_SYS_I2C_MULTI_EEPROMS
@@ -138,8 +138,9 @@
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
/* devices */
-#define CONFIG_NAND_OMAP_BCH8
#define CONFIG_BCH
+#define CONFIG_SYS_NAND_MAX_OOBFREE 2
+#define CONFIG_SYS_NAND_MAX_ECCPOS 56
/* commands to include */
#include <config_cmd_default.h>
@@ -374,6 +375,7 @@
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 13
+#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
diff --git a/include/configs/u8500_href.h b/include/configs/u8500_href.h
index 45d33a6..629299d 100644
--- a/include/configs/u8500_href.h
+++ b/include/configs/u8500_href.h
@@ -12,7 +12,6 @@
* (easy to change)
*/
#define CONFIG_U8500
-#define CONFIG_L2_OFF
#define CONFIG_SYS_MEMTEST_START 0x00000000
#define CONFIG_SYS_MEMTEST_END 0x1FFFFFFF
diff --git a/include/configs/xpedite517x.h b/include/configs/xpedite517x.h
index 4738c23..88d7f88 100644
--- a/include/configs/xpedite517x.h
+++ b/include/configs/xpedite517x.h
@@ -40,7 +40,7 @@
/*
* DDR config
*/
-#define CONFIG_FSL_DDR2
+#define CONFIG_SYS_FSL_DDR2
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#define CONFIG_DDR_SPD
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
diff --git a/include/configs/xpedite520x.h b/include/configs/xpedite520x.h
index 3342880..f39d6f9 100644
--- a/include/configs/xpedite520x.h
+++ b/include/configs/xpedite520x.h
@@ -39,7 +39,7 @@
/*
* DDR config
*/
-#define CONFIG_FSL_DDR2
+#define CONFIG_SYS_FSL_DDR2
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#define CONFIG_DDR_SPD
diff --git a/include/configs/xpedite537x.h b/include/configs/xpedite537x.h
index 9da845d..e1bdf90 100644
--- a/include/configs/xpedite537x.h
+++ b/include/configs/xpedite537x.h
@@ -49,7 +49,7 @@
/*
* DDR config
*/
-#define CONFIG_FSL_DDR2
+#define CONFIG_SYS_FSL_DDR2
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#define CONFIG_DDR_SPD
diff --git a/include/configs/xpedite550x.h b/include/configs/xpedite550x.h
index 4137cc9..2328c7a 100644
--- a/include/configs/xpedite550x.h
+++ b/include/configs/xpedite550x.h
@@ -49,7 +49,7 @@
/*
* DDR config
*/
-#define CONFIG_FSL_DDR3
+#define CONFIG_SYS_FSL_DDR3
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#define CONFIG_DDR_SPD
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
diff --git a/include/configs/zynq.h b/include/configs/zynq.h
index 4c6e6e8..82ec826 100644
--- a/include/configs/zynq.h
+++ b/include/configs/zynq.h
@@ -60,10 +60,10 @@
/* I2C */
#if defined(CONFIG_ZYNQ_I2C0) || defined(CONFIG_ZYNQ_I2C1)
# define CONFIG_CMD_I2C
-# define CONFIG_ZYNQ_I2C
-# define CONFIG_HARD_I2C
-# define CONFIG_SYS_I2C_SPEED 100000
-# define CONFIG_SYS_I2C_SLAVE 1
+# define CONFIG_SYS_I2C
+# define CONFIG_SYS_I2C_ZYNQ
+# define CONFIG_SYS_I2C_ZYNQ_SPEED 100000
+# define CONFIG_SYS_I2C_ZYNQ_SLAVE 1
#endif
#if defined(CONFIG_ZYNQ_DCC)
diff --git a/include/fm_eth.h b/include/fm_eth.h
index 5a4fb70..98edfcf 100644
--- a/include/fm_eth.h
+++ b/include/fm_eth.h
@@ -22,6 +22,8 @@
FM1_DTSEC10,
FM1_10GEC1,
FM1_10GEC2,
+ FM1_10GEC3,
+ FM1_10GEC4,
FM2_DTSEC1,
FM2_DTSEC2,
FM2_DTSEC3,
@@ -85,6 +87,22 @@
.compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
offsetof(struct ccsr_fman, memac[n-1+8]),\
}
+
+#if (CONFIG_SYS_NUM_FM1_10GEC >= 3)
+#define FM_TGEC_INFO_INITIALIZER2(idx, n) \
+{ \
+ FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR) \
+ .index = idx, \
+ .num = n - 1, \
+ .type = FM_ETH_10G_E, \
+ .port = FM##idx##_10GEC##n, \
+ .rx_port_id = RX_PORT_10G_BASE2 + n - 3, \
+ .tx_port_id = TX_PORT_10G_BASE2 + n - 3, \
+ .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
+ offsetof(struct ccsr_fman, memac[n-1-2]),\
+}
+#endif
+
#else
#define FM_DTSEC_INFO_INITIALIZER(idx, n) \
{ \
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h b/include/fsl_ddr.h
similarity index 96%
rename from arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
rename to include/fsl_ddr.h
index e3b414e..e03f9db 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
+++ b/include/fsl_ddr.h
@@ -9,10 +9,10 @@
#ifndef FSL_DDR_MAIN_H
#define FSL_DDR_MAIN_H
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
-#include "common_timing_params.h"
+#include <common_timing_params.h>
#if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM)
/*
diff --git a/arch/powerpc/include/asm/fsl_ddr_dimm_params.h b/include/fsl_ddr_dimm_params.h
similarity index 100%
rename from arch/powerpc/include/asm/fsl_ddr_dimm_params.h
rename to include/fsl_ddr_dimm_params.h
diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h
similarity index 98%
rename from arch/powerpc/include/asm/fsl_ddr_sdram.h
rename to include/fsl_ddr_sdram.h
index 2c3c514..16cccc7 100644
--- a/arch/powerpc/include/asm/fsl_ddr_sdram.h
+++ b/include/fsl_ddr_sdram.h
@@ -36,25 +36,25 @@
#define DDR2_RTT_150_OHM 2
#define DDR2_RTT_50_OHM 3
-#if defined(CONFIG_FSL_DDR1)
+#if defined(CONFIG_SYS_FSL_DDR1)
#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (1)
typedef ddr1_spd_eeprom_t generic_spd_eeprom_t;
#ifndef CONFIG_FSL_SDRAM_TYPE
#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR1
#endif
-#elif defined(CONFIG_FSL_DDR2)
+#elif defined(CONFIG_SYS_FSL_DDR2)
#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3)
typedef ddr2_spd_eeprom_t generic_spd_eeprom_t;
#ifndef CONFIG_FSL_SDRAM_TYPE
#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR2
#endif
-#elif defined(CONFIG_FSL_DDR3)
+#elif defined(CONFIG_SYS_FSL_DDR3)
#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3) /* FIXME */
typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
#ifndef CONFIG_FSL_SDRAM_TYPE
#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR3
#endif
-#endif /* #if defined(CONFIG_FSL_DDR1) */
+#endif /* #if defined(CONFIG_SYS_FSL_DDR1) */
#define FSL_DDR_ODT_NEVER 0x0
#define FSL_DDR_ODT_CS 0x1
diff --git a/arch/powerpc/include/asm/fsl_ifc.h b/include/fsl_ifc.h
similarity index 99%
rename from arch/powerpc/include/asm/fsl_ifc.h
rename to include/fsl_ifc.h
index a945e4b..be6c107 100644
--- a/arch/powerpc/include/asm/fsl_ifc.h
+++ b/include/fsl_ifc.h
@@ -5,8 +5,8 @@
* SPDX-License-Identifier: GPL-2.0+
*/
-#ifndef __ASM_PPC_FSL_IFC_H
-#define __ASM_PPC_FSL_IFC_H
+#ifndef __FSL_IFC_H
+#define __FSL_IFC_H
#ifdef CONFIG_FSL_IFC
#include <config.h>
@@ -77,6 +77,7 @@
#define CSOR_NAND_PGS_512 0x00000000
#define CSOR_NAND_PGS_2K 0x00080000
#define CSOR_NAND_PGS_4K 0x00100000
+#define CSOR_NAND_PGS_8K 0x00180000
/* Spare region Size */
#define CSOR_NAND_SPRZ_MASK 0x0000E000
#define CSOR_NAND_SPRZ_SHIFT 13
@@ -86,6 +87,7 @@
#define CSOR_NAND_SPRZ_210 0x00006000
#define CSOR_NAND_SPRZ_218 0x00008000
#define CSOR_NAND_SPRZ_224 0x0000A000
+#define CSOR_NAND_SPRZ_CSOR_EXT 0x0000C000
/* Pages Per Block */
#define CSOR_NAND_PB_MASK 0x00000700
#define CSOR_NAND_PB_SHIFT 8
@@ -983,4 +985,4 @@
#endif /* CONFIG_FSL_IFC */
#endif /* __ASSEMBLY__ */
-#endif /* __ASM_PPC_FSL_IFC_H */
+#endif /* __FSL_IFC_H */
diff --git a/include/fsl_immap.h b/include/fsl_immap.h
new file mode 100644
index 0000000..00902ca
--- /dev/null
+++ b/include/fsl_immap.h
@@ -0,0 +1,112 @@
+/*
+ * Common internal memory map for some Freescale SoCs
+ *
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __FSL_IMMAP_H
+#define __FSL_IMMAP_H
+/*
+ * DDR memory controller registers
+ * This structure works for mpc83xx (DDR2 and DDR3), mpc85xx, mpc86xx.
+ */
+struct ccsr_ddr {
+ u32 cs0_bnds; /* Chip Select 0 Memory Bounds */
+ u8 res_04[4];
+ u32 cs1_bnds; /* Chip Select 1 Memory Bounds */
+ u8 res_0c[4];
+ u32 cs2_bnds; /* Chip Select 2 Memory Bounds */
+ u8 res_14[4];
+ u32 cs3_bnds; /* Chip Select 3 Memory Bounds */
+ u8 res_1c[100];
+ u32 cs0_config; /* Chip Select Configuration */
+ u32 cs1_config; /* Chip Select Configuration */
+ u32 cs2_config; /* Chip Select Configuration */
+ u32 cs3_config; /* Chip Select Configuration */
+ u8 res_90[48];
+ u32 cs0_config_2; /* Chip Select Configuration 2 */
+ u32 cs1_config_2; /* Chip Select Configuration 2 */
+ u32 cs2_config_2; /* Chip Select Configuration 2 */
+ u32 cs3_config_2; /* Chip Select Configuration 2 */
+ u8 res_d0[48];
+ u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */
+ u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */
+ u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */
+ u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */
+ u32 sdram_cfg; /* SDRAM Control Configuration */
+ u32 sdram_cfg_2; /* SDRAM Control Configuration 2 */
+ u32 sdram_mode; /* SDRAM Mode Configuration */
+ u32 sdram_mode_2; /* SDRAM Mode Configuration 2 */
+ u32 sdram_md_cntl; /* SDRAM Mode Control */
+ u32 sdram_interval; /* SDRAM Interval Configuration */
+ u32 sdram_data_init; /* SDRAM Data initialization */
+ u8 res_12c[4];
+ u32 sdram_clk_cntl; /* SDRAM Clock Control */
+ u8 res_134[20];
+ u32 init_addr; /* training init addr */
+ u32 init_ext_addr; /* training init extended addr */
+ u8 res_150[16];
+ u32 timing_cfg_4; /* SDRAM Timing Configuration 4 */
+ u32 timing_cfg_5; /* SDRAM Timing Configuration 5 */
+ u8 reg_168[8];
+ u32 ddr_zq_cntl; /* ZQ calibration control*/
+ u32 ddr_wrlvl_cntl; /* write leveling control*/
+ u8 reg_178[4];
+ u32 ddr_sr_cntr; /* self refresh counter */
+ u32 ddr_sdram_rcw_1; /* Control Words 1 */
+ u32 ddr_sdram_rcw_2; /* Control Words 2 */
+ u8 reg_188[8];
+ u32 ddr_wrlvl_cntl_2; /* write leveling control 2 */
+ u32 ddr_wrlvl_cntl_3; /* write leveling control 3 */
+ u8 res_198[104];
+ u32 sdram_mode_3; /* SDRAM Mode Configuration 3 */
+ u32 sdram_mode_4; /* SDRAM Mode Configuration 4 */
+ u32 sdram_mode_5; /* SDRAM Mode Configuration 5 */
+ u32 sdram_mode_6; /* SDRAM Mode Configuration 6 */
+ u32 sdram_mode_7; /* SDRAM Mode Configuration 7 */
+ u32 sdram_mode_8; /* SDRAM Mode Configuration 8 */
+ u8 res_218[0x908];
+ u32 ddr_dsr1; /* Debug Status 1 */
+ u32 ddr_dsr2; /* Debug Status 2 */
+ u32 ddr_cdr1; /* Control Driver 1 */
+ u32 ddr_cdr2; /* Control Driver 2 */
+ u8 res_b30[200];
+ u32 ip_rev1; /* IP Block Revision 1 */
+ u32 ip_rev2; /* IP Block Revision 2 */
+ u32 eor; /* Enhanced Optimization Register */
+ u8 res_c04[252];
+ u32 mtcr; /* Memory Test Control Register */
+ u8 res_d04[28];
+ u32 mtp1; /* Memory Test Pattern 1 */
+ u32 mtp2; /* Memory Test Pattern 2 */
+ u32 mtp3; /* Memory Test Pattern 3 */
+ u32 mtp4; /* Memory Test Pattern 4 */
+ u32 mtp5; /* Memory Test Pattern 5 */
+ u32 mtp6; /* Memory Test Pattern 6 */
+ u32 mtp7; /* Memory Test Pattern 7 */
+ u32 mtp8; /* Memory Test Pattern 8 */
+ u32 mtp9; /* Memory Test Pattern 9 */
+ u32 mtp10; /* Memory Test Pattern 10 */
+ u8 res_d48[184];
+ u32 data_err_inject_hi; /* Data Path Err Injection Mask High */
+ u32 data_err_inject_lo; /* Data Path Err Injection Mask Low */
+ u32 ecc_err_inject; /* Data Path Err Injection Mask ECC */
+ u8 res_e0c[20];
+ u32 capture_data_hi; /* Data Path Read Capture High */
+ u32 capture_data_lo; /* Data Path Read Capture Low */
+ u32 capture_ecc; /* Data Path Read Capture ECC */
+ u8 res_e2c[20];
+ u32 err_detect; /* Error Detect */
+ u32 err_disable; /* Error Disable */
+ u32 err_int_en;
+ u32 capture_attributes; /* Error Attrs Capture */
+ u32 capture_address; /* Error Addr Capture */
+ u32 capture_ext_address; /* Error Extended Addr Capture */
+ u32 err_sbe; /* Single-Bit ECC Error Management */
+ u8 res_e5c[164];
+ u32 debug[32]; /* debug_1 to debug_32 */
+ u8 res_f80[128];
+};
+#endif /* __FSL_IMMAP_H */
diff --git a/include/fsl_mdio.h b/include/fsl_mdio.h
index 9c0b762..b58713d 100644
--- a/include/fsl_mdio.h
+++ b/include/fsl_mdio.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2009-2012 Freescale Semiconductor, Inc.
+ * Copyright 2009-2012, 2013 Freescale Semiconductor, Inc.
* Jun-jie Zhang <b18070@freescale.com>
* Mingkai Hu <Mingkai.hu@freescale.com>
*
@@ -31,9 +31,9 @@
#define MIIMIND_BUSY 0x00000001
#define MIIMIND_NOTVALID 0x00000004
-void tsec_local_mdio_write(struct tsec_mii_mng *phyregs, int port_addr,
+void tsec_local_mdio_write(struct tsec_mii_mng __iomem *phyregs, int port_addr,
int dev_addr, int reg, int value);
-int tsec_local_mdio_read(struct tsec_mii_mng *phyregs, int port_addr,
+int tsec_local_mdio_read(struct tsec_mii_mng __iomem *phyregs, int port_addr,
int dev_addr, int regnum);
int tsec_phy_read(struct mii_dev *bus, int addr, int dev_addr, int regnum);
int tsec_phy_write(struct mii_dev *bus, int addr, int dev_addr, int regnum,
@@ -44,7 +44,7 @@
int regnum);
struct fsl_pq_mdio_info {
- struct tsec_mii_mng *regs;
+ struct tsec_mii_mng __iomem *regs;
char *name;
};
int fsl_pq_mdio_init(bd_t *bis, struct fsl_pq_mdio_info *info);
diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h
index 6f44abd..a65b681 100644
--- a/include/linux/mtd/mtd.h
+++ b/include/linux/mtd/mtd.h
@@ -96,6 +96,29 @@
uint8_t *oobbuf;
};
+#ifdef CONFIG_SYS_NAND_MAX_OOBFREE
+#define MTD_MAX_OOBFREE_ENTRIES_LARGE CONFIG_SYS_NAND_MAX_OOBFREE
+#else
+#define MTD_MAX_OOBFREE_ENTRIES_LARGE 32
+#endif
+
+#ifdef CONFIG_SYS_NAND_MAX_ECCPOS
+#define MTD_MAX_ECCPOS_ENTRIES_LARGE CONFIG_SYS_NAND_MAX_ECCPOS
+#else
+#define MTD_MAX_ECCPOS_ENTRIES_LARGE 640
+#endif
+
+/*
+ * ECC layout control structure. Exported to userspace for
+ * diagnosis and to allow creation of raw images
+ */
+struct nand_ecclayout {
+ uint32_t eccbytes;
+ uint32_t eccpos[MTD_MAX_ECCPOS_ENTRIES_LARGE];
+ uint32_t oobavail;
+ struct nand_oobfree oobfree[MTD_MAX_OOBFREE_ENTRIES_LARGE];
+};
+
struct mtd_info {
u_char type;
u_int32_t flags;
diff --git a/include/micrel.h b/include/micrel.h
index e1c62d8..04c9ecf 100644
--- a/include/micrel.h
+++ b/include/micrel.h
@@ -15,6 +15,11 @@
#define MII_KSZ9031_MOD_DATA_POST_INC_RW 0x8000
#define MII_KSZ9031_MOD_DATA_POST_INC_W 0xC000
+#define MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW 0x4
+#define MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW 0x5
+#define MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW 0x6
+#define MII_KSZ9031_EXT_RGMII_CLOCK_SKEW 0x8
+
struct phy_device;
int ksz9021_phy_extended_write(struct phy_device *phydev, int regnum, u16 val);
int ksz9021_phy_extended_read(struct phy_device *phydev, int regnum);
diff --git a/include/msc01.h b/include/msc01.h
new file mode 100644
index 0000000..37cf963
--- /dev/null
+++ b/include/msc01.h
@@ -0,0 +1,135 @@
+/*
+ * Copyright (C) 2013 Imagination Technologies
+ * Author: Paul Burton <paul.burton@imgtec.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __MSC01_H__
+#define __MSC01_H__
+
+/*
+ * Bus Interface Unit
+ */
+
+#define MSC01_BIU_IP1BAS1L_OFS 0x0208
+#define MSC01_BIU_IP1MSK1L_OFS 0x0218
+#define MSC01_BIU_IP1BAS2L_OFS 0x0248
+#define MSC01_BIU_IP1MSK2L_OFS 0x0258
+#define MSC01_BIU_IP2BAS1L_OFS 0x0288
+#define MSC01_BIU_IP2MSK1L_OFS 0x0298
+#define MSC01_BIU_IP2BAS2L_OFS 0x02c8
+#define MSC01_BIU_IP2MSK2L_OFS 0x02d8
+#define MSC01_BIU_IP3BAS1L_OFS 0x0308
+#define MSC01_BIU_IP3MSK1L_OFS 0x0318
+#define MSC01_BIU_IP3BAS2L_OFS 0x0348
+#define MSC01_BIU_IP3MSK2L_OFS 0x0358
+#define MSC01_BIU_MCBAS1L_OFS 0x0388
+#define MSC01_BIU_MCMSK1L_OFS 0x0398
+#define MSC01_BIU_MCBAS2L_OFS 0x03c8
+#define MSC01_BIU_MCMSK2L_OFS 0x03d8
+
+/*
+ * PCI Bridge
+ */
+
+#define MSC01_PCI_SC2PMBASL_OFS 0x0208
+#define MSC01_PCI_SC2PMMSKL_OFS 0x0218
+#define MSC01_PCI_SC2PMMAPL_OFS 0x0228
+#define MSC01_PCI_SC2PIOBASL_OFS 0x0248
+#define MSC01_PCI_SC2PIOMSKL_OFS 0x0258
+#define MSC01_PCI_SC2PIOMAPL_OFS 0x0268
+#define MSC01_PCI_P2SCMSKL_OFS 0x0308
+#define MSC01_PCI_P2SCMAPL_OFS 0x0318
+#define MSC01_PCI_INTSTAT_OFS 0x0608
+#define MSC01_PCI_CFGADDR_OFS 0x0610
+#define MSC01_PCI_CFGDATA_OFS 0x0618
+#define MSC01_PCI_HEAD0_OFS 0x2000
+#define MSC01_PCI_HEAD1_OFS 0x2008
+#define MSC01_PCI_HEAD2_OFS 0x2010
+#define MSC01_PCI_HEAD3_OFS 0x2018
+#define MSC01_PCI_HEAD4_OFS 0x2020
+#define MSC01_PCI_HEAD5_OFS 0x2028
+#define MSC01_PCI_HEAD6_OFS 0x2030
+#define MSC01_PCI_HEAD7_OFS 0x2038
+#define MSC01_PCI_HEAD8_OFS 0x2040
+#define MSC01_PCI_HEAD9_OFS 0x2048
+#define MSC01_PCI_HEAD10_OFS 0x2050
+#define MSC01_PCI_HEAD11_OFS 0x2058
+#define MSC01_PCI_HEAD12_OFS 0x2060
+#define MSC01_PCI_HEAD13_OFS 0x2068
+#define MSC01_PCI_HEAD14_OFS 0x2070
+#define MSC01_PCI_HEAD15_OFS 0x2078
+#define MSC01_PCI_BAR0_OFS 0x2220
+#define MSC01_PCI_CFG_OFS 0x2380
+#define MSC01_PCI_SWAP_OFS 0x2388
+
+#define MSC01_PCI_SC2PMMSKL_MSK_MSK 0xff000000
+#define MSC01_PCI_SC2PIOMSKL_MSK_MSK 0xff000000
+
+#define MSC01_PCI_INTSTAT_TA_SHF 6
+#define MSC01_PCI_INTSTAT_TA_MSK (0x1 << MSC01_PCI_INTSTAT_TA_SHF)
+#define MSC01_PCI_INTSTAT_MA_SHF 7
+#define MSC01_PCI_INTSTAT_MA_MSK (0x1 << MSC01_PCI_INTSTAT_MA_SHF)
+
+#define MSC01_PCI_CFGADDR_BNUM_SHF 16
+#define MSC01_PCI_CFGADDR_BNUM_MSK (0xff << MSC01_PCI_CFGADDR_BNUM_SHF)
+#define MSC01_PCI_CFGADDR_DNUM_SHF 11
+#define MSC01_PCI_CFGADDR_DNUM_MSK (0x1f << MSC01_PCI_CFGADDR_DNUM_SHF)
+#define MSC01_PCI_CFGADDR_FNUM_SHF 8
+#define MSC01_PCI_CFGADDR_FNUM_MSK (0x3 << MSC01_PCI_CFGADDR_FNUM_SHF)
+#define MSC01_PCI_CFGADDR_RNUM_SHF 2
+#define MSC01_PCI_CFGADDR_RNUM_MSK (0x3f << MSC01_PCI_CFGADDR_RNUM_SHF)
+
+#define MSC01_PCI_HEAD0_VENDORID_SHF 0
+#define MSC01_PCI_HEAD0_DEVICEID_SHF 16
+
+#define MSC01_PCI_HEAD2_REV_SHF 0
+#define MSC01_PCI_HEAD2_CLASS_SHF 16
+
+#define MSC01_PCI_CFG_EN_SHF 15
+#define MSC01_PCI_CFG_EN_MSK (0x1 << MSC01_PCI_CFG_EN_SHF)
+#define MSC01_PCI_CFG_G_SHF 16
+#define MSC01_PCI_CFG_G_MSK (0x1 << MSC01_PCI_CFG_G_SHF)
+#define MSC01_PCI_CFG_RA_SHF 17
+#define MSC01_PCI_CFG_RA_MSK (0x1 << MSC01_PCI_CFG_RA_SHF)
+
+#define MSC01_PCI_SWAP_BAR0_BSWAP_SHF 0
+#define MSC01_PCI_SWAP_IO_BSWAP_SHF 18
+
+/*
+ * Peripheral Bus Controller
+ */
+
+#define MSC01_PBC_CLKCFG_OFS 0x0100
+#define MSC01_PBC_CS0CFG_OFS 0x0400
+#define MSC01_PBC_CS0TIM_OFS 0x0500
+#define MSC01_PBC_CS0RW_OFS 0x0600
+
+#define MSC01_PBC_CLKCFG_SHF 0
+#define MSC01_PBC_CLKCFG_MSK (0x1f << MSC01_PBC_CLKCFG_SHF)
+
+#define MSC01_PBC_CS0CFG_WS_SHF 0
+#define MSC01_PBC_CS0CFG_WS_MSK (0x1f << MSC01_PBC_CS0CFG_WS_SHF)
+#define MSC01_PBC_CS0CFG_WSIDLE_SHF 8
+#define MSC01_PBC_CS0CFG_WSIDLE_MSK (0x1f << MSC01_PBC_CS0CFG_WSIDLE_SHF)
+#define MSC01_PBC_CS0CFG_DTYP_SHF 16
+#define MSC01_PBC_CS0CFG_DTYP_MSK (0x3 << MSC01_PBC_CS0CFG_DTYP_SHF)
+#define MSC01_PBC_CS0CFG_ADM_SHF 20
+#define MSC01_PBC_CS0CFG_ADM_MSK (0x1 << MSC01_PBC_CS0CFG_ADM_SHF)
+
+#define MSC01_PBC_CS0TIM_CAT_SHF 0
+#define MSC01_PBC_CS0TIM_CAT_MSK (0x1f << MSC01_PBC_CS0TIM_CAT_SHF)
+#define MSC01_PBC_CS0TIM_CDT_SHF 8
+#define MSC01_PBC_CS0TIM_CDT_MSK (0x1f << MSC01_PBC_CS0TIM_CDT_SHF)
+
+#define MSC01_PBC_CS0RW_WAT_SHF 0
+#define MSC01_PBC_CS0RW_WAT_MSK (0x1f << MSC01_PBC_CS0RW_WAT_SHF)
+#define MSC01_PBC_CS0RW_WDT_SHF 8
+#define MSC01_PBC_CS0RW_WDT_MSK (0x1f << MSC01_PBC_CS0RW_WDT_SHF)
+#define MSC01_PBC_CS0RW_RAT_SHF 16
+#define MSC01_PBC_CS0RW_RAT_MSK (0x1f << MSC01_PBC_CS0RW_RAT_SHF)
+#define MSC01_PBC_CS0RW_RDT_SHF 24
+#define MSC01_PBC_CS0RW_RDT_MSK (0x1f << MSC01_PBC_CS0RW_RDT_SHF)
+
+#endif /* __MSC01_H__ */
diff --git a/include/mtd/mtd-abi.h b/include/mtd/mtd-abi.h
index d51c1ab..ac3c298 100644
--- a/include/mtd/mtd-abi.h
+++ b/include/mtd/mtd-abi.h
@@ -155,18 +155,6 @@
uint32_t length;
};
-#define MTD_MAX_OOBFREE_ENTRIES 8
-/*
- * ECC layout control structure. Exported to userspace for
- * diagnosis and to allow creation of raw images
- */
-struct nand_ecclayout {
- uint32_t eccbytes;
- uint32_t eccpos[128];
- uint32_t oobavail;
- struct nand_oobfree oobfree[MTD_MAX_OOBFREE_ENTRIES];
-};
-
/**
* struct mtd_ecc_stats - error correction stats
*
diff --git a/include/net.h b/include/net.h
index 5aedc17..0802fad 100644
--- a/include/net.h
+++ b/include/net.h
@@ -89,7 +89,7 @@
int (*recv) (struct eth_device *);
void (*halt) (struct eth_device *);
#ifdef CONFIG_MCAST_TFTP
- int (*mcast) (struct eth_device *, u32 ip, u8 set);
+ int (*mcast) (struct eth_device *, const u8 *enetaddr, u8 set);
#endif
int (*write_hwaddr) (struct eth_device *);
struct eth_device *next;
diff --git a/include/os.h b/include/os.h
index 8665f70..950433d 100644
--- a/include/os.h
+++ b/include/os.h
@@ -11,6 +11,8 @@
#ifndef __OS_H__
#define __OS_H__
+#include <linux/types.h>
+
struct sandbox_state;
/**
@@ -116,7 +118,7 @@
*
* \return A monotonic increasing time scaled in nano seconds
*/
-u64 os_get_nsec(void);
+uint64_t os_get_nsec(void);
/**
* Parse arguments and update sandbox state.
diff --git a/include/pci.h b/include/pci.h
index d462479..461f17c 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -417,6 +417,8 @@
#include <pci_ids.h>
+#ifndef __ASSEMBLY__
+
#ifdef CONFIG_SYS_PCI_64BIT
typedef u64 pci_addr_t;
typedef u64 pci_size_t;
@@ -667,4 +669,6 @@
#ifdef CONFIG_MPC85xx
extern void pci_mpc85xx_init (struct pci_controller *hose);
#endif
-#endif /* _PCI_H */
+
+#endif /* __ASSEMBLY__ */
+#endif /* _PCI_H */
diff --git a/include/pci_ids.h b/include/pci_ids.h
index 2c6dfd4..6bab677 100644
--- a/include/pci_ids.h
+++ b/include/pci_ids.h
@@ -2170,6 +2170,9 @@
#define PCI_DEVICE_ID_ENE_720 0x1421
#define PCI_DEVICE_ID_ENE_722 0x1422
+#define PCI_VENDOR_ID_MIPS 0x153f
+#define PCI_DEVICE_ID_MIPS_MSC01 0x0001
+
#define PCI_SUBVENDOR_ID_PERLE 0x155f
#define PCI_SUBDEVICE_ID_PCI_RAS4 0xf001
#define PCI_SUBDEVICE_ID_PCI_RAS8 0xf010
diff --git a/include/pci_msc01.h b/include/pci_msc01.h
new file mode 100644
index 0000000..54945a7
--- /dev/null
+++ b/include/pci_msc01.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2013 Imagination Technologies
+ * Author: Paul Burton <paul.burton@imgtec.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __PCI_MSC01_H__
+#define __PCI_MSC01_H__
+
+extern void msc01_pci_init(void *base, unsigned long sys_bus,
+ unsigned long sys_phys, unsigned long sys_size,
+ unsigned long mem_bus, unsigned long mem_phys,
+ unsigned long mem_size, unsigned long io_bus,
+ unsigned long io_phys, unsigned long io_size);
+
+#endif /* __PCI_MSC01_H__ */
diff --git a/include/phy.h b/include/phy.h
index f0f522a..1f22fa1 100644
--- a/include/phy.h
+++ b/include/phy.h
@@ -125,6 +125,9 @@
/* Called when bringing down the controller */
int (*shutdown)(struct phy_device *phydev);
+ int (*readext)(struct phy_device *phydev, int addr, int devad, int reg);
+ int (*writeext)(struct phy_device *phydev, int addr, int devad, int reg,
+ u16 val);
struct list_head list;
};
@@ -160,6 +163,14 @@
u32 flags;
};
+struct fixed_link {
+ int phy_id;
+ int duplex;
+ int link_speed;
+ int pause;
+ int asym_pause;
+};
+
static inline int phy_read(struct phy_device *phydev, int devad, int regnum)
{
struct mii_dev *bus = phydev->bus;
diff --git a/include/scf0403_lcd.h b/include/scf0403_lcd.h
new file mode 100644
index 0000000..d71896b
--- /dev/null
+++ b/include/scf0403_lcd.h
@@ -0,0 +1,11 @@
+/*
+ * Copyright (c) 2013, Compulab Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef SCF0403_LCD_H_
+#define SCF0403_LCD_H_
+
+int scf0403_init(int reset_gpio);
+
+#endif
diff --git a/include/spi.h b/include/spi.h
index ad9248b..e2563c9 100644
--- a/include/spi.h
+++ b/include/spi.h
@@ -29,10 +29,13 @@
#define SPI_XFER_END 0x02 /* Deassert CS after transfer */
#define SPI_XFER_MMAP 0x08 /* Memory Mapped start */
#define SPI_XFER_MMAP_END 0x10 /* Memory Mapped End */
+#define SPI_XFER_ONCE (SPI_XFER_BEGIN | SPI_XFER_END)
/* Header byte that marks the start of the message */
#define SPI_PREAMBLE_END_BYTE 0xec
+#define SPI_DEFAULT_WORDLEN 8
+
/**
* struct spi_slave - Representation of a SPI slave
*
@@ -40,6 +43,7 @@
*
* @bus: ID of the bus that the slave is attached to.
* @cs: ID of the chip select connected to the slave.
+ * @wordlen: Size of SPI word in number of bits
* @max_write_size: If non-zero, the maximum number of bytes which can
* be written at once, excluding command bytes.
* @memory_map: Address of read-only SPI flash access.
@@ -47,6 +51,7 @@
struct spi_slave {
unsigned int bus;
unsigned int cs;
+ unsigned int wordlen;
unsigned int max_write_size;
void *memory_map;
};
@@ -153,6 +158,18 @@
void spi_release_bus(struct spi_slave *slave);
/**
+ * Set the word length for SPI transactions
+ *
+ * Set the word length (number of bits per word) for SPI transactions.
+ *
+ * @slave: The SPI slave
+ * @wordlen: The number of bits in a word
+ *
+ * Returns: 0 on success, -1 on failure.
+ */
+int spi_set_wordlen(struct spi_slave *slave, unsigned int wordlen);
+
+/**
* SPI transfer
*
* This writes "bitlen" bits out the SPI MOSI port and simultaneously clocks
diff --git a/include/tsec.h b/include/tsec.h
index f0f3d4d..1046426 100644
--- a/include/tsec.h
+++ b/include/tsec.h
@@ -7,7 +7,7 @@
* terms of the GNU Public License, Version 2, incorporated
* herein by reference.
*
- * Copyright 2004, 2007, 2009, 2011 Freescale Semiconductor, Inc.
+ * Copyright 2004, 2007, 2009, 2011, 2013 Freescale Semiconductor, Inc.
* (C) Copyright 2003, Motorola, Inc.
* maintained by Xianghua Xiao (x.xiao@motorola.com)
* author Andy Fleming
@@ -27,13 +27,26 @@
#define CONFIG_SYS_MDIO_BASE_ADDR (MDIO_BASE_ADDR + 0x520)
+#define TSEC_GET_REGS(num, offset) \
+ (struct tsec __iomem *)\
+ (TSEC_BASE_ADDR + (((num) - 1) * (offset)))
+
+#define TSEC_GET_REGS_BASE(num) \
+ TSEC_GET_REGS((num), TSEC_SIZE)
+
+#define TSEC_GET_MDIO_REGS(num, offset) \
+ (struct tsec_mii_mng __iomem *)\
+ (CONFIG_SYS_MDIO_BASE_ADDR + ((num) - 1) * (offset))
+
+#define TSEC_GET_MDIO_REGS_BASE(num) \
+ TSEC_GET_MDIO_REGS((num), TSEC_MDIO_OFFSET)
+
#define DEFAULT_MII_NAME "FSL_MDIO"
#define STD_TSEC_INFO(num) \
{ \
- .regs = (tsec_t *)(TSEC_BASE_ADDR + ((num - 1) * TSEC_SIZE)), \
- .miiregs_sgmii = (struct tsec_mii_mng *)(CONFIG_SYS_MDIO_BASE_ADDR \
- + (num - 1) * TSEC_MDIO_OFFSET), \
+ .regs = TSEC_GET_REGS_BASE(num), \
+ .miiregs_sgmii = TSEC_GET_MDIO_REGS_BASE(num), \
.devname = CONFIG_TSEC##num##_NAME, \
.phyaddr = TSEC##num##_PHY_ADDR, \
.flags = TSEC##num##_FLAGS, \
@@ -42,9 +55,8 @@
#define SET_STD_TSEC_INFO(x, num) \
{ \
- x.regs = (tsec_t *)(TSEC_BASE_ADDR + ((num - 1) * TSEC_SIZE)); \
- x.miiregs_sgmii = (struct tsec_mii_mng *)(CONFIG_SYS_MDIO_BASE_ADDR \
- + (num - 1) * TSEC_MDIO_OFFSET); \
+ x.regs = TSEC_GET_REGS_BASE(num); \
+ x.miiregs_sgmii = TSEC_GET_MDIO_REGS_BASE(num); \
x.devname = CONFIG_TSEC##num##_NAME; \
x.phyaddr = TSEC##num##_PHY_ADDR; \
x.flags = TSEC##num##_FLAGS;\
@@ -186,195 +198,190 @@
#define RXBD_TRUNCATED 0x0001
#define RXBD_STATS 0x003f
-typedef struct txbd8
-{
- ushort status; /* Status Fields */
- ushort length; /* Buffer length */
- uint bufPtr; /* Buffer Pointer */
-} txbd8_t;
+struct txbd8 {
+ uint16_t status; /* Status Fields */
+ uint16_t length; /* Buffer length */
+ uint32_t bufptr; /* Buffer Pointer */
+};
-typedef struct rxbd8
-{
- ushort status; /* Status Fields */
- ushort length; /* Buffer Length */
- uint bufPtr; /* Buffer Pointer */
-} rxbd8_t;
+struct rxbd8 {
+ uint16_t status; /* Status Fields */
+ uint16_t length; /* Buffer Length */
+ uint32_t bufptr; /* Buffer Pointer */
+};
-typedef struct rmon_mib
-{
+struct tsec_rmon_mib {
/* Transmit and Receive Counters */
- uint tr64; /* Transmit and Receive 64-byte Frame Counter */
- uint tr127; /* Transmit and Receive 65-127 byte Frame Counter */
- uint tr255; /* Transmit and Receive 128-255 byte Frame Counter */
- uint tr511; /* Transmit and Receive 256-511 byte Frame Counter */
- uint tr1k; /* Transmit and Receive 512-1023 byte Frame Counter */
- uint trmax; /* Transmit and Receive 1024-1518 byte Frame Counter */
- uint trmgv; /* Transmit and Receive 1519-1522 byte Good VLAN Frame */
+ u32 tr64; /* Tx/Rx 64-byte Frame Counter */
+ u32 tr127; /* Tx/Rx 65-127 byte Frame Counter */
+ u32 tr255; /* Tx/Rx 128-255 byte Frame Counter */
+ u32 tr511; /* Tx/Rx 256-511 byte Frame Counter */
+ u32 tr1k; /* Tx/Rx 512-1023 byte Frame Counter */
+ u32 trmax; /* Tx/Rx 1024-1518 byte Frame Counter */
+ u32 trmgv; /* Tx/Rx 1519-1522 byte Good VLAN Frame */
/* Receive Counters */
- uint rbyt; /* Receive Byte Counter */
- uint rpkt; /* Receive Packet Counter */
- uint rfcs; /* Receive FCS Error Counter */
- uint rmca; /* Receive Multicast Packet (Counter) */
- uint rbca; /* Receive Broadcast Packet */
- uint rxcf; /* Receive Control Frame Packet */
- uint rxpf; /* Receive Pause Frame Packet */
- uint rxuo; /* Receive Unknown OP Code */
- uint raln; /* Receive Alignment Error */
- uint rflr; /* Receive Frame Length Error */
- uint rcde; /* Receive Code Error */
- uint rcse; /* Receive Carrier Sense Error */
- uint rund; /* Receive Undersize Packet */
- uint rovr; /* Receive Oversize Packet */
- uint rfrg; /* Receive Fragments */
- uint rjbr; /* Receive Jabber */
- uint rdrp; /* Receive Drop */
+ u32 rbyt; /* Receive Byte Counter */
+ u32 rpkt; /* Receive Packet Counter */
+ u32 rfcs; /* Receive FCS Error Counter */
+ u32 rmca; /* Receive Multicast Packet (Counter) */
+ u32 rbca; /* Receive Broadcast Packet */
+ u32 rxcf; /* Receive Control Frame Packet */
+ u32 rxpf; /* Receive Pause Frame Packet */
+ u32 rxuo; /* Receive Unknown OP Code */
+ u32 raln; /* Receive Alignment Error */
+ u32 rflr; /* Receive Frame Length Error */
+ u32 rcde; /* Receive Code Error */
+ u32 rcse; /* Receive Carrier Sense Error */
+ u32 rund; /* Receive Undersize Packet */
+ u32 rovr; /* Receive Oversize Packet */
+ u32 rfrg; /* Receive Fragments */
+ u32 rjbr; /* Receive Jabber */
+ u32 rdrp; /* Receive Drop */
/* Transmit Counters */
- uint tbyt; /* Transmit Byte Counter */
- uint tpkt; /* Transmit Packet */
- uint tmca; /* Transmit Multicast Packet */
- uint tbca; /* Transmit Broadcast Packet */
- uint txpf; /* Transmit Pause Control Frame */
- uint tdfr; /* Transmit Deferral Packet */
- uint tedf; /* Transmit Excessive Deferral Packet */
- uint tscl; /* Transmit Single Collision Packet */
+ u32 tbyt; /* Transmit Byte Counter */
+ u32 tpkt; /* Transmit Packet */
+ u32 tmca; /* Transmit Multicast Packet */
+ u32 tbca; /* Transmit Broadcast Packet */
+ u32 txpf; /* Transmit Pause Control Frame */
+ u32 tdfr; /* Transmit Deferral Packet */
+ u32 tedf; /* Transmit Excessive Deferral Packet */
+ u32 tscl; /* Transmit Single Collision Packet */
/* (0x2_n700) */
- uint tmcl; /* Transmit Multiple Collision Packet */
- uint tlcl; /* Transmit Late Collision Packet */
- uint txcl; /* Transmit Excessive Collision Packet */
- uint tncl; /* Transmit Total Collision */
+ u32 tmcl; /* Transmit Multiple Collision Packet */
+ u32 tlcl; /* Transmit Late Collision Packet */
+ u32 txcl; /* Transmit Excessive Collision Packet */
+ u32 tncl; /* Transmit Total Collision */
- uint res2;
+ u32 res2;
- uint tdrp; /* Transmit Drop Frame */
- uint tjbr; /* Transmit Jabber Frame */
- uint tfcs; /* Transmit FCS Error */
- uint txcf; /* Transmit Control Frame */
- uint tovr; /* Transmit Oversize Frame */
- uint tund; /* Transmit Undersize Frame */
- uint tfrg; /* Transmit Fragments Frame */
+ u32 tdrp; /* Transmit Drop Frame */
+ u32 tjbr; /* Transmit Jabber Frame */
+ u32 tfcs; /* Transmit FCS Error */
+ u32 txcf; /* Transmit Control Frame */
+ u32 tovr; /* Transmit Oversize Frame */
+ u32 tund; /* Transmit Undersize Frame */
+ u32 tfrg; /* Transmit Fragments Frame */
/* General Registers */
- uint car1; /* Carry Register One */
- uint car2; /* Carry Register Two */
- uint cam1; /* Carry Register One Mask */
- uint cam2; /* Carry Register Two Mask */
-} rmon_mib_t;
+ u32 car1; /* Carry Register One */
+ u32 car2; /* Carry Register Two */
+ u32 cam1; /* Carry Register One Mask */
+ u32 cam2; /* Carry Register Two Mask */
+};
-typedef struct tsec_hash_regs
-{
- uint iaddr0; /* Individual Address Register 0 */
- uint iaddr1; /* Individual Address Register 1 */
- uint iaddr2; /* Individual Address Register 2 */
- uint iaddr3; /* Individual Address Register 3 */
- uint iaddr4; /* Individual Address Register 4 */
- uint iaddr5; /* Individual Address Register 5 */
- uint iaddr6; /* Individual Address Register 6 */
- uint iaddr7; /* Individual Address Register 7 */
- uint res1[24];
- uint gaddr0; /* Group Address Register 0 */
- uint gaddr1; /* Group Address Register 1 */
- uint gaddr2; /* Group Address Register 2 */
- uint gaddr3; /* Group Address Register 3 */
- uint gaddr4; /* Group Address Register 4 */
- uint gaddr5; /* Group Address Register 5 */
- uint gaddr6; /* Group Address Register 6 */
- uint gaddr7; /* Group Address Register 7 */
- uint res2[24];
-} tsec_hash_t;
+struct tsec_hash_regs {
+ u32 iaddr0; /* Individual Address Register 0 */
+ u32 iaddr1; /* Individual Address Register 1 */
+ u32 iaddr2; /* Individual Address Register 2 */
+ u32 iaddr3; /* Individual Address Register 3 */
+ u32 iaddr4; /* Individual Address Register 4 */
+ u32 iaddr5; /* Individual Address Register 5 */
+ u32 iaddr6; /* Individual Address Register 6 */
+ u32 iaddr7; /* Individual Address Register 7 */
+ u32 res1[24];
+ u32 gaddr0; /* Group Address Register 0 */
+ u32 gaddr1; /* Group Address Register 1 */
+ u32 gaddr2; /* Group Address Register 2 */
+ u32 gaddr3; /* Group Address Register 3 */
+ u32 gaddr4; /* Group Address Register 4 */
+ u32 gaddr5; /* Group Address Register 5 */
+ u32 gaddr6; /* Group Address Register 6 */
+ u32 gaddr7; /* Group Address Register 7 */
+ u32 res2[24];
+};
-typedef struct tsec
-{
+struct tsec {
/* General Control and Status Registers (0x2_n000) */
- uint res000[4];
+ u32 res000[4];
- uint ievent; /* Interrupt Event */
- uint imask; /* Interrupt Mask */
- uint edis; /* Error Disabled */
- uint res01c;
- uint ecntrl; /* Ethernet Control */
- uint minflr; /* Minimum Frame Length */
- uint ptv; /* Pause Time Value */
- uint dmactrl; /* DMA Control */
- uint tbipa; /* TBI PHY Address */
+ u32 ievent; /* Interrupt Event */
+ u32 imask; /* Interrupt Mask */
+ u32 edis; /* Error Disabled */
+ u32 res01c;
+ u32 ecntrl; /* Ethernet Control */
+ u32 minflr; /* Minimum Frame Length */
+ u32 ptv; /* Pause Time Value */
+ u32 dmactrl; /* DMA Control */
+ u32 tbipa; /* TBI PHY Address */
- uint res034[3];
- uint res040[48];
+ u32 res034[3];
+ u32 res040[48];
/* Transmit Control and Status Registers (0x2_n100) */
- uint tctrl; /* Transmit Control */
- uint tstat; /* Transmit Status */
- uint res108;
- uint tbdlen; /* Tx BD Data Length */
- uint res110[5];
- uint ctbptr; /* Current TxBD Pointer */
- uint res128[23];
- uint tbptr; /* TxBD Pointer */
- uint res188[30];
+ u32 tctrl; /* Transmit Control */
+ u32 tstat; /* Transmit Status */
+ u32 res108;
+ u32 tbdlen; /* Tx BD Data Length */
+ u32 res110[5];
+ u32 ctbptr; /* Current TxBD Pointer */
+ u32 res128[23];
+ u32 tbptr; /* TxBD Pointer */
+ u32 res188[30];
/* (0x2_n200) */
- uint res200;
- uint tbase; /* TxBD Base Address */
- uint res208[42];
- uint ostbd; /* Out of Sequence TxBD */
- uint ostbdp; /* Out of Sequence Tx Data Buffer Pointer */
- uint res2b8[18];
+ u32 res200;
+ u32 tbase; /* TxBD Base Address */
+ u32 res208[42];
+ u32 ostbd; /* Out of Sequence TxBD */
+ u32 ostbdp; /* Out of Sequence Tx Data Buffer Pointer */
+ u32 res2b8[18];
/* Receive Control and Status Registers (0x2_n300) */
- uint rctrl; /* Receive Control */
- uint rstat; /* Receive Status */
- uint res308;
- uint rbdlen; /* RxBD Data Length */
- uint res310[4];
- uint res320;
- uint crbptr; /* Current Receive Buffer Pointer */
- uint res328[6];
- uint mrblr; /* Maximum Receive Buffer Length */
- uint res344[16];
- uint rbptr; /* RxBD Pointer */
- uint res388[30];
+ u32 rctrl; /* Receive Control */
+ u32 rstat; /* Receive Status */
+ u32 res308;
+ u32 rbdlen; /* RxBD Data Length */
+ u32 res310[4];
+ u32 res320;
+ u32 crbptr; /* Current Receive Buffer Pointer */
+ u32 res328[6];
+ u32 mrblr; /* Maximum Receive Buffer Length */
+ u32 res344[16];
+ u32 rbptr; /* RxBD Pointer */
+ u32 res388[30];
/* (0x2_n400) */
- uint res400;
- uint rbase; /* RxBD Base Address */
- uint res408[62];
+ u32 res400;
+ u32 rbase; /* RxBD Base Address */
+ u32 res408[62];
/* MAC Registers (0x2_n500) */
- uint maccfg1; /* MAC Configuration #1 */
- uint maccfg2; /* MAC Configuration #2 */
- uint ipgifg; /* Inter Packet Gap/Inter Frame Gap */
- uint hafdup; /* Half-duplex */
- uint maxfrm; /* Maximum Frame */
- uint res514;
- uint res518;
+ u32 maccfg1; /* MAC Configuration #1 */
+ u32 maccfg2; /* MAC Configuration #2 */
+ u32 ipgifg; /* Inter Packet Gap/Inter Frame Gap */
+ u32 hafdup; /* Half-duplex */
+ u32 maxfrm; /* Maximum Frame */
+ u32 res514;
+ u32 res518;
- uint res51c;
+ u32 res51c;
- uint resmdio[6];
+ u32 resmdio[6];
- uint res538;
+ u32 res538;
- uint ifstat; /* Interface Status */
- uint macstnaddr1; /* Station Address, part 1 */
- uint macstnaddr2; /* Station Address, part 2 */
- uint res548[46];
+ u32 ifstat; /* Interface Status */
+ u32 macstnaddr1; /* Station Address, part 1 */
+ u32 macstnaddr2; /* Station Address, part 2 */
+ u32 res548[46];
/* (0x2_n600) */
- uint res600[32];
+ u32 res600[32];
/* RMON MIB Registers (0x2_n680-0x2_n73c) */
- rmon_mib_t rmon;
- uint res740[48];
+ struct tsec_rmon_mib rmon;
+ u32 res740[48];
/* Hash Function Registers (0x2_n800) */
- tsec_hash_t hash;
+ struct tsec_hash_regs hash;
- uint res900[128];
+ u32 res900[128];
/* Pattern Registers (0x2_nb00) */
- uint resb00[62];
- uint attr; /* Default Attribute Register */
- uint attreli; /* Default Attribute Extract Length and Index */
+ u32 resb00[62];
+ u32 attr; /* Default Attribute Register */
+ u32 attreli; /* Default Attribute Extract Length and Index */
/* TSEC Future Expansion Space (0x2_nc00-0x2_nffc) */
- uint resc00[256];
-} tsec_t;
+ u32 resc00[256];
+};
#define TSEC_GIGABIT (1 << 0)
@@ -383,8 +390,8 @@
#define TSEC_SGMII (1 << 2) /* MAC-PHY interface uses SGMII */
struct tsec_private {
- tsec_t *regs;
- struct tsec_mii_mng *phyregs_sgmii;
+ struct tsec __iomem *regs;
+ struct tsec_mii_mng __iomem *phyregs_sgmii;
struct phy_device *phydev;
phy_interface_t interface;
struct mii_dev *bus;
@@ -394,8 +401,8 @@
};
struct tsec_info_struct {
- tsec_t *regs;
- struct tsec_mii_mng *miiregs_sgmii;
+ struct tsec __iomem *regs;
+ struct tsec_mii_mng __iomem *miiregs_sgmii;
char *devname;
char *mii_devname;
phy_interface_t interface;
diff --git a/lib/Makefile b/lib/Makefile
index 4e3b500..e787f77 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -6,6 +6,13 @@
#
ifndef CONFIG_SPL_BUILD
+
+obj-$(CONFIG_RSA) += rsa/
+obj-$(CONFIG_LZMA) += lzma/
+obj-$(CONFIG_LZO) += lzo/
+obj-$(CONFIG_ZLIB) += zlib/
+obj-$(CONFIG_TIZEN) += tizen/
+
obj-$(CONFIG_AES) += aes.o
obj-$(CONFIG_BZIP2) += bzlib.o
obj-$(CONFIG_BZIP2) += bzlib_crctable.o
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 51fa868..207314f 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -86,10 +86,10 @@
size = (fdt_size_t *)((char *)cell +
sizeof(fdt_addr_t));
*sizep = fdt_size_to_cpu(*size);
- debug("addr=%p, size=%p\n", (void *)addr,
- (void *)*sizep);
+ debug("addr=%08lx, size=%08x\n",
+ (ulong)addr, *sizep);
} else {
- debug("%p\n", (void *)addr);
+ debug("%08lx\n", (ulong)addr);
}
return addr;
}
@@ -611,7 +611,7 @@
if (!cell || (len != sizeof(fdt_addr_t) * 2))
return -1;
- *ptrp = (void *)fdt_addr_to_cpu(*cell);
+ *ptrp = map_sysmem(fdt_addr_to_cpu(*cell), *size);
*size = fdt_size_to_cpu(cell[1]);
debug("%s: size=%zx\n", __func__, *size);
return 0;
diff --git a/lib/lzma/Makefile b/lib/lzma/Makefile
index 25c6797..f8eda06 100644
--- a/lib/lzma/Makefile
+++ b/lib/lzma/Makefile
@@ -10,4 +10,4 @@
CFLAGS += -D_LZMA_PROB32
-obj-$(CONFIG_LZMA) += LzmaDec.o LzmaTools.o
+obj-y += LzmaDec.o LzmaTools.o
diff --git a/lib/lzo/Makefile b/lib/lzo/Makefile
index dd853ea..2936544 100644
--- a/lib/lzo/Makefile
+++ b/lib/lzo/Makefile
@@ -5,4 +5,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(CONFIG_LZO) += lzo1x_decompress.o
+obj-y += lzo1x_decompress.o
diff --git a/lib/rsa/Makefile b/lib/rsa/Makefile
index 693c745..164ab39 100644
--- a/lib/rsa/Makefile
+++ b/lib/rsa/Makefile
@@ -7,6 +7,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifdef CONFIG_FIT_SIGNATURE
-obj-$(CONFIG_RSA) += rsa-verify.o
-endif
+obj-$(CONFIG_FIT_SIGNATURE) += rsa-verify.o
diff --git a/lib/time.c b/lib/time.c
index 111b493..09bb05a 100644
--- a/lib/time.c
+++ b/lib/time.c
@@ -51,7 +51,7 @@
return ((unsigned long long)gd->timebase_h << 32) | gd->timebase_l;
}
-static unsigned long long notrace tick_to_time(unsigned long long tick)
+static unsigned long long notrace tick_to_time(uint64_t tick)
{
unsigned int div = get_tbclk();
@@ -71,7 +71,7 @@
}
static unsigned long long usec_to_tick(unsigned long usec)
{
- unsigned long long tick = usec * get_tbclk();
+ uint64_t tick = usec * get_tbclk();
usec *= get_tbclk();
do_div(tick, 1000000);
return tick;
diff --git a/lib/zlib/Makefile b/lib/zlib/Makefile
index 1e9e04d..2fba95f 100644
--- a/lib/zlib/Makefile
+++ b/lib/zlib/Makefile
@@ -5,4 +5,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(CONFIG_ZLIB) += zlib.o
+obj-y += zlib.o
diff --git a/nand_spl/board/amcc/acadia/Makefile b/nand_spl/board/amcc/acadia/Makefile
index 20459c9..022a205 100644
--- a/nand_spl/board/amcc/acadia/Makefile
+++ b/nand_spl/board/amcc/acadia/Makefile
@@ -24,11 +24,9 @@
__OBJS := $(SOBJS) $(COBJS)
LNDIR := $(nandobj)board/$(BOARDDIR)
-ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin \
+all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin \
$(nandobj)System.map
-all: $(obj).depend $(ALL)
-
$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
@@ -37,13 +35,12 @@
$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds
cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
- -Map $(nandobj)u-boot-spl.map \
- -o $(nandobj)u-boot-spl
+ -Map $(nandobj)u-boot-spl.map -o $@
$(nandobj)System.map: $(nandobj)u-boot-spl
@$(NM) $< | \
grep -v '\(compiled\)\|\(\.o$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \
- sort > $(nandobj)System.map
+ sort > $@
$(nandobj)u-boot.lds: $(LDSCRIPT)
$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
@@ -52,43 +49,43 @@
# from cpu directory
$(obj)cache.S:
- @rm -f $(obj)cache.S
- ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/cache.S $(obj)cache.S
+ @rm -f $@
+ ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/cache.S $@
$(obj)gpio.c:
- @rm -f $(obj)gpio.c
- ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/gpio.c $(obj)gpio.c
+ @rm -f $@
+ ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/gpio.c $@
$(obj)ndfc.c:
- @rm -f $(obj)ndfc.c
- ln -s $(SRCTREE)/drivers/mtd/nand/ndfc.c $(obj)ndfc.c
+ @rm -f $@
+ ln -s $(SRCTREE)/drivers/mtd/nand/ndfc.c $@
$(obj)resetvec.S:
- @rm -f $(obj)resetvec.S
- ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/resetvec.S $(obj)resetvec.S
+ @rm -f $@
+ ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/resetvec.S $@
$(obj)start.S:
- @rm -f $(obj)start.S
- ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/start.S $(obj)start.S
+ @rm -f $@
+ ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/start.S $@
# from board directory
$(obj)memory.c:
- @rm -f $(obj)memory.c
- ln -s $(SRCTREE)/board/amcc/acadia/memory.c $(obj)memory.c
+ @rm -f $@
+ ln -s $(SRCTREE)/board/amcc/acadia/memory.c $@
$(obj)pll.c:
- @rm -f $(obj)pll.c
- ln -s $(SRCTREE)/board/amcc/acadia/pll.c $(obj)pll.c
+ @rm -f $@
+ ln -s $(SRCTREE)/board/amcc/acadia/pll.c $@
# from nand_spl directory
$(obj)nand_boot.c:
- @rm -f $(obj)nand_boot.c
- ln -s $(SRCTREE)/nand_spl/nand_boot.c $(obj)nand_boot.c
+ @rm -f $@
+ ln -s $(SRCTREE)/nand_spl/nand_boot.c $@
# from drivers/mtd/nand directory
$(obj)nand_ecc.c:
- @rm -f $(obj)nand_ecc.c
- ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $(obj)nand_ecc.c
+ @rm -f $@
+ ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $@
#########################################################################
diff --git a/nand_spl/board/amcc/bamboo/Makefile b/nand_spl/board/amcc/bamboo/Makefile
index ca3dab4..d413a48 100644
--- a/nand_spl/board/amcc/bamboo/Makefile
+++ b/nand_spl/board/amcc/bamboo/Makefile
@@ -24,9 +24,7 @@
__OBJS := $(SOBJS) $(COBJS)
LNDIR := $(nandobj)board/$(BOARDDIR)
-ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
-
-all: $(obj).depend $(ALL)
+all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
@@ -36,8 +34,7 @@
$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds
cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
- -Map $(nandobj)u-boot-spl.map \
- -o $(nandobj)u-boot-spl
+ -Map $(nandobj)u-boot-spl.map -o $@
$(nandobj)u-boot.lds: $(LDSCRIPT)
$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
@@ -46,36 +43,36 @@
# from cpu directory
$(obj)ndfc.c:
- @rm -f $(obj)ndfc.c
- ln -s $(SRCTREE)/drivers/mtd/nand/ndfc.c $(obj)ndfc.c
+ @rm -f $@
+ ln -s $(SRCTREE)/drivers/mtd/nand/ndfc.c $@
$(obj)resetvec.S:
- @rm -f $(obj)resetvec.S
- ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/resetvec.S $(obj)resetvec.S
+ @rm -f $@
+ ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/resetvec.S $@
$(obj)start.S:
- @rm -f $(obj)start.S
- ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/start.S $(obj)start.S
+ @rm -f $@
+ ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/start.S $@
# from board directory
$(obj)init.S:
- @rm -f $(obj)init.S
- ln -s $(SRCTREE)/board/amcc/bamboo/init.S $(obj)init.S
+ @rm -f $@
+ ln -s $(SRCTREE)/board/amcc/bamboo/init.S $@
# from nand_spl directory
$(obj)nand_boot.c:
- @rm -f $(obj)nand_boot.c
- ln -s $(SRCTREE)/nand_spl/nand_boot.c $(obj)nand_boot.c
+ @rm -f $@
+ ln -s $(SRCTREE)/nand_spl/nand_boot.c $@
# from drivers/mtd/nand directory
$(obj)nand_ecc.c:
- @rm -f $(obj)nand_ecc.c
- ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $(obj)nand_ecc.c
+ @rm -f $@
+ ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $@
ifneq ($(OBJTREE), $(SRCTREE))
$(obj)sdram.c:
- @rm -f $(obj)sdram.c
- ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/sdram.c $(obj)sdram.c
+ @rm -f $@
+ ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/sdram.c $@
endif
#########################################################################
diff --git a/nand_spl/board/amcc/canyonlands/Makefile b/nand_spl/board/amcc/canyonlands/Makefile
index f50d84b..b2ef03f 100644
--- a/nand_spl/board/amcc/canyonlands/Makefile
+++ b/nand_spl/board/amcc/canyonlands/Makefile
@@ -29,9 +29,7 @@
__OBJS := $(SOBJS) $(COBJS)
LNDIR := $(nandobj)board/$(BOARDDIR)
-ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
-
-all: $(obj).depend $(ALL)
+all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
@@ -41,8 +39,7 @@
$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds
cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
- -Map $(nandobj)u-boot-spl.map \
- -o $(nandobj)u-boot-spl
+ -Map $(nandobj)u-boot-spl.map -o $@
$(nandobj)u-boot.lds: $(LDSCRIPT)
$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
@@ -51,36 +48,36 @@
# from cpu directory
$(obj)ndfc.c:
- @rm -f $(obj)ndfc.c
- ln -s $(SRCTREE)/drivers/mtd/nand/ndfc.c $(obj)ndfc.c
+ @rm -f $@
+ ln -s $(SRCTREE)/drivers/mtd/nand/ndfc.c $@
$(obj)resetvec.S:
- @rm -f $(obj)resetvec.S
- ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/resetvec.S $(obj)resetvec.S
+ @rm -f $@
+ ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/resetvec.S $@
$(obj)start.S:
- @rm -f $(obj)start.S
- ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/start.S $(obj)start.S
+ @rm -f $@
+ ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/start.S $@
# from board directory
$(obj)init.S:
- @rm -f $(obj)init.S
- ln -s $(SRCTREE)/board/amcc/canyonlands/init.S $(obj)init.S
+ @rm -f $@
+ ln -s $(SRCTREE)/board/amcc/canyonlands/init.S $@
# from nand_spl directory
$(obj)nand_boot.c:
- @rm -f $(obj)nand_boot.c
- ln -s $(SRCTREE)/nand_spl/nand_boot.c $(obj)nand_boot.c
+ @rm -f $@
+ ln -s $(SRCTREE)/nand_spl/nand_boot.c $@
# from drivers/mtd/nand directory
$(obj)nand_ecc.c:
- @rm -f $(obj)nand_ecc.c
- ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $(obj)nand_ecc.c
+ @rm -f $@
+ ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $@
ifneq ($(OBJTREE), $(SRCTREE))
$(obj)ddr2_fixed.c:
- @rm -f $(obj)ddr2_fixed.c
- ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/ddr2_fixed.c $(obj)ddr2_fixed.c
+ @rm -f $@
+ ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/ddr2_fixed.c $@
endif
#########################################################################
diff --git a/nand_spl/board/amcc/kilauea/Makefile b/nand_spl/board/amcc/kilauea/Makefile
index 8b4206f..5899b9e 100644
--- a/nand_spl/board/amcc/kilauea/Makefile
+++ b/nand_spl/board/amcc/kilauea/Makefile
@@ -24,9 +24,7 @@
__OBJS := $(SOBJS) $(COBJS)
LNDIR := $(nandobj)board/$(BOARDDIR)
-ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
-
-all: $(obj).depend $(ALL)
+all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
@@ -36,8 +34,7 @@
$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds
cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
- -Map $(nandobj)u-boot-spl.map \
- -o $(nandobj)u-boot-spl
+ -Map $(nandobj)u-boot-spl.map -o $@
$(nandobj)u-boot.lds: $(LDSCRIPT)
$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
@@ -46,38 +43,38 @@
# from cpu directory
$(obj)44x_spd_ddr2.c: $(obj)ecc.h
- @rm -f $(obj)44x_spd_ddr2.c
- ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c $(obj)44x_spd_ddr2.c
+ @rm -f $@
+ ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c $@
$(obj)cache.S:
- @rm -f $(obj)cache.S
- ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/cache.S $(obj)cache.S
+ @rm -f $@
+ ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/cache.S $@
$(obj)ecc.h:
- @rm -f $(obj)ecc.h
- ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/ecc.h $(obj)ecc.h
+ @rm -f $@
+ ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/ecc.h $@
$(obj)ndfc.c:
- @rm -f $(obj)ndfc.c
- ln -s $(SRCTREE)/drivers/mtd/nand/ndfc.c $(obj)ndfc.c
+ @rm -f $@
+ ln -s $(SRCTREE)/drivers/mtd/nand/ndfc.c $@
$(obj)resetvec.S:
- @rm -f $(obj)resetvec.S
- ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/resetvec.S $(obj)resetvec.S
+ @rm -f $@
+ ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/resetvec.S $@
$(obj)start.S:
- @rm -f $(obj)start.S
- ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/start.S $(obj)start.S
+ @rm -f $@
+ ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/start.S $@
# from nand_spl directory
$(obj)nand_boot.c:
- @rm -f $(obj)nand_boot.c
- ln -s $(SRCTREE)/nand_spl/nand_boot.c $(obj)nand_boot.c
+ @rm -f $@
+ ln -s $(SRCTREE)/nand_spl/nand_boot.c $@
# from drivers/nand directory
$(obj)nand_ecc.c:
- @rm -f $(obj)nand_ecc.c
- ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $(obj)nand_ecc.c
+ @rm -f $@
+ ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $@
#########################################################################
diff --git a/nand_spl/board/amcc/sequoia/Makefile b/nand_spl/board/amcc/sequoia/Makefile
index 0fcf030..fea6c4e 100644
--- a/nand_spl/board/amcc/sequoia/Makefile
+++ b/nand_spl/board/amcc/sequoia/Makefile
@@ -24,9 +24,7 @@
__OBJS := $(SOBJS) $(COBJS)
LNDIR := $(nandobj)board/$(BOARDDIR)
-ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
-
-all: $(obj).depend $(ALL)
+all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
@@ -36,8 +34,7 @@
$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds
cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
- -Map $(nandobj)u-boot-spl.map \
- -o $(nandobj)u-boot-spl
+ -Map $(nandobj)u-boot-spl.map -o $@
$(nandobj)u-boot.lds: $(LDSCRIPT)
$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
@@ -46,41 +43,41 @@
# from cpu directory
$(obj)denali_data_eye.c:
- @rm -f $(obj)denali_data_eye.c
- ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/denali_data_eye.c $(obj)denali_data_eye.c
+ @rm -f $@
+ ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/denali_data_eye.c $@
$(obj)ndfc.c:
- @rm -f $(obj)ndfc.c
- ln -s $(SRCTREE)/drivers/mtd/nand/ndfc.c $(obj)ndfc.c
+ @rm -f $@
+ ln -s $(SRCTREE)/drivers/mtd/nand/ndfc.c $@
$(obj)resetvec.S:
- @rm -f $(obj)resetvec.S
- ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/resetvec.S $(obj)resetvec.S
+ @rm -f $@
+ ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/resetvec.S $@
$(obj)start.S:
- @rm -f $(obj)start.S
- ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/start.S $(obj)start.S
+ @rm -f $@
+ ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/start.S $@
# from board directory
$(obj)init.S:
- @rm -f $(obj)init.S
- ln -s $(SRCTREE)/board/amcc/sequoia/init.S $(obj)init.S
+ @rm -f $@
+ ln -s $(SRCTREE)/board/amcc/sequoia/init.S $@
$(obj)sdram.c:
- @rm -f $(obj)sdram.c
+ @rm -f $@
@rm -f $(obj)sdram.h
- ln -s $(SRCTREE)/board/amcc/sequoia/sdram.c $(obj)sdram.c
+ ln -s $(SRCTREE)/board/amcc/sequoia/sdram.c $@
ln -s $(SRCTREE)/board/amcc/sequoia/sdram.h $(obj)sdram.h
# from nand_spl directory
$(obj)nand_boot.c:
- @rm -f $(obj)nand_boot.c
- ln -s $(SRCTREE)/nand_spl/nand_boot.c $(obj)nand_boot.c
+ @rm -f $@
+ ln -s $(SRCTREE)/nand_spl/nand_boot.c $@
# from drivers/mtd/nand directory
$(obj)nand_ecc.c:
- @rm -f $(obj)nand_ecc.c
- ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $(obj)nand_ecc.c
+ @rm -f $@
+ ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $@
#########################################################################
diff --git a/nand_spl/board/freescale/mpc8315erdb/Makefile b/nand_spl/board/freescale/mpc8315erdb/Makefile
index 5b11d10..c49a6e0 100644
--- a/nand_spl/board/freescale/mpc8315erdb/Makefile
+++ b/nand_spl/board/freescale/mpc8315erdb/Makefile
@@ -28,9 +28,7 @@
__OBJS := $(SOBJS) $(COBJS)
LNDIR := $(nandobj)board/$(BOARDDIR)
-ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
-
-all: $(obj).depend $(ALL)
+all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
@@ -40,8 +38,7 @@
$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds
cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
- -Map $(nandobj)u-boot-spl.map \
- -o $(nandobj)u-boot-spl
+ -Map $(nandobj)u-boot-spl.map -o $@
$(nandobj)u-boot.lds: $(LDSCRIPT)
$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
@@ -49,32 +46,31 @@
# create symbolic links for common files
$(obj)start.S:
- ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc83xx/start.S $(obj)start.S
+ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc83xx/start.S $@
$(obj)nand_boot_fsl_elbc.c:
- ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c \
- $(obj)nand_boot_fsl_elbc.c
+ ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c $@
$(obj)sdram.c:
- ln -sf $(SRCTREE)/board/$(BOARDDIR)/sdram.c $(obj)sdram.c
+ ln -sf $(SRCTREE)/board/$(BOARDDIR)/sdram.c $@
$(obj)$(BOARD).c:
- ln -sf $(SRCTREE)/board/$(BOARDDIR)/$(BOARD).c $(obj)$(BOARD).c
+ ln -sf $(SRCTREE)/board/$(BOARDDIR)/$(BOARD).c $@
$(obj)ns16550.c:
- ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c
+ ln -sf $(SRCTREE)/drivers/serial/ns16550.c $@
$(obj)spl_minimal.c:
- ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc83xx/spl_minimal.c $(obj)spl_minimal.c
+ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc83xx/spl_minimal.c $@
$(obj)cache.c:
- ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $(obj)cache.c
+ ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $@
$(obj)time.c:
- ln -sf $(SRCTREE)/arch/powerpc/lib/time.c $(obj)time.c
+ ln -sf $(SRCTREE)/arch/powerpc/lib/time.c $@
$(obj)ticks.S:
- ln -sf $(SRCTREE)/arch/powerpc/lib/ticks.S $(obj)ticks.S
+ ln -sf $(SRCTREE)/arch/powerpc/lib/ticks.S $@
#########################################################################
diff --git a/nand_spl/board/freescale/mpc8536ds/Makefile b/nand_spl/board/freescale/mpc8536ds/Makefile
index d3dac20..6233081 100644
--- a/nand_spl/board/freescale/mpc8536ds/Makefile
+++ b/nand_spl/board/freescale/mpc8536ds/Makefile
@@ -30,9 +30,7 @@
__OBJS := $(SOBJS) $(COBJS)
LNDIR := $(nandobj)board/$(BOARDDIR)
-ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
-
-all: $(obj).depend $(ALL)
+all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
@@ -42,8 +40,7 @@
$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot-nand_spl.lds
cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
- -Map $(nandobj)u-boot-spl.map \
- -o $(nandobj)u-boot-spl
+ -Map $(nandobj)u-boot-spl.map -o $@
$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT)
$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \
@@ -52,58 +49,57 @@
# create symbolic links for common files
$(obj)cache.c:
- @rm -f $(obj)cache.c
- ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $(obj)cache.c
+ @rm -f $@
+ ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $@
$(obj)cpu_init_early.c:
- @rm -f $(obj)cpu_init_early.c
- ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c
+ @rm -f $@
+ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $@
$(obj)spl_minimal.c:
- @rm -f $(obj)spl_minimal.c
- ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $(obj)spl_minimal.c
+ @rm -f $@
+ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $@
$(obj)fsl_law.c:
- @rm -f $(obj)fsl_law.c
- ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $(obj)fsl_law.c
+ @rm -f $@
+ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $@
$(obj)law.c:
- @rm -f $(obj)law.c
- ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $(obj)law.c
+ @rm -f $@
+ ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $@
$(obj)nand_boot_fsl_elbc.c:
- @rm -f $(obj)nand_boot_fsl_elbc.c
- ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c \
- $(obj)nand_boot_fsl_elbc.c
+ @rm -f $@
+ ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c $@
$(obj)ns16550.c:
- @rm -f $(obj)ns16550.c
- ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c
+ @rm -f $@
+ ln -sf $(SRCTREE)/drivers/serial/ns16550.c $@
$(obj)resetvec.S:
- @rm -f $(obj)resetvec.S
- ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $(obj)resetvec.S
+ @rm -f $@
+ ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $@
$(obj)fixed_ivor.S:
- @rm -f $(obj)fixed_ivor.S
- ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/fixed_ivor.S $(obj)fixed_ivor.S
+ @rm -f $@
+ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/fixed_ivor.S $@
$(obj)start.S: $(obj)fixed_ivor.S
- @rm -f $(obj)start.S
- ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/start.S $(obj)start.S
+ @rm -f $@
+ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/start.S $@
$(obj)tlb.c:
- @rm -f $(obj)tlb.c
- ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/tlb.c $(obj)tlb.c
+ @rm -f $@
+ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/tlb.c $@
$(obj)tlb_table.c:
- @rm -f $(obj)tlb_table.c
- ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $(obj)tlb_table.c
+ @rm -f $@
+ ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $@
ifneq ($(OBJTREE), $(SRCTREE))
$(obj)nand_boot.c:
- @rm -f $(obj)nand_boot.c
- ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c
+ @rm -f $@
+ ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $@
endif
#########################################################################
diff --git a/nand_spl/board/freescale/mpc8569mds/Makefile b/nand_spl/board/freescale/mpc8569mds/Makefile
index d3dac20..6233081 100644
--- a/nand_spl/board/freescale/mpc8569mds/Makefile
+++ b/nand_spl/board/freescale/mpc8569mds/Makefile
@@ -30,9 +30,7 @@
__OBJS := $(SOBJS) $(COBJS)
LNDIR := $(nandobj)board/$(BOARDDIR)
-ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
-
-all: $(obj).depend $(ALL)
+all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
@@ -42,8 +40,7 @@
$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot-nand_spl.lds
cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
- -Map $(nandobj)u-boot-spl.map \
- -o $(nandobj)u-boot-spl
+ -Map $(nandobj)u-boot-spl.map -o $@
$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT)
$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \
@@ -52,58 +49,57 @@
# create symbolic links for common files
$(obj)cache.c:
- @rm -f $(obj)cache.c
- ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $(obj)cache.c
+ @rm -f $@
+ ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $@
$(obj)cpu_init_early.c:
- @rm -f $(obj)cpu_init_early.c
- ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c
+ @rm -f $@
+ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $@
$(obj)spl_minimal.c:
- @rm -f $(obj)spl_minimal.c
- ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $(obj)spl_minimal.c
+ @rm -f $@
+ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $@
$(obj)fsl_law.c:
- @rm -f $(obj)fsl_law.c
- ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $(obj)fsl_law.c
+ @rm -f $@
+ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $@
$(obj)law.c:
- @rm -f $(obj)law.c
- ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $(obj)law.c
+ @rm -f $@
+ ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $@
$(obj)nand_boot_fsl_elbc.c:
- @rm -f $(obj)nand_boot_fsl_elbc.c
- ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c \
- $(obj)nand_boot_fsl_elbc.c
+ @rm -f $@
+ ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c $@
$(obj)ns16550.c:
- @rm -f $(obj)ns16550.c
- ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c
+ @rm -f $@
+ ln -sf $(SRCTREE)/drivers/serial/ns16550.c $@
$(obj)resetvec.S:
- @rm -f $(obj)resetvec.S
- ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $(obj)resetvec.S
+ @rm -f $@
+ ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $@
$(obj)fixed_ivor.S:
- @rm -f $(obj)fixed_ivor.S
- ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/fixed_ivor.S $(obj)fixed_ivor.S
+ @rm -f $@
+ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/fixed_ivor.S $@
$(obj)start.S: $(obj)fixed_ivor.S
- @rm -f $(obj)start.S
- ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/start.S $(obj)start.S
+ @rm -f $@
+ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/start.S $@
$(obj)tlb.c:
- @rm -f $(obj)tlb.c
- ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/tlb.c $(obj)tlb.c
+ @rm -f $@
+ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/tlb.c $@
$(obj)tlb_table.c:
- @rm -f $(obj)tlb_table.c
- ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $(obj)tlb_table.c
+ @rm -f $@
+ ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $@
ifneq ($(OBJTREE), $(SRCTREE))
$(obj)nand_boot.c:
- @rm -f $(obj)nand_boot.c
- ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c
+ @rm -f $@
+ ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $@
endif
#########################################################################
diff --git a/nand_spl/board/freescale/mpc8569mds/nand_boot.c b/nand_spl/board/freescale/mpc8569mds/nand_boot.c
index 716b737..ce7f619 100644
--- a/nand_spl/board/freescale/mpc8569mds/nand_boot.c
+++ b/nand_spl/board/freescale/mpc8569mds/nand_boot.c
@@ -10,7 +10,7 @@
#include <nand.h>
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/fsl_law.h>
#define SYSCLK_66 66666666
diff --git a/nand_spl/board/freescale/mpc8572ds/Makefile b/nand_spl/board/freescale/mpc8572ds/Makefile
index d3dac20..6233081 100644
--- a/nand_spl/board/freescale/mpc8572ds/Makefile
+++ b/nand_spl/board/freescale/mpc8572ds/Makefile
@@ -30,9 +30,7 @@
__OBJS := $(SOBJS) $(COBJS)
LNDIR := $(nandobj)board/$(BOARDDIR)
-ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
-
-all: $(obj).depend $(ALL)
+all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
@@ -42,8 +40,7 @@
$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot-nand_spl.lds
cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
- -Map $(nandobj)u-boot-spl.map \
- -o $(nandobj)u-boot-spl
+ -Map $(nandobj)u-boot-spl.map -o $@
$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT)
$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \
@@ -52,58 +49,57 @@
# create symbolic links for common files
$(obj)cache.c:
- @rm -f $(obj)cache.c
- ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $(obj)cache.c
+ @rm -f $@
+ ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $@
$(obj)cpu_init_early.c:
- @rm -f $(obj)cpu_init_early.c
- ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c
+ @rm -f $@
+ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $@
$(obj)spl_minimal.c:
- @rm -f $(obj)spl_minimal.c
- ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $(obj)spl_minimal.c
+ @rm -f $@
+ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $@
$(obj)fsl_law.c:
- @rm -f $(obj)fsl_law.c
- ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $(obj)fsl_law.c
+ @rm -f $@
+ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $@
$(obj)law.c:
- @rm -f $(obj)law.c
- ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $(obj)law.c
+ @rm -f $@
+ ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $@
$(obj)nand_boot_fsl_elbc.c:
- @rm -f $(obj)nand_boot_fsl_elbc.c
- ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c \
- $(obj)nand_boot_fsl_elbc.c
+ @rm -f $@
+ ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c $@
$(obj)ns16550.c:
- @rm -f $(obj)ns16550.c
- ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c
+ @rm -f $@
+ ln -sf $(SRCTREE)/drivers/serial/ns16550.c $@
$(obj)resetvec.S:
- @rm -f $(obj)resetvec.S
- ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $(obj)resetvec.S
+ @rm -f $@
+ ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $@
$(obj)fixed_ivor.S:
- @rm -f $(obj)fixed_ivor.S
- ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/fixed_ivor.S $(obj)fixed_ivor.S
+ @rm -f $@
+ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/fixed_ivor.S $@
$(obj)start.S: $(obj)fixed_ivor.S
- @rm -f $(obj)start.S
- ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/start.S $(obj)start.S
+ @rm -f $@
+ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/start.S $@
$(obj)tlb.c:
- @rm -f $(obj)tlb.c
- ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/tlb.c $(obj)tlb.c
+ @rm -f $@
+ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/tlb.c $@
$(obj)tlb_table.c:
- @rm -f $(obj)tlb_table.c
- ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $(obj)tlb_table.c
+ @rm -f $@
+ ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $@
ifneq ($(OBJTREE), $(SRCTREE))
$(obj)nand_boot.c:
- @rm -f $(obj)nand_boot.c
- ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c
+ @rm -f $@
+ ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $@
endif
#########################################################################
diff --git a/nand_spl/board/freescale/p1023rds/Makefile b/nand_spl/board/freescale/p1023rds/Makefile
index e89d405..dbdfa19 100644
--- a/nand_spl/board/freescale/p1023rds/Makefile
+++ b/nand_spl/board/freescale/p1023rds/Makefile
@@ -25,9 +25,7 @@
__OBJS := $(SOBJS) $(COBJS)
LNDIR := $(nandobj)board/$(BOARDDIR)
-ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
-
-all: $(obj).depend $(ALL)
+all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
@@ -37,8 +35,7 @@
$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot-nand_spl.lds
cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
- -Map $(nandobj)u-boot-spl.map \
- -o $(nandobj)u-boot-spl
+ -Map $(nandobj)u-boot-spl.map -o $@
$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT)
$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \
@@ -47,58 +44,57 @@
# create symbolic links for common files
$(obj)cache.c:
- @rm -f $(obj)cache.c
- ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $(obj)cache.c
+ @rm -f $@
+ ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $@
$(obj)cpu_init_early.c:
- @rm -f $(obj)cpu_init_early.c
- ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_early.c $(obj)cpu_init_early.c
+ @rm -f $@
+ ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_early.c $@
$(obj)spl_minimal.c:
- @rm -f $(obj)spl_minimal.c
- ln -sf $(SRCTREE)/$(CPUDIR)/spl_minimal.c $(obj)spl_minimal.c
+ @rm -f $@
+ ln -sf $(SRCTREE)/$(CPUDIR)/spl_minimal.c $@
$(obj)fsl_law.c:
- @rm -f $(obj)fsl_law.c
- ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $(obj)fsl_law.c
+ @rm -f $@
+ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $@
$(obj)law.c:
- @rm -f $(obj)law.c
- ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $(obj)law.c
+ @rm -f $@
+ ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $@
$(obj)nand_boot_fsl_elbc.c:
- @rm -f $(obj)nand_boot_fsl_elbc.c
- ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c \
- $(obj)nand_boot_fsl_elbc.c
+ @rm -f $@
+ ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c $@
$(obj)ns16550.c:
- @rm -f $(obj)ns16550.c
- ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c
+ @rm -f $@
+ ln -sf $(SRCTREE)/drivers/serial/ns16550.c $@
$(obj)resetvec.S:
- @rm -f $(obj)resetvec.S
- ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $(obj)resetvec.S
+ @rm -f $@
+ ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $@
$(obj)fixed_ivor.S:
- @rm -f $(obj)fixed_ivor.S
- ln -sf $(SRCTREE)/$(CPUDIR)/fixed_ivor.S $(obj)fixed_ivor.S
+ @rm -f $@
+ ln -sf $(SRCTREE)/$(CPUDIR)/fixed_ivor.S $@
$(obj)start.S: $(obj)fixed_ivor.S
- @rm -f $(obj)start.S
- ln -sf $(SRCTREE)/$(CPUDIR)/start.S $(obj)start.S
+ @rm -f $@
+ ln -sf $(SRCTREE)/$(CPUDIR)/start.S $@
$(obj)tlb.c:
- @rm -f $(obj)tlb.c
- ln -sf $(SRCTREE)/$(CPUDIR)/tlb.c $(obj)tlb.c
+ @rm -f $@
+ ln -sf $(SRCTREE)/$(CPUDIR)/tlb.c $@
$(obj)tlb_table.c:
- @rm -f $(obj)tlb_table.c
- ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $(obj)tlb_table.c
+ @rm -f $@
+ ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $@
ifneq ($(OBJTREE), $(SRCTREE))
$(obj)nand_boot.c:
- @rm -f $(obj)nand_boot.c
- ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c
+ @rm -f $@
+ ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $@
endif
#########################################################################
diff --git a/nand_spl/board/freescale/p1023rds/nand_boot.c b/nand_spl/board/freescale/p1023rds/nand_boot.c
index 9468000..d9afa6d 100644
--- a/nand_spl/board/freescale/p1023rds/nand_boot.c
+++ b/nand_spl/board/freescale/p1023rds/nand_boot.c
@@ -10,7 +10,7 @@
#include <asm/io.h>
#include <nand.h>
#include <asm/fsl_law.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -18,7 +18,8 @@
/* Fixed sdram init -- doesn't use serial presence detect. */
void sdram_init(void)
{
- ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
+ struct ccsr_ddr __iomem *ddr =
+ (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
set_next_law(0, LAW_SIZE_2G, LAW_TRGT_IF_DDR_1);
diff --git a/nand_spl/board/freescale/p1_p2_rdb/Makefile b/nand_spl/board/freescale/p1_p2_rdb/Makefile
index d3dac20..6233081 100644
--- a/nand_spl/board/freescale/p1_p2_rdb/Makefile
+++ b/nand_spl/board/freescale/p1_p2_rdb/Makefile
@@ -30,9 +30,7 @@
__OBJS := $(SOBJS) $(COBJS)
LNDIR := $(nandobj)board/$(BOARDDIR)
-ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
-
-all: $(obj).depend $(ALL)
+all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
@@ -42,8 +40,7 @@
$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot-nand_spl.lds
cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
- -Map $(nandobj)u-boot-spl.map \
- -o $(nandobj)u-boot-spl
+ -Map $(nandobj)u-boot-spl.map -o $@
$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT)
$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \
@@ -52,58 +49,57 @@
# create symbolic links for common files
$(obj)cache.c:
- @rm -f $(obj)cache.c
- ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $(obj)cache.c
+ @rm -f $@
+ ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $@
$(obj)cpu_init_early.c:
- @rm -f $(obj)cpu_init_early.c
- ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c
+ @rm -f $@
+ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $@
$(obj)spl_minimal.c:
- @rm -f $(obj)spl_minimal.c
- ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $(obj)spl_minimal.c
+ @rm -f $@
+ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $@
$(obj)fsl_law.c:
- @rm -f $(obj)fsl_law.c
- ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $(obj)fsl_law.c
+ @rm -f $@
+ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $@
$(obj)law.c:
- @rm -f $(obj)law.c
- ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $(obj)law.c
+ @rm -f $@
+ ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $@
$(obj)nand_boot_fsl_elbc.c:
- @rm -f $(obj)nand_boot_fsl_elbc.c
- ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c \
- $(obj)nand_boot_fsl_elbc.c
+ @rm -f $@
+ ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c $@
$(obj)ns16550.c:
- @rm -f $(obj)ns16550.c
- ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c
+ @rm -f $@
+ ln -sf $(SRCTREE)/drivers/serial/ns16550.c $@
$(obj)resetvec.S:
- @rm -f $(obj)resetvec.S
- ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $(obj)resetvec.S
+ @rm -f $@
+ ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $@
$(obj)fixed_ivor.S:
- @rm -f $(obj)fixed_ivor.S
- ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/fixed_ivor.S $(obj)fixed_ivor.S
+ @rm -f $@
+ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/fixed_ivor.S $@
$(obj)start.S: $(obj)fixed_ivor.S
- @rm -f $(obj)start.S
- ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/start.S $(obj)start.S
+ @rm -f $@
+ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/start.S $@
$(obj)tlb.c:
- @rm -f $(obj)tlb.c
- ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/tlb.c $(obj)tlb.c
+ @rm -f $@
+ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/tlb.c $@
$(obj)tlb_table.c:
- @rm -f $(obj)tlb_table.c
- ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $(obj)tlb_table.c
+ @rm -f $@
+ ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $@
ifneq ($(OBJTREE), $(SRCTREE))
$(obj)nand_boot.c:
- @rm -f $(obj)nand_boot.c
- ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c
+ @rm -f $@
+ ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $@
endif
#########################################################################
diff --git a/nand_spl/board/freescale/p1_p2_rdb/nand_boot.c b/nand_spl/board/freescale/p1_p2_rdb/nand_boot.c
index 3244c8f..f7e8438 100644
--- a/nand_spl/board/freescale/p1_p2_rdb/nand_boot.c
+++ b/nand_spl/board/freescale/p1_p2_rdb/nand_boot.c
@@ -10,7 +10,7 @@
#include <nand.h>
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/fsl_law.h>
#define SYSCLK_MASK 0x00200000
diff --git a/nand_spl/board/sheldon/simpc8313/Makefile b/nand_spl/board/sheldon/simpc8313/Makefile
index 08739ed..90f132c 100644
--- a/nand_spl/board/sheldon/simpc8313/Makefile
+++ b/nand_spl/board/sheldon/simpc8313/Makefile
@@ -28,9 +28,7 @@
__OBJS := $(SOBJS) $(COBJS)
LNDIR := $(nandobj)board/$(BOARDDIR)
-ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
-
-all: $(obj).depend $(ALL)
+all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
@@ -40,8 +38,7 @@
$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds
cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
- -Map $(nandobj)u-boot-spl.map \
- -o $(nandobj)u-boot-spl
+ -Map $(nandobj)u-boot-spl.map -o $@
$(nandobj)u-boot.lds: $(LDSCRIPT)
$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
diff --git a/net/tftp.c b/net/tftp.c
index 6d333d5..966d1cf 100644
--- a/net/tftp.c
+++ b/net/tftp.c
@@ -281,7 +281,7 @@
* number of 0 this means that there was a wrap
* around of the (16 bit) counter.
*/
- if (TftpBlock == 0) {
+ if (TftpBlock == 0 && TftpLastBlock != 0) {
TftpBlockWrap++;
TftpBlockWrapOffset += TftpBlkSize * TFTP_SEQUENCE_SIZE;
TftpTimeoutCount = 0; /* we've done well, reset thhe timeout */
@@ -849,6 +849,9 @@
TftpState = STATE_RECV_WRQ;
net_set_udp_handler(TftpHandler);
+
+ /* zero out server ether in case the server ip has changed */
+ memset(NetServerEther, 0, 6);
}
#endif /* CONFIG_CMD_TFTPSRV */
diff --git a/post/board/lwmon/Makefile b/post/board/lwmon/Makefile
index 1ac7aa5..b23debc 100644
--- a/post/board/lwmon/Makefile
+++ b/post/board/lwmon/Makefile
@@ -5,6 +5,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-CPPFLAGS += -I$(TOPDIR)
-
obj-$(CONFIG_HAS_POST) += sysmon.o
diff --git a/post/board/lwmon5/Makefile b/post/board/lwmon5/Makefile
index d8b1952..a50ce67 100644
--- a/post/board/lwmon5/Makefile
+++ b/post/board/lwmon5/Makefile
@@ -5,6 +5,4 @@
#
# SPDX-License-Identifier: GPL-2.0+
-CPPFLAGS += -I$(TOPDIR)
-
obj-$(CONFIG_HAS_POST) += sysmon.o watchdog.o dspic.o fpga.o dsp.o gdc.o
diff --git a/post/board/netta/Makefile b/post/board/netta/Makefile
index cd27a5c..5c37f49 100644
--- a/post/board/netta/Makefile
+++ b/post/board/netta/Makefile
@@ -5,6 +5,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-CPPFLAGS += -I$(TOPDIR)
-
obj-$(CONFIG_HAS_POST) += codec.o dsp.o
diff --git a/post/board/pdm360ng/Makefile b/post/board/pdm360ng/Makefile
index 3f74889..b43b77b 100644
--- a/post/board/pdm360ng/Makefile
+++ b/post/board/pdm360ng/Makefile
@@ -5,6 +5,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-CPPFLAGS += -I$(TOPDIR)
-
obj-$(CONFIG_HAS_POST) += coproc_com.o
diff --git a/post/cpu/mpc83xx/Makefile b/post/cpu/mpc83xx/Makefile
index 0643d01..4b3c50e 100644
--- a/post/cpu/mpc83xx/Makefile
+++ b/post/cpu/mpc83xx/Makefile
@@ -5,6 +5,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-CPPFLAGS += -I$(TOPDIR)
-
obj-$(CONFIG_HAS_POST) += ecc.o
diff --git a/post/cpu/mpc8xx/Makefile b/post/cpu/mpc8xx/Makefile
index 7a2930a..f8bb6c9 100644
--- a/post/cpu/mpc8xx/Makefile
+++ b/post/cpu/mpc8xx/Makefile
@@ -5,7 +5,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
-CPPFLAGS += -I$(TOPDIR)
-
obj-$(CONFIG_HAS_POST) += cache_8xx.o
obj-$(CONFIG_HAS_POST) += cache.o ether.o spr.o uart.o usb.o watchdog.o
diff --git a/post/cpu/ppc4xx/Makefile b/post/cpu/ppc4xx/Makefile
index b7435c8..ed3e8e8 100644
--- a/post/cpu/ppc4xx/Makefile
+++ b/post/cpu/ppc4xx/Makefile
@@ -5,8 +5,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-CPPFLAGS += -I$(TOPDIR)
-
obj-$(CONFIG_HAS_POST) += cache_4xx.o
obj-$(CONFIG_HAS_POST) += cache.o
obj-$(CONFIG_HAS_POST) += denali_ecc.o
diff --git a/post/drivers/Makefile b/post/drivers/Makefile
index 2f6844c..328f880 100644
--- a/post/drivers/Makefile
+++ b/post/drivers/Makefile
@@ -5,6 +5,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-CPPFLAGS += -I$(TOPDIR)
-
obj-$(CONFIG_HAS_POST) += flash.o i2c.o memory.o rtc.o
diff --git a/post/lib_powerpc/Makefile b/post/lib_powerpc/Makefile
index f19fea3..d2b8a94 100644
--- a/post/lib_powerpc/Makefile
+++ b/post/lib_powerpc/Makefile
@@ -5,8 +5,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-CPPFLAGS += -I$(TOPDIR)
-
obj-$(CONFIG_HAS_POST) += asm.o
obj-$(CONFIG_HAS_POST) += cpu.o cmp.o cmpi.o two.o twox.o three.o threex.o
obj-$(CONFIG_HAS_POST) += threei.o andi.o srawi.o rlwnm.o rlwinm.o rlwimi.o
diff --git a/post/lib_powerpc/fpu/Makefile b/post/lib_powerpc/fpu/Makefile
index 6aec96c..ee01a31 100644
--- a/post/lib_powerpc/fpu/Makefile
+++ b/post/lib_powerpc/fpu/Makefile
@@ -5,8 +5,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-CPPFLAGS += -I$(TOPDIR)
-
obj-$(CONFIG_HAS_POST) += 20001122-1.o
obj-$(CONFIG_HAS_POST) += 20010114-2.o
obj-$(CONFIG_HAS_POST) += 20010226-1.o
diff --git a/scripts/Makefile.build b/scripts/Makefile.build
index 2ef7341..e3354aa 100644
--- a/scripts/Makefile.build
+++ b/scripts/Makefile.build
@@ -10,10 +10,6 @@
include Makefile
-# Backward compatible: obj-y is preferable
-COBJS := $(sort $(COBJS) $(COBJS-y))
-SOBJS := $(sort $(SOBJS) $(SOBJS-y))
-
# Going forward use the following
obj-y := $(sort $(obj-y))
extra-y := $(sort $(extra-y))
@@ -24,11 +20,18 @@
subdir-obj-y := $(filter %/built-in.o, $(obj-y))
subdir-obj-y := $(addprefix $(obj),$(subdir-obj-y))
-SRCS += $(COBJS:.o=.c) $(SOBJS:.o=.S) \
- $(wildcard $(obj-y:.o=.c) $(obj-y:.o=.S) $(lib-y:.o=.c) $(lib-y:.o=.S) $(extra-y:.o=.c) $(extra-y:.o=.S))
-OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS) $(obj-y))
+SRCS += $(wildcard $(obj-y:.o=.c) $(obj-y:.o=.S) $(lib-y:.o=.c) \
+ $(lib-y:.o=.S) $(extra-y:.o=.c) $(extra-y:.o=.S))
+OBJS := $(addprefix $(obj),$(obj-y))
-LGOBJS := $(addprefix $(obj),$(sort $(GLSOBJS) $(GLCOBJS)) $(lib-y))
+# $(obj-dirs) is a list of directories that contain object files
+obj-dirs := $(dir $(OBJS))
+
+# Create directories for object files if directory does not exist
+# Needed when obj-y := dir/file.o syntax is used
+_dummy := $(foreach d,$(obj-dirs), $(shell [ -d $(d) ] || mkdir -p $(d)))
+
+LGOBJS := $(addprefix $(obj),$(sort $(lib-y)))
all: $(LIB) $(addprefix $(obj),$(extra-y))
diff --git a/spl/Makefile b/spl/Makefile
index cbd3d27..2a787af 100644
--- a/spl/Makefile
+++ b/spl/Makefile
@@ -54,63 +54,55 @@
START += $(START_PATH)/resetvec.o
endif
-LIBS-y += arch/$(ARCH)/lib/lib$(ARCH).o
+LIBS-y += arch/$(ARCH)/lib/
-LIBS-y += $(CPUDIR)/lib$(CPU).o
-ifeq ($(CPU),mpc83xx)
-LIBS-y += arch/powerpc/cpu/mpc8xxx/lib8xxx.o
-endif
-ifeq ($(CPU),mpc85xx)
-LIBS-y += arch/powerpc/cpu/mpc8xxx/lib8xxx.o
-ifdef CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
-LIBS-y += arch/powerpc/cpu/mpc8xxx/ddr/libddr.o
-endif
-endif
-ifeq ($(CPU),mpc86xx)
-LIBS-y += arch/powerpc/cpu/mpc8xxx/lib8xxx.o
-endif
+LIBS-y += $(CPUDIR)/
ifdef SOC
-LIBS-y += $(CPUDIR)/$(SOC)/lib$(SOC).o
+LIBS-y += $(CPUDIR)/$(SOC)/
endif
-LIBS-y += board/$(BOARDDIR)/lib$(BOARD).o
-LIBS-$(HAVE_VENDOR_COMMON_LIB) += board/$(VENDOR)/common/lib$(VENDOR).o
+LIBS-y += board/$(BOARDDIR)/
+LIBS-$(HAVE_VENDOR_COMMON_LIB) += board/$(VENDOR)/common/
-LIBS-$(CONFIG_SPL_FRAMEWORK) += common/spl/libspl.o
-LIBS-$(CONFIG_SPL_LIBCOMMON_SUPPORT) += common/libcommon.o
-LIBS-$(CONFIG_SPL_LIBDISK_SUPPORT) += disk/libdisk.o
-LIBS-$(CONFIG_SPL_I2C_SUPPORT) += drivers/i2c/libi2c.o
-LIBS-$(CONFIG_SPL_GPIO_SUPPORT) += drivers/gpio/libgpio.o
-LIBS-$(CONFIG_SPL_MMC_SUPPORT) += drivers/mmc/libmmc.o
-LIBS-$(CONFIG_SPL_SERIAL_SUPPORT) += drivers/serial/libserial.o
-LIBS-$(CONFIG_SPL_SPI_FLASH_SUPPORT) += drivers/mtd/spi/libspi_flash.o
-LIBS-$(CONFIG_SPL_SPI_SUPPORT) += drivers/spi/libspi.o
-LIBS-$(CONFIG_SPL_FAT_SUPPORT) += fs/fat/libfat.o
-LIBS-$(CONFIG_SPL_LIBGENERIC_SUPPORT) += lib/libgeneric.o
-LIBS-$(CONFIG_SPL_POWER_SUPPORT) += drivers/power/libpower.o \
- drivers/power/pmic/libpmic.o
-LIBS-$(CONFIG_SPL_NAND_SUPPORT) += drivers/mtd/nand/libnand.o
-LIBS-$(CONFIG_SPL_ONENAND_SUPPORT) += drivers/mtd/onenand/libonenand.o
-LIBS-$(CONFIG_SPL_DMA_SUPPORT) += drivers/dma/libdma.o
-LIBS-$(CONFIG_SPL_POST_MEM_SUPPORT) += post/drivers/memory.o
-LIBS-$(CONFIG_SPL_NET_SUPPORT) += net/libnet.o
-LIBS-$(CONFIG_SPL_ETH_SUPPORT) += drivers/net/libnet.o
-LIBS-$(CONFIG_SPL_ETH_SUPPORT) += drivers/net/phy/libphy.o
-LIBS-$(CONFIG_SPL_USBETH_SUPPORT) += drivers/net/phy/libphy.o
-LIBS-$(CONFIG_SPL_MUSB_NEW_SUPPORT) += drivers/usb/musb-new/libusb_musb-new.o
-LIBS-$(CONFIG_SPL_USBETH_SUPPORT) += drivers/usb/gadget/libusb_gadget.o
-LIBS-$(CONFIG_SPL_WATCHDOG_SUPPORT) += drivers/watchdog/libwatchdog.o
+LIBS-$(CONFIG_SPL_FRAMEWORK) += common/spl/
+LIBS-$(CONFIG_SPL_LIBCOMMON_SUPPORT) += common/
+LIBS-$(CONFIG_SPL_LIBDISK_SUPPORT) += disk/
+LIBS-$(CONFIG_SPL_I2C_SUPPORT) += drivers/i2c/
+LIBS-$(CONFIG_SPL_GPIO_SUPPORT) += drivers/gpio/
+LIBS-$(CONFIG_SPL_MMC_SUPPORT) += drivers/mmc/
+LIBS-$(CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT) += drivers/ddr/fsl/
+LIBS-$(CONFIG_SPL_SERIAL_SUPPORT) += drivers/serial/
+LIBS-$(CONFIG_SPL_SPI_FLASH_SUPPORT) += drivers/mtd/spi/
+LIBS-$(CONFIG_SPL_SPI_SUPPORT) += drivers/spi/
+LIBS-y += fs/
+LIBS-$(CONFIG_SPL_LIBGENERIC_SUPPORT) += lib/
+LIBS-$(CONFIG_SPL_POWER_SUPPORT) += drivers/power/ \
+ drivers/power/pmic/
+LIBS-$(CONFIG_SPL_NAND_SUPPORT) += drivers/mtd/nand/
+LIBS-$(CONFIG_SPL_ONENAND_SUPPORT) += drivers/mtd/onenand/
+LIBS-$(CONFIG_SPL_DMA_SUPPORT) += drivers/dma/
+LIBS-$(CONFIG_SPL_POST_MEM_SUPPORT) += post/drivers/
+LIBS-$(CONFIG_SPL_NET_SUPPORT) += net/
+LIBS-$(CONFIG_SPL_ETH_SUPPORT) += drivers/net/
+LIBS-$(CONFIG_SPL_ETH_SUPPORT) += drivers/net/phy/
+LIBS-$(CONFIG_SPL_USBETH_SUPPORT) += drivers/net/phy/
+LIBS-$(CONFIG_SPL_MUSB_NEW_SUPPORT) += drivers/usb/musb-new/
+LIBS-$(CONFIG_SPL_USBETH_SUPPORT) += drivers/usb/gadget/
+LIBS-$(CONFIG_SPL_WATCHDOG_SUPPORT) += drivers/watchdog/
ifneq (,$(CONFIG_MX23)$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35))
-LIBS-y += arch/$(ARCH)/imx-common/libimx-common.o
+LIBS-y += arch/$(ARCH)/imx-common/
endif
-LIBS-$(CONFIG_ARM) += arch/arm/cpu/libcpu.o
+LIBS-$(CONFIG_ARM) += arch/arm/cpu/
+LIBS-$(CONFIG_PPC) += arch/powerpc/cpu/
ifneq ($(CONFIG_MX23)$(CONFIG_MX35),)
-LIBS-y += arch/$(ARCH)/imx-common/libimx-common.o
+LIBS-y += arch/$(ARCH)/imx-common/
endif
+LIBS-y := $(patsubst %/, %/built-in.o, $(LIBS-y))
+
# Add GCC lib
ifeq ("$(USE_PRIVATE_LIBGCC)", "yes")
PLATFORM_LIBGCC = $(SPLTREE)/arch/$(ARCH)/lib/libgcc.o
@@ -175,8 +167,7 @@
ifdef CONFIG_SAMSUNG
$(obj)$(BOARD)-spl.bin: $(obj)u-boot-spl.bin
- $(OBJTREE)/tools/mk$(BOARD)spl \
- $(obj)u-boot-spl.bin $(obj)$(BOARD)-spl.bin
+ $(OBJTREE)/tools/mk$(BOARD)spl $< $@
endif
$(obj)$(SPL_BIN).bin: $(obj)$(SPL_BIN)
@@ -195,7 +186,6 @@
$(LIBS): depend
$(MAKE) $(build) $(SRCTREE)$(dir $(subst $(SPLTREE),,$@))
- mv $(dir $@)built-in.o $@
$(obj)u-boot-spl.lds: $(LDSCRIPT) depend
$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(obj). -ansi -D__ASSEMBLY__ -P - < $< > $@
diff --git a/tools/buildman/README b/tools/buildman/README
index 090b653..c30c1d4 100644
--- a/tools/buildman/README
+++ b/tools/buildman/README
@@ -89,10 +89,16 @@
plan to use your machine for anything else, you can use -T to increase the
number of threads beyond the default.
-Buildman lets you build all boards, or a subset. Specify the subset using
-the board name, architecture name, SOC name, or anything else in the
-boards.cfg file. So 'at91' will build all AT91 boards (arm), powerpc will
-build all PowerPC boards.
+Buildman lets you build all boards, or a subset. Specify the subset by passing
+command-line arguments that list the desired board name, architecture name,
+SOC name, or anything else in the boards.cfg file. Multiple arguments are
+allowed. Each argument will be interpreted as a regular expression, so
+behaviour is a superset of exact or substring matching. Examples are:
+
+* 'tegra20' All boards with a Tegra20 SoC
+* 'tegra' All boards with any Tegra Soc (Tegra20, Tegra30, Tegra114...)
+* '^tegra[23]0$' All boards with either Tegra20 or Tegra30 SoC
+* 'powerpc' All PowerPC boards
Buildman does not store intermediate object files. It optionally copies
the binary output into a directory when a build is successful. Size
@@ -643,7 +649,7 @@
snapper9g45=${at91-boards} BUILD_TAG=443
This will use 'make ENABLE_AT91_TEST=1 BUILD_TAG=442' for snapper9260
-and 'make ENABLE_AT91_TEST=1 BUILD_TAG=442' for snapper9g45. A special
+and 'make ENABLE_AT91_TEST=1 BUILD_TAG=443' for snapper9g45. A special
variable ${target} is available to access the target name (snapper9260 and
snapper9g20 in this case). Variables are resolved recursively.
diff --git a/tools/buildman/board.py b/tools/buildman/board.py
index 1d3db20..5172a47 100644
--- a/tools/buildman/board.py
+++ b/tools/buildman/board.py
@@ -3,6 +3,8 @@
# SPDX-License-Identifier: GPL-2.0+
#
+import re
+
class Board:
"""A particular board that we can build"""
def __init__(self, status, arch, cpu, soc, vendor, board_name, target, options):
@@ -135,14 +137,22 @@
due to each argument, arranged by argument.
"""
result = {}
+ argres = {}
for arg in args:
result[arg] = 0
+ argres[arg] = re.compile(arg)
result['all'] = 0
for board in self._boards:
if args:
for arg in args:
- if arg in board.props:
+ argre = argres[arg]
+ match = False
+ for prop in board.props:
+ match = argre.match(prop)
+ if match:
+ break
+ if match:
if not board.build_it:
board.build_it = True
result[arg] += 1
diff --git a/tools/gdb/Makefile b/tools/gdb/Makefile
index dee91fc..dd98fb6 100644
--- a/tools/gdb/Makefile
+++ b/tools/gdb/Makefile
@@ -23,8 +23,6 @@
#
HOSTCPPFLAGS = -I$(BFD_ROOT_DIR)/include
-HOSTOS := $(shell uname -s | sed -e 's/\([Cc][Yy][Gg][Ww][Ii][Nn]\).*/cygwin/')
-
ifeq ($(HOSTOS),cygwin)
all:
diff --git a/tools/imls/Makefile b/tools/imls/Makefile
deleted file mode 100644
index b045df2..0000000
--- a/tools/imls/Makefile
+++ /dev/null
@@ -1,84 +0,0 @@
-#
-# (C) Copyright 2009 Marco Stornelli <marco.stornelli@gmail.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-include $(TOPDIR)/config.mk
-
-# Generated executable files
-BIN_FILES-y += imls
-
-# Source files which exist outside the tools/imls directory
-EXT_OBJ_FILES-y += lib/crc32.o
-EXT_OBJ_FILES-y += lib/md5.o
-EXT_OBJ_FILES-y += lib/sha1.o
-EXT_OBJ_FILES-y += common/image.o
-
-# Source files located in the tools/imls directory
-OBJ_FILES-y += imls.o
-
-# Flattened device tree objects
-LIBFDT_OBJ_FILES-y += fdt.o
-LIBFDT_OBJ_FILES-y += fdt_ro.o
-LIBFDT_OBJ_FILES-y += fdt_rw.o
-LIBFDT_OBJ_FILES-y += fdt_strerror.o
-LIBFDT_OBJ_FILES-y += fdt_wip.o
-
-# now $(obj) is defined
-SRCS += $(addprefix $(SRCTREE)/,$(EXT_OBJ_FILES-y:.o=.c))
-SRCS += $(addprefix $(SRCTREE)/tools/,$(OBJ_FILES-y:.o=.c))
-SRCS += $(addprefix $(SRCTREE)/lib/libfdt/,$(LIBFDT_OBJ_FILES-y:.o=.c))
-BINS := $(addprefix $(obj),$(sort $(BIN_FILES-y)))
-LIBFDT_OBJS := $(addprefix $(obj),$(LIBFDT_OBJ_FILES-y))
-
-#
-# Compile for a hosted environment on the target
-# Define __KERNEL_STRICT_NAMES to prevent typedef overlaps
-#
-HOSTCPPFLAGS = -idirafter $(SRCTREE)/include \
- -idirafter $(SRCTREE)/arch/$(ARCH)/include \
- -idirafter $(OBJTREE)/include \
- -I $(SRCTREE)/lib/libfdt \
- -I $(SRCTREE)/tools \
- -DUSE_HOSTCC -D__KERNEL_STRICT_NAMES
-
-ifeq ($(MTD_VERSION),old)
-HOSTCPPFLAGS += -DMTD_OLD
-endif
-
-all: $(BINS)
-
-$(obj)imls: $(obj)imls.o $(obj)crc32.o $(obj)image.o $(obj)md5.o \
- $(obj)sha1.o $(LIBFDT_OBJS)
- $(CC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
- $(STRIP) $@
-
-# Some files complain if compiled with -pedantic, use HOSTCFLAGS_NOPED
-$(obj)image.o: $(SRCTREE)/common/image.c
- $(CC) -g $(HOSTCFLAGS_NOPED) -c -o $@ $<
-
-$(obj)imls.o: $(SRCTREE)/tools/imls/imls.c
- $(CC) -g $(HOSTCFLAGS_NOPED) -c -o $@ $<
-
-# Some of the tool objects need to be accessed from outside the tools/imls directory
-$(obj)%.o: $(SRCTREE)/common/%.c
- $(CC) -g $(HOSTCFLAGS_NOPED) -c -o $@ $<
-
-$(obj)%.o: $(SRCTREE)/lib/%.c
- $(CC) -g $(HOSTCFLAGS) -c -o $@ $<
-
-$(obj)%.o: $(SRCTREE)/lib/libfdt/%.c
- $(CC) -g $(HOSTCFLAGS_NOPED) -c -o $@ $<
-
-clean:
- rm -rf *.o imls
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/tools/imls/README b/tools/imls/README
deleted file mode 100644
index 9adf923..0000000
--- a/tools/imls/README
+++ /dev/null
@@ -1,41 +0,0 @@
-#
-# (C) Copyright 2009 Marco Stornelli <marco.stornelli@gmail.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-IMLS
--------------
-
-imls is an implementation of a Linux command line tool to access
-to raw flash partitions and list images made with mkimage command.
-
-For building against older versions of the MTD headers (meaning before
-v2.6.8-rc1) it is required to pass the argument "MTD_VERSION=old" to
-make.
-
-Usage examples
---------------
-
-1) Flash with sectors of 128KiB and 32 sectors:
-
-> imls -c 32 -s 131072 /dev/mtd0
-Searching...
-Image Name: foo
-Created: Fri Apr 10 18:11:30 2009
-Image Type: Intel x86 Linux Standalone Program (uncompressed)
-Data Size: 10716 Bytes = 10.46 kB = 0.01 MB
-Load Address: 00000000
-Entry Point: 00000000
-
-2) Flash with sectors of 64KiB and 128 sectors and with a search offset of one
-sector:
-
-> imls -o 1 -c 128 -s 65536 /dev/mtd0
-Searching...
-Image Name: foo
-Created: Fri Apr 10 18:11:30 2009
-Image Type: Intel x86 Linux Standalone Program (uncompressed)
-Data Size: 10716 Bytes = 10.46 kB = 0.01 MB
-Load Address: 00000000
-Entry Point: 00000000
diff --git a/tools/imls/imls.c b/tools/imls/imls.c
deleted file mode 100644
index 95043b4..0000000
--- a/tools/imls/imls.c
+++ /dev/null
@@ -1,256 +0,0 @@
-/*
- * (C) Copyright 2009 Marco Stornelli
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <errno.h>
-#include <fcntl.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <stddef.h>
-#include <string.h>
-#include <sys/types.h>
-#include <sys/ioctl.h>
-#include <sys/stat.h>
-#include <unistd.h>
-#include <asm/page.h>
-
-#ifdef MTD_OLD
-#include <stdint.h>
-#include <linux/mtd/mtd.h>
-#else
-#define __user /* nothing */
-#include <mtd/mtd-user.h>
-#endif
-
-#include <sha1.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-#include <image.h>
-
-#define MIN(a, b) (((a) < (b)) ? (a) : (b))
-
-extern unsigned long crc32(unsigned long crc, const char *buf, unsigned int len);
-static void usage(void);
-static int image_verify_header(char *ptr, int fd);
-static int flash_bad_block(int fd, uint8_t mtd_type, loff_t start);
-
-char *cmdname;
-char *devicefile;
-
-unsigned int sectorcount = 0;
-int sflag = 0;
-unsigned int sectoroffset = 0;
-unsigned int sectorsize = 0;
-int cflag = 0;
-
-int main (int argc, char **argv)
-{
- int fd = -1, err = 0, readbyte = 0, j;
- struct mtd_info_user mtdinfo;
- char buf[sizeof(image_header_t)];
- int found = 0;
-
- cmdname = *argv;
-
- while (--argc > 0 && **++argv == '-') {
- while (*++*argv) {
- switch (**argv) {
- case 'c':
- if (--argc <= 0)
- usage ();
- sectorcount = (unsigned int)atoi(*++argv);
- cflag = 1;
- goto NXTARG;
- case 'o':
- if (--argc <= 0)
- usage ();
- sectoroffset = (unsigned int)atoi(*++argv);
- goto NXTARG;
-
- case 's':
- if (--argc <= 0)
- usage ();
- sectorsize = (unsigned int)atoi(*++argv);
- sflag = 1;
- goto NXTARG;
- default:
- usage ();
- }
- }
-NXTARG: ;
- }
-
- if (argc != 1 || cflag == 0 || sflag == 0)
- usage();
-
- devicefile = *argv;
-
- fd = open(devicefile, O_RDONLY);
- if (fd < 0) {
- fprintf (stderr, "%s: Can't open %s: %s\n",
- cmdname, devicefile, strerror(errno));
- exit(EXIT_FAILURE);
- }
-
- err = ioctl(fd, MEMGETINFO, &mtdinfo);
- if (err < 0) {
- fprintf(stderr, "%s: Cannot get MTD information: %s\n",cmdname,
- strerror(errno));
- exit(EXIT_FAILURE);
- }
-
- if (mtdinfo.type != MTD_NORFLASH && mtdinfo.type != MTD_NANDFLASH) {
- fprintf(stderr, "%s: Unsupported flash type %u\n",
- cmdname, mtdinfo.type);
- exit(EXIT_FAILURE);
- }
-
- if (sectorsize * sectorcount != mtdinfo.size) {
- fprintf(stderr, "%s: Partition size (%d) incompatible with "
- "sector size and count\n", cmdname, mtdinfo.size);
- exit(EXIT_FAILURE);
- }
-
- if (sectorsize * sectoroffset >= mtdinfo.size) {
- fprintf(stderr, "%s: Partition size (%d) incompatible with "
- "sector offset given\n", cmdname, mtdinfo.size);
- exit(EXIT_FAILURE);
- }
-
- if (sectoroffset > sectorcount - 1) {
- fprintf(stderr, "%s: Sector offset cannot be grater than "
- "sector count minus one\n", cmdname);
- exit(EXIT_FAILURE);
- }
-
- printf("Searching....\n");
-
- for (j = sectoroffset; j < sectorcount; ++j) {
-
- if (lseek(fd, j*sectorsize, SEEK_SET) != j*sectorsize) {
- fprintf(stderr, "%s: lseek failure: %s\n",
- cmdname, strerror(errno));
- exit(EXIT_FAILURE);
- }
-
- err = flash_bad_block(fd, mtdinfo.type, j*sectorsize);
- if (err < 0)
- exit(EXIT_FAILURE);
- if (err)
- continue; /* Skip and jump to next */
-
- readbyte = read(fd, buf, sizeof(image_header_t));
- if (readbyte != sizeof(image_header_t)) {
- fprintf(stderr, "%s: Can't read from device: %s\n",
- cmdname, strerror(errno));
- exit(EXIT_FAILURE);
- }
-
- if (fdt_check_header(buf)) {
- /* old-style image */
- if (image_verify_header(buf, fd)) {
- found = 1;
- image_print_contents((image_header_t *)buf);
- }
- } else {
- /* FIT image */
- fit_print_contents(buf);
- }
-
- }
-
- close(fd);
-
- if(!found)
- printf("No images found\n");
-
- exit(EXIT_SUCCESS);
-}
-
-void usage()
-{
- fprintf (stderr, "Usage:\n"
- " %s [-o offset] -s size -c count device\n"
- " -o ==> number of sectors to use as offset\n"
- " -c ==> number of sectors\n"
- " -s ==> size of sectors (byte)\n",
- cmdname);
-
- exit(EXIT_FAILURE);
-}
-
-static int image_verify_header(char *ptr, int fd)
-{
- int len, nread;
- char *data;
- uint32_t checksum;
- image_header_t *hdr = (image_header_t *)ptr;
- char buf[PAGE_SIZE];
-
- if (image_get_magic(hdr) != IH_MAGIC)
- return 0;
-
- data = (char *)hdr;
- len = image_get_header_size();
-
- checksum = image_get_hcrc(hdr);
- hdr->ih_hcrc = htonl(0); /* clear for re-calculation */
-
- if (crc32(0, data, len) != checksum) {
- fprintf(stderr,
- "%s: Maybe image found but it has bad header checksum!\n",
- cmdname);
- return 0;
- }
-
- len = image_get_size(hdr);
- checksum = 0;
-
- while (len > 0) {
- nread = read(fd, buf, MIN(len,PAGE_SIZE));
- if (nread != MIN(len,PAGE_SIZE)) {
- fprintf(stderr,
- "%s: Error while reading: %s\n",
- cmdname, strerror(errno));
- exit(EXIT_FAILURE);
- }
- checksum = crc32(checksum, buf, nread);
- len -= nread;
- }
-
- if (checksum != image_get_dcrc(hdr)) {
- fprintf (stderr,
- "%s: Maybe image found but it has corrupted data!\n",
- cmdname);
- return 0;
- }
-
- return 1;
-}
-
-/*
- * Test for bad block on NAND, just returns 0 on NOR, on NAND:
- * 0 - block is good
- * > 0 - block is bad
- * < 0 - failed to test
- */
-static int flash_bad_block(int fd, uint8_t mtd_type, loff_t start)
-{
- if (mtd_type == MTD_NANDFLASH) {
- int badblock = ioctl(fd, MEMGETBADBLOCK, &start);
-
- if (badblock < 0) {
- fprintf(stderr,"%s: Cannot read bad block mark: %s\n",
- cmdname, strerror(errno));
- return badblock;
- }
-
- if (badblock) {
- return badblock;
- }
- }
-
- return 0;
-}
diff --git a/tools/patman/README b/tools/patman/README
index e6d3070..59f1776 100644
--- a/tools/patman/README
+++ b/tools/patman/README
@@ -180,6 +180,14 @@
together and put after the cover letter. Can appear multiple
times.
+Commit-notes:
+blah blah
+blah blah
+more blah blah
+END
+ Similar, but for a single commit (patch). These notes will appear
+ immediately below the --- cut in the patch file.
+
Signed-off-by: Their Name <email>
A sign-off is added automatically to your patches (this is
probably a bug). If you put this tag in your patches, it will
@@ -227,7 +235,7 @@
Change-Id:
Review URL:
Reviewed-on:
-
+Commit-xxxx: (except Commit-notes)
Exercise for the reader: Try adding some tags to one of your current
patch series and see how the patches turn out.
diff --git a/tools/patman/commit.py b/tools/patman/commit.py
index 900cfb3..89cce7f 100644
--- a/tools/patman/commit.py
+++ b/tools/patman/commit.py
@@ -21,6 +21,7 @@
changes: Dict containing a list of changes (single line strings).
The dict is indexed by change version (an integer)
cc_list: List of people to aliases/emails to cc on this commit
+ notes: List of lines in the commit (not series) notes
"""
def __init__(self, hash):
self.hash = hash
@@ -28,6 +29,7 @@
self.tags = []
self.changes = {}
self.cc_list = []
+ self.notes = []
def AddChange(self, version, info):
"""Add a new change line to the change list for a version.
diff --git a/tools/patman/patchstream.py b/tools/patman/patchstream.py
index c204523..684204c 100644
--- a/tools/patman/patchstream.py
+++ b/tools/patman/patchstream.py
@@ -30,7 +30,10 @@
re_cover_cc = re.compile('^Cover-letter-cc: *(.*)')
# Patch series tag
-re_series = re.compile('^Series-([a-z-]*): *(.*)')
+re_series_tag = re.compile('^Series-([a-z-]*): *(.*)')
+
+# Commit series tag
+re_commit_tag = re.compile('^Commit-([a-z-]*): *(.*)')
# Commit tags that we want to collect and keep
re_tag = re.compile('^(Tested-by|Acked-by|Reviewed-by|Cc): (.*)')
@@ -90,6 +93,20 @@
if self.is_log:
self.series.AddTag(self.commit, line, name, value)
+ def AddToCommit(self, line, name, value):
+ """Add a new Commit-xxx tag.
+
+ When a Commit-xxx tag is detected, we come here to record it.
+
+ Args:
+ line: Source line containing tag (useful for debug/error messages)
+ name: Tag name (part after 'Commit-')
+ value: Tag value (part after 'Commit-xxx: ')
+ """
+ if name == 'notes':
+ self.in_section = 'commit-' + name
+ self.skip_blank = False
+
def CloseCommit(self):
"""Save the current commit into our commit list, and reset our state"""
if self.commit and self.is_log:
@@ -138,7 +155,8 @@
line = line[4:]
# Handle state transition and skipping blank lines
- series_match = re_series.match(line)
+ series_tag_match = re_series_tag.match(line)
+ commit_tag_match = re_commit_tag.match(line)
commit_match = re_commit.match(line) if self.is_log else None
cover_cc_match = re_cover_cc.match(line)
tag_match = None
@@ -165,6 +183,9 @@
elif self.in_section == 'notes':
if self.is_log:
self.series.notes += self.section
+ elif self.in_section == 'commit-notes':
+ if self.is_log:
+ self.commit.notes += self.section
else:
self.warn.append("Unknown section '%s'" % self.in_section)
self.in_section = None
@@ -178,7 +199,7 @@
self.commit.subject = line
# Detect the tags we want to remove, and skip blank lines
- elif re_remove.match(line):
+ elif re_remove.match(line) and not commit_tag_match:
self.skip_blank = True
# TEST= should be the last thing in the commit, so remove
@@ -211,9 +232,9 @@
self.skip_blank = False
# Detect Series-xxx tags
- elif series_match:
- name = series_match.group(1)
- value = series_match.group(2)
+ elif series_tag_match:
+ name = series_tag_match.group(1)
+ value = series_tag_match.group(2)
if name == 'changes':
# value is the version number: e.g. 1, or 2
try:
@@ -226,6 +247,14 @@
self.AddToSeries(line, name, value)
self.skip_blank = True
+ # Detect Commit-xxx tags
+ elif commit_tag_match:
+ name = commit_tag_match.group(1)
+ value = commit_tag_match.group(2)
+ if name == 'notes':
+ self.AddToCommit(line, name, value)
+ self.skip_blank = True
+
# Detect the start of a new commit
elif commit_match:
self.CloseCommit()
@@ -276,7 +305,7 @@
out = []
log = self.series.MakeChangeLog(self.commit)
out += self.FormatTags(self.tags)
- out += [line] + log
+ out += [line] + self.commit.notes + [''] + log
elif self.found_test:
if not re_allowed_after_test.match(line):
self.lines_after_test += 1
diff --git a/tools/updater/Makefile b/tools/updater/Makefile
deleted file mode 100644
index 19dd5eb..0000000
--- a/tools/updater/Makefile
+++ /dev/null
@@ -1,89 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-LOAD_ADDR = 0x40000
-
-include $(TOPDIR)/config.mk
-
-PROG = $(obj)updater
-IMAGE = $(obj)updater.image
-
-COBJS = update.o flash.o flash_hw.o utils.o cmd_flash.o string.o ctype.o dummy.o
-COBJS_LINKS = stubs.o
-AOBJS = ppcstring.o
-AOBJS_LINKS = memio.o
-
-OBJS := $(addprefix $(obj),$(COBJS) $(COBJS_LINKS) $(AOBJS) $(AOBJS_LINKS))
-SRCS := $(COBJS:.o=.c) $(AOBJS:.o=.S) $(addprefix $(obj), $(COBJS_LINKS:.o:.c) $(AOBJS_LINKS:.o:.S))
-
-CPPFLAGS += -I$(TOPDIR) -I$(TOPDIR)/board/MAI/AmigaOneG3SE
-CFLAGS += -I$(TOPDIR)/board/MAI/AmigaOneG3SE
-AFLAGS += -I$(TOPDIR)/board/MAI/AmigaOneG3SE
-
-DEPS = $(OBJTREE)/u-boot.bin $(OBJTREE)/tools/mkimage
-ifneq ($(DEPS),$(wildcard $(DEPS)))
-$(error "updater: Missing required objects, please run regular build first")
-endif
-
-all: $(obj).depend $(PROG) $(IMAGE)
-
-#########################################################################
-
-$(obj)%.srec: %.o $(LIB)
- $(LD) -g -Ttext $(LOAD_ADDR) -o $(<:.o=) -e $(<:.o=) $< $(LIB)
- $(OBJCOPY) -O srec $(<:.o=) $@
-
-$(obj)%.o: %.c
- $(CC) $(CFLAGS) -c -o $@ $<
-
-$(obj)%.o: %.S
- $(CC) $(AFLAGS) -c -o $@ $<
-
-$(obj)memio.o: $(obj)memio.S
- $(CC) $(AFLAGS) -c -o $@ $<
-
-$(obj)memio.S:
- rm -f $(obj)memio.c
- ln -s $(SRCTREE)/board/MAI/AmigaOneG3SE/memio.S $(obj)memio.S
-
-$(obj)stubs.o: $(obj)stubs.c
- $(CC) $(CFLAGS) -c -o $@ $<
-
-$(obj)stubs.c:
- rm -f $(obj)stubs.c
- ln -s $(SRCTREE)/examples/stubs.c $(obj)stubs.c
-
-#########################################################################
-
-$(obj)updater: $(OBJS)
- $(LD) -g -Ttext $(LOAD_ADDR) -o $(obj)updater -e _main $(OBJS)
- $(OBJCOPY) -O binary $(obj)updater $(obj)updater.bin
-
-$(obj)updater.image: $(obj)updater $(OBJTREE)/u-boot.bin
- cat >/tmp/tempimage $(obj)updater.bin junk $(OBJTREE)/u-boot.bin
- $(OBJTREE)/tools/mkimage -A ppc -O u-boot -T standalone -C none -a $(LOAD_ADDR) \
- -e `$(NM) $(obj)updater | grep _main | cut --bytes=0-8` \
- -n "Firmware Updater" -d /tmp/tempimage $(obj)updater.image
- rm /tmp/tempimage
- cp $(obj)updater.image /tftpboot
-
-(obj)updater.image2: $(obj)updater $(OBJTREE)/u-boot.bin
- cat >/tmp/tempimage $(obj)updater.bin junk ../../create_image/image
- $(OBJTREE)/tools/mkimage -A ppc -O u-boot -T standalone -C none -a $(LOAD_ADDR) \
- -e `$(NM) $(obj)updater | grep _main | cut --bytes=0-8` \
- -n "Firmware Updater" -d /tmp/tempimage $(obj)updater.image
- rm /tmp/tempimage
- cp $(obj)updater.image /tftpboot
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/tools/updater/cmd_flash.c b/tools/updater/cmd_flash.c
deleted file mode 100644
index 3a604d0..0000000
--- a/tools/updater/cmd_flash.c
+++ /dev/null
@@ -1,401 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * FLASH support
- */
-#include <common.h>
-#include <command.h>
-#include <flash.h>
-
-#if defined(CONFIG_CMD_FLASH)
-
-extern flash_info_t flash_info[]; /* info for FLASH chips */
-
-/*
- * The user interface starts numbering for Flash banks with 1
- * for historical reasons.
- */
-
-/*
- * this routine looks for an abbreviated flash range specification.
- * the syntax is B:SF[-SL], where B is the bank number, SF is the first
- * sector to erase, and SL is the last sector to erase (defaults to SF).
- * bank numbers start at 1 to be consistent with other specs, sector numbers
- * start at zero.
- *
- * returns: 1 - correct spec; *pinfo, *psf and *psl are
- * set appropriately
- * 0 - doesn't look like an abbreviated spec
- * -1 - looks like an abbreviated spec, but got
- * a parsing error, a number out of range,
- * or an invalid flash bank.
- */
-static int
-abbrev_spec(char *str, flash_info_t **pinfo, int *psf, int *psl)
-{
- flash_info_t *fp;
- int bank, first, last;
- char *p, *ep;
-
- if ((p = strchr(str, ':')) == NULL)
- return 0;
- *p++ = '\0';
-
- bank = simple_strtoul(str, &ep, 10);
- if (ep == str || *ep != '\0' ||
- bank < 1 || bank > CONFIG_SYS_MAX_FLASH_BANKS ||
- (fp = &flash_info[bank - 1])->flash_id == FLASH_UNKNOWN)
- return -1;
-
- str = p;
- if ((p = strchr(str, '-')) != NULL)
- *p++ = '\0';
-
- first = simple_strtoul(str, &ep, 10);
- if (ep == str || *ep != '\0' || first >= fp->sector_count)
- return -1;
-
- if (p != NULL) {
- last = simple_strtoul(p, &ep, 10);
- if (ep == p || *ep != '\0' ||
- last < first || last >= fp->sector_count)
- return -1;
- }
- else
- last = first;
-
- *pinfo = fp;
- *psf = first;
- *psl = last;
-
- return 1;
-}
-int do_flinfo (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
-{
- ulong bank;
-
- if (argc == 1) { /* print info for all FLASH banks */
- for (bank=0; bank <CONFIG_SYS_MAX_FLASH_BANKS; ++bank) {
- printf ("\nBank # %ld: ", bank+1);
-
- flash_print_info (&flash_info[bank]);
- }
- return 0;
- }
-
- bank = simple_strtoul(argv[1], NULL, 16);
- if ((bank < 1) || (bank > CONFIG_SYS_MAX_FLASH_BANKS)) {
- printf ("Only FLASH Banks # 1 ... # %d supported\n",
- CONFIG_SYS_MAX_FLASH_BANKS);
- return 1;
- }
- printf ("\nBank # %ld: ", bank);
- flash_print_info (&flash_info[bank-1]);
- return 0;
-}
-int do_flerase(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
-{
- flash_info_t *info;
- ulong bank, addr_first, addr_last;
- int n, sect_first, sect_last;
- int rcode = 0;
-
- if (argc < 2)
- return cmd_usage(cmdtp);
-
- if (strcmp(argv[1], "all") == 0) {
- for (bank=1; bank<=CONFIG_SYS_MAX_FLASH_BANKS; ++bank) {
- printf ("Erase Flash Bank # %ld ", bank);
- info = &flash_info[bank-1];
- rcode = flash_erase (info, 0, info->sector_count-1);
- }
- return rcode;
- }
-
- if ((n = abbrev_spec(argv[1], &info, §_first, §_last)) != 0) {
- if (n < 0) {
- printf("Bad sector specification\n");
- return 1;
- }
- printf ("Erase Flash Sectors %d-%d in Bank # %d ",
- sect_first, sect_last, (info-flash_info)+1);
- rcode = flash_erase(info, sect_first, sect_last);
- return rcode;
- }
-
- if (argc != 3)
- return cmd_usage(cmdtp);
-
- if (strcmp(argv[1], "bank") == 0) {
- bank = simple_strtoul(argv[2], NULL, 16);
- if ((bank < 1) || (bank > CONFIG_SYS_MAX_FLASH_BANKS)) {
- printf ("Only FLASH Banks # 1 ... # %d supported\n",
- CONFIG_SYS_MAX_FLASH_BANKS);
- return 1;
- }
- printf ("Erase Flash Bank # %ld ", bank);
- info = &flash_info[bank-1];
- rcode = flash_erase (info, 0, info->sector_count-1);
- return rcode;
- }
-
- addr_first = simple_strtoul(argv[1], NULL, 16);
- addr_last = simple_strtoul(argv[2], NULL, 16);
-
- if (addr_first >= addr_last)
- return cmd_usage(cmdtp);
-
- printf ("Erase Flash from 0x%08lx to 0x%08lx ", addr_first, addr_last);
- rcode = flash_sect_erase(addr_first, addr_last);
- return rcode;
-}
-
-int flash_sect_erase (ulong addr_first, ulong addr_last)
-{
- flash_info_t *info;
- ulong bank;
- int s_first, s_last;
- int erased;
- int rcode = 0;
-
- erased = 0;
-
- for (bank=0,info = &flash_info[0]; bank < CONFIG_SYS_MAX_FLASH_BANKS; ++bank, ++info) {
- ulong b_end;
- int sect;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- continue;
- }
-
- b_end = info->start[0] + info->size - 1; /* bank end addr */
-
- s_first = -1; /* first sector to erase */
- s_last = -1; /* last sector to erase */
-
- for (sect=0; sect < info->sector_count; ++sect) {
- ulong end; /* last address in current sect */
- short s_end;
-
- s_end = info->sector_count - 1;
-
- end = (sect == s_end) ? b_end : info->start[sect + 1] - 1;
-
- if (addr_first > end)
- continue;
- if (addr_last < info->start[sect])
- continue;
-
- if (addr_first == info->start[sect]) {
- s_first = sect;
- }
- if (addr_last == end) {
- s_last = sect;
- }
- }
- if (s_first>=0 && s_first<=s_last) {
- erased += s_last - s_first + 1;
- rcode = flash_erase (info, s_first, s_last);
- }
- }
- if (erased) {
- /* printf ("Erased %d sectors\n", erased); */
- } else {
- printf ("Error: start and/or end address"
- " not on sector boundary\n");
- rcode = 1;
- }
- return rcode;
-}
-
-
-int do_protect(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
-{
- flash_info_t *info;
- ulong bank, addr_first, addr_last;
- int i, p, n, sect_first, sect_last;
- int rcode = 0;
-
- if (argc < 3)
- return cmd_usage(cmdtp);
-
- if (strcmp(argv[1], "off") == 0)
- p = 0;
- else if (strcmp(argv[1], "on") == 0)
- p = 1;
- else
- return cmd_usage(cmdtp);
-
- if (strcmp(argv[2], "all") == 0) {
- for (bank=1; bank<=CONFIG_SYS_MAX_FLASH_BANKS; ++bank) {
- info = &flash_info[bank-1];
- if (info->flash_id == FLASH_UNKNOWN) {
- continue;
- }
- /*printf ("%sProtect Flash Bank # %ld\n", */
- /* p ? "" : "Un-", bank); */
-
- for (i=0; i<info->sector_count; ++i) {
-#if defined(CONFIG_SYS_FLASH_PROTECTION)
- if (flash_real_protect(info, i, p))
- rcode = 1;
- putc ('.');
-#else
- info->protect[i] = p;
-#endif /* CONFIG_SYS_FLASH_PROTECTION */
- }
- }
-
-#if defined(CONFIG_SYS_FLASH_PROTECTION)
- if (!rcode) puts (" done\n");
-#endif /* CONFIG_SYS_FLASH_PROTECTION */
-
- return rcode;
- }
-
- if ((n = abbrev_spec(argv[2], &info, §_first, §_last)) != 0) {
- if (n < 0) {
- printf("Bad sector specification\n");
- return 1;
- }
- /*printf("%sProtect Flash Sectors %d-%d in Bank # %d\n", */
- /* p ? "" : "Un-", sect_first, sect_last, */
- /* (info-flash_info)+1); */
- for (i = sect_first; i <= sect_last; i++) {
-#if defined(CONFIG_SYS_FLASH_PROTECTION)
- if (flash_real_protect(info, i, p))
- rcode = 1;
- putc ('.');
-#else
- info->protect[i] = p;
-#endif /* CONFIG_SYS_FLASH_PROTECTION */
- }
-
-#if defined(CONFIG_SYS_FLASH_PROTECTION)
- if (!rcode) puts (" done\n");
-#endif /* CONFIG_SYS_FLASH_PROTECTION */
-
- return rcode;
- }
-
- if (argc != 4)
- return cmd_usage(cmdtp);
-
- if (strcmp(argv[2], "bank") == 0) {
- bank = simple_strtoul(argv[3], NULL, 16);
- if ((bank < 1) || (bank > CONFIG_SYS_MAX_FLASH_BANKS)) {
- printf ("Only FLASH Banks # 1 ... # %d supported\n",
- CONFIG_SYS_MAX_FLASH_BANKS);
- return 1;
- }
- printf ("%sProtect Flash Bank # %ld\n",
- p ? "" : "Un-", bank);
- info = &flash_info[bank-1];
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return 1;
- }
- for (i=0; i<info->sector_count; ++i) {
-#if defined(CONFIG_SYS_FLASH_PROTECTION)
- if (flash_real_protect(info, i, p))
- rcode = 1;
- putc ('.');
-#else
- info->protect[i] = p;
-#endif /* CONFIG_SYS_FLASH_PROTECTION */
- }
-
-#if defined(CONFIG_SYS_FLASH_PROTECTION)
- if (!rcode)
- puts(" done\n");
-#endif /* CONFIG_SYS_FLASH_PROTECTION */
-
- return rcode;
- }
-
- addr_first = simple_strtoul(argv[2], NULL, 16);
- addr_last = simple_strtoul(argv[3], NULL, 16);
-
- if (addr_first >= addr_last)
- return cmd_usage(cmdtp);
-
- return flash_sect_protect (p, addr_first, addr_last);
-}
-int flash_sect_protect (int p, ulong addr_first, ulong addr_last)
-{
- flash_info_t *info;
- ulong bank;
- int s_first, s_last;
- int protected, i;
- int rcode = 0;
-
- protected = 0;
-
- for (bank=0,info = &flash_info[0]; bank < CONFIG_SYS_MAX_FLASH_BANKS; ++bank, ++info) {
- ulong b_end;
- int sect;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- continue;
- }
-
- b_end = info->start[0] + info->size - 1; /* bank end addr */
-
- s_first = -1; /* first sector to erase */
- s_last = -1; /* last sector to erase */
-
- for (sect=0; sect < info->sector_count; ++sect) {
- ulong end; /* last address in current sect */
- short s_end;
-
- s_end = info->sector_count - 1;
-
- end = (sect == s_end) ? b_end : info->start[sect + 1] - 1;
-
- if (addr_first > end)
- continue;
- if (addr_last < info->start[sect])
- continue;
-
- if (addr_first == info->start[sect]) {
- s_first = sect;
- }
- if (addr_last == end) {
- s_last = sect;
- }
- }
- if (s_first>=0 && s_first<=s_last) {
- protected += s_last - s_first + 1;
- for (i=s_first; i<=s_last; ++i) {
-#if defined(CONFIG_SYS_FLASH_PROTECTION)
- if (flash_real_protect(info, i, p))
- rcode = 1;
- putc ('.');
-#else
- info->protect[i] = p;
-#endif /* CONFIG_SYS_FLASH_PROTECTION */
- }
- }
-#if defined(CONFIG_SYS_FLASH_PROTECTION)
- if (!rcode) putc ('\n');
-#endif /* CONFIG_SYS_FLASH_PROTECTION */
-
- }
- if (protected) {
- /* printf ("%sProtected %d sectors\n", */
- /* p ? "" : "Un-", protected); */
- } else {
- printf ("Error: start and/or end address"
- " not on sector boundary\n");
- rcode = 1;
- }
- return rcode;
-}
-
-#endif
diff --git a/tools/updater/ctype.c b/tools/updater/ctype.c
deleted file mode 100644
index 96fa9ed..0000000
--- a/tools/updater/ctype.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * linux/lib/ctype.c
- *
- * Copyright (C) 1991, 1992 Linus Torvalds
- */
-
-#include <linux/ctype.h>
-
-unsigned char _ctype[] = {
-_C,_C,_C,_C,_C,_C,_C,_C, /* 0-7 */
-_C,_C|_S,_C|_S,_C|_S,_C|_S,_C|_S,_C,_C, /* 8-15 */
-_C,_C,_C,_C,_C,_C,_C,_C, /* 16-23 */
-_C,_C,_C,_C,_C,_C,_C,_C, /* 24-31 */
-_S|_SP,_P,_P,_P,_P,_P,_P,_P, /* 32-39 */
-_P,_P,_P,_P,_P,_P,_P,_P, /* 40-47 */
-_D,_D,_D,_D,_D,_D,_D,_D, /* 48-55 */
-_D,_D,_P,_P,_P,_P,_P,_P, /* 56-63 */
-_P,_U|_X,_U|_X,_U|_X,_U|_X,_U|_X,_U|_X,_U, /* 64-71 */
-_U,_U,_U,_U,_U,_U,_U,_U, /* 72-79 */
-_U,_U,_U,_U,_U,_U,_U,_U, /* 80-87 */
-_U,_U,_U,_P,_P,_P,_P,_P, /* 88-95 */
-_P,_L|_X,_L|_X,_L|_X,_L|_X,_L|_X,_L|_X,_L, /* 96-103 */
-_L,_L,_L,_L,_L,_L,_L,_L, /* 104-111 */
-_L,_L,_L,_L,_L,_L,_L,_L, /* 112-119 */
-_L,_L,_L,_P,_P,_P,_P,_C, /* 120-127 */
-0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 128-143 */
-0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 144-159 */
-_S|_SP,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P, /* 160-175 */
-_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P, /* 176-191 */
-_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U, /* 192-207 */
-_U,_U,_U,_U,_U,_U,_U,_P,_U,_U,_U,_U,_U,_U,_U,_L, /* 208-223 */
-_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L, /* 224-239 */
-_L,_L,_L,_L,_L,_L,_L,_P,_L,_L,_L,_L,_L,_L,_L,_L}; /* 240-255 */
diff --git a/tools/updater/dummy.c b/tools/updater/dummy.c
deleted file mode 100644
index 9fe5ac1..0000000
--- a/tools/updater/dummy.c
+++ /dev/null
@@ -1 +0,0 @@
-volatile int __dummy = 0xDEADBEEF;
diff --git a/tools/updater/flash.c b/tools/updater/flash.c
deleted file mode 100644
index 5388872..0000000
--- a/tools/updater/flash.c
+++ /dev/null
@@ -1,168 +0,0 @@
-/*
- * (C) Copyright 2000-2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <flash.h>
-
-extern flash_info_t flash_info[]; /* info for FLASH chips */
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-
-/*-----------------------------------------------------------------------
- * Set protection status for monitor sectors
- *
- * The monitor is always located in the _first_ Flash bank.
- * If necessary you have to map the second bank at lower addresses.
- */
-void
-flash_protect (int flag, ulong from, ulong to, flash_info_t *info)
-{
- ulong b_end = info->start[0] + info->size - 1; /* bank end address */
- short s_end = info->sector_count - 1; /* index of last sector */
- int i;
-
- /* Do nothing if input data is bad. */
- if (info->sector_count == 0 || info->size == 0 || to < from) {
- return;
- }
-
- /* There is nothing to do if we have no data about the flash
- * or the protect range and flash range don't overlap.
- */
- if (info->flash_id == FLASH_UNKNOWN ||
- to < info->start[0] || from > b_end) {
- return;
- }
-
- for (i=0; i<info->sector_count; ++i) {
- ulong end; /* last address in current sect */
-
- end = (i == s_end) ? b_end : info->start[i + 1] - 1;
-
- /* Update protection if any part of the sector
- * is in the specified range.
- */
- if (from <= end && to >= info->start[i]) {
- if (flag & FLAG_PROTECT_CLEAR) {
-#if defined(CONFIG_SYS_FLASH_PROTECTION)
- flash_real_protect(info, i, 0);
-#else
- info->protect[i] = 0;
-#endif /* CONFIG_SYS_FLASH_PROTECTION */
- }
- else if (flag & FLAG_PROTECT_SET) {
-#if defined(CONFIG_SYS_FLASH_PROTECTION)
- flash_real_protect(info, i, 1);
-#else
- info->protect[i] = 1;
-#endif /* CONFIG_SYS_FLASH_PROTECTION */
- }
- }
- }
-}
-
-/*-----------------------------------------------------------------------
- */
-
-flash_info_t *
-addr2info (ulong addr)
-{
-#ifndef CONFIG_SPD823TS
- flash_info_t *info;
- int i;
-
- for (i=0, info = &flash_info[0]; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i, ++info) {
- if (info->flash_id != FLASH_UNKNOWN &&
- addr >= info->start[0] &&
- /* WARNING - The '- 1' is needed if the flash
- * is at the end of the address space, since
- * info->start[0] + info->size wraps back to 0.
- * Please don't change this unless you understand this.
- */
- addr <= info->start[0] + info->size - 1) {
- return (info);
- }
- }
-#endif /* CONFIG_SPD823TS */
-
- return (NULL);
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash.
- * Make sure all target addresses are within Flash bounds,
- * and no protected sectors are hit.
- * Returns:
- * ERR_OK 0 - OK
- * ERR_TIMOUT 1 - write timeout
- * ERR_NOT_ERASED 2 - Flash not erased
- * ERR_PROTECTED 4 - target range includes protected sectors
- * ERR_INVAL 8 - target address not in Flash memory
- * ERR_ALIGN 16 - target address not aligned on boundary
- * (only some targets require alignment)
- */
-int
-flash_write (char *src, ulong addr, ulong cnt)
-{
-#ifdef CONFIG_SPD823TS
- return (ERR_TIMOUT); /* any other error codes are possible as well */
-#else
- int i;
- ulong end = addr + cnt - 1;
- flash_info_t *info_first = addr2info (addr);
- flash_info_t *info_last = addr2info (end );
- flash_info_t *info;
- int j;
-
- if (cnt == 0) {
- return (ERR_OK);
- }
-
- if (!info_first || !info_last) {
- return (ERR_INVAL);
- }
-
- for (info = info_first; info <= info_last; ++info) {
- ulong b_end = info->start[0] + info->size; /* bank end addr */
- short s_end = info->sector_count - 1;
- for (i=0; i<info->sector_count; ++i) {
- ulong e_addr = (i == s_end) ? b_end : info->start[i + 1];
-
- if ((end >= info->start[i]) && (addr < e_addr) &&
- (info->protect[i] != 0) ) {
- return (ERR_PROTECTED);
- }
- }
- }
-
- printf("\rWriting ");
- for (j=0; j<20; j++) putc(177);
- printf("\rWriting ");
-
- /* finally write data to flash */
- for (info = info_first; info <= info_last && cnt>0; ++info) {
- ulong len;
-
- len = info->start[0] + info->size - addr;
- if (len > cnt)
- len = cnt;
-
- if ((i = write_buff(info, src, addr, len)) != 0) {
- return (i);
- }
- cnt -= len;
- addr += len;
- src += len;
- }
- return (ERR_OK);
-#endif /* CONFIG_SPD823TS */
-}
-
-/*-----------------------------------------------------------------------
- */
diff --git a/tools/updater/flash_hw.c b/tools/updater/flash_hw.c
deleted file mode 100644
index 54a910b..0000000
--- a/tools/updater/flash_hw.c
+++ /dev/null
@@ -1,643 +0,0 @@
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <flash.h>
-#include <asm/io.h>
-#include <memio.h>
-
-/*---------------------------------------------------------------------*/
-#undef DEBUG_FLASH
-
-#ifdef DEBUG_FLASH
-#define DEBUGF(fmt,args...) printf(fmt ,##args)
-#else
-#define DEBUGF(fmt,args...)
-#endif
-/*---------------------------------------------------------------------*/
-
-flash_info_t flash_info[];
-
-static ulong flash_get_size (ulong addr, flash_info_t *info);
-static int flash_get_offsets (ulong base, flash_info_t *info);
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-static void flash_reset (ulong addr);
-
-int flash_xd_nest;
-
-static void flash_to_xd(void)
-{
- unsigned char x;
-
- flash_xd_nest ++;
-
- if (flash_xd_nest == 1)
- {
- DEBUGF("Flash on XD\n");
- x = pci_read_cfg_byte(0, 0, 0x74);
- pci_write_cfg_byte(0, 0, 0x74, x|1);
- }
-}
-
-static void flash_to_mem(void)
-{
- unsigned char x;
-
- flash_xd_nest --;
-
- if (flash_xd_nest == 0)
- {
- DEBUGF("Flash on memory bus\n");
- x = pci_read_cfg_byte(0, 0, 0x74);
- pci_write_cfg_byte(0, 0, 0x74, x&0xFE);
- }
-}
-
-unsigned long flash_init_old(void)
-{
- int i;
-
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
- {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- flash_info[i].sector_count = 0;
- flash_info[i].size = 0;
- }
-
-
- return 1;
-}
-
-unsigned long flash_init (void)
-{
- unsigned int i;
- unsigned long flash_size = 0;
-
- flash_xd_nest = 0;
-
- flash_to_xd();
-
- /* Init: no FLASHes known */
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- flash_info[i].sector_count = 0;
- flash_info[i].size = 0;
- }
-
- DEBUGF("\n## Get flash size @ 0x%08x\n", CONFIG_SYS_FLASH_BASE);
-
- flash_size = flash_get_size (CONFIG_SYS_FLASH_BASE, flash_info);
-
- DEBUGF("## Flash bank size: %08lx\n", flash_size);
-
- if (flash_size) {
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE && \
- CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_MAX_SIZE
- /* monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
- &flash_info[0]);
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
- /* ENV protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
- &flash_info[0]);
-#endif
-
- } else {
- printf ("Warning: the BOOT Flash is not initialised !");
- }
-
- flash_to_mem();
-
- return flash_size;
-}
-
-/*
- * The following code cannot be run from FLASH!
- */
-static ulong flash_get_size (ulong addr, flash_info_t *info)
-{
- short i;
- uchar value;
- uchar *x = (uchar *)addr;
-
- flash_to_xd();
-
- /* Write auto select command: read Manufacturer ID */
- x[0x0555] = 0xAA;
- __asm__ volatile ("sync\n eieio");
- x[0x02AA] = 0x55;
- __asm__ volatile ("sync\n eieio");
- x[0x0555] = 0x90;
- __asm__ volatile ("sync\n eieio");
-
- value = x[0];
- __asm__ volatile ("sync\n eieio");
-
- DEBUGF("Manuf. ID @ 0x%08lx: 0x%08x\n", (ulong)addr, value);
-
- switch (value | (value << 16)) {
- case AMD_MANUFACT:
- info->flash_id = FLASH_MAN_AMD;
- break;
-
- case FUJ_MANUFACT:
- info->flash_id = FLASH_MAN_FUJ;
- break;
-
- case STM_MANUFACT:
- info->flash_id = FLASH_MAN_STM;
- break;
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- flash_reset (addr);
- return 0;
- }
-
- value = x[1];
- __asm__ volatile ("sync\n eieio");
-
- DEBUGF("Device ID @ 0x%08lx: 0x%08x\n", addr+1, value);
-
- switch (value) {
- case AMD_ID_F040B:
- DEBUGF("Am29F040B\n");
- info->flash_id += FLASH_AM040;
- info->sector_count = 8;
- info->size = 0x00080000;
- break; /* => 512 kB */
-
- case AMD_ID_LV040B:
- DEBUGF("Am29LV040B\n");
- info->flash_id += FLASH_AM040;
- info->sector_count = 8;
- info->size = 0x00080000;
- break; /* => 512 kB */
-
- case AMD_ID_LV400T:
- DEBUGF("Am29LV400T\n");
- info->flash_id += FLASH_AM400T;
- info->sector_count = 11;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case AMD_ID_LV400B:
- DEBUGF("Am29LV400B\n");
- info->flash_id += FLASH_AM400B;
- info->sector_count = 11;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case AMD_ID_LV800T:
- DEBUGF("Am29LV800T\n");
- info->flash_id += FLASH_AM800T;
- info->sector_count = 19;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case AMD_ID_LV800B:
- DEBUGF("Am29LV400B\n");
- info->flash_id += FLASH_AM800B;
- info->sector_count = 19;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case AMD_ID_LV160T:
- DEBUGF("Am29LV160T\n");
- info->flash_id += FLASH_AM160T;
- info->sector_count = 35;
- info->size = 0x00400000;
- break; /* => 4 MB */
-
- case AMD_ID_LV160B:
- DEBUGF("Am29LV160B\n");
- info->flash_id += FLASH_AM160B;
- info->sector_count = 35;
- info->size = 0x00400000;
- break; /* => 4 MB */
-
- case AMD_ID_LV320T:
- DEBUGF("Am29LV320T\n");
- info->flash_id += FLASH_AM320T;
- info->sector_count = 67;
- info->size = 0x00800000;
- break; /* => 8 MB */
-
-#if 0
- /* Has the same ID as AMD_ID_LV320T, to be fixed */
- case AMD_ID_LV320B:
- DEBUGF("Am29LV320B\n");
- info->flash_id += FLASH_AM320B;
- info->sector_count = 67;
- info->size = 0x00800000;
- break; /* => 8 MB */
-#endif
-
- case AMD_ID_LV033C:
- DEBUGF("Am29LV033C\n");
- info->flash_id += FLASH_AM033C;
- info->sector_count = 64;
- info->size = 0x01000000;
- break; /* => 16Mb */
-
- case STM_ID_F040B:
- DEBUGF("M29F040B\n");
- info->flash_id += FLASH_AM040;
- info->sector_count = 8;
- info->size = 0x00080000;
- break; /* => 512 kB */
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- flash_reset (addr);
- flash_to_mem();
- return (0); /* => no or unknown flash */
-
- }
-
- if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
- printf ("** ERROR: sector count %d > max (%d) **\n",
- info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
- info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
- }
-
- if (! flash_get_offsets (addr, info)) {
- flash_reset (addr);
- flash_to_mem();
- return 0;
- }
-
- /* check for protected sectors */
- for (i = 0; i < info->sector_count; i++) {
- /* read sector protection at sector address, (A7 .. A0) = 0x02 */
- /* D0 = 1 if protected */
- value = in8(info->start[i] + 2);
- iobarrier_rw();
- info->protect[i] = (value & 1) != 0;
- }
-
- /*
- * Reset bank to read mode
- */
- flash_reset (addr);
-
- flash_to_mem();
-
- return (info->size);
-}
-
-static int flash_get_offsets (ulong base, flash_info_t *info)
-{
- unsigned int i;
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM040:
- /* set sector offsets for uniform sector type */
- for (i = 0; i < info->sector_count; i++) {
- info->start[i] = base + i * info->size /
- info->sector_count;
- }
- break;
- default:
- return 0;
- }
-
- return 1;
-}
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- volatile ulong addr = info->start[0];
- int flag, prot, sect, l_sect;
- ulong start, now, last;
-
- flash_to_xd();
-
- if (s_first < 0 || s_first > s_last) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- flash_to_mem();
- return 1;
- }
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("Can't erase unknown flash type %08lx - aborted\n",
- info->flash_id);
- flash_to_mem();
- return 1;
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("");
- }
-
- l_sect = -1;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- out8(addr + 0x555, 0xAA);
- iobarrier_rw();
- out8(addr + 0x2AA, 0x55);
- iobarrier_rw();
- out8(addr + 0x555, 0x80);
- iobarrier_rw();
- out8(addr + 0x555, 0xAA);
- iobarrier_rw();
- out8(addr + 0x2AA, 0x55);
- iobarrier_rw();
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- addr = info->start[sect];
- out8(addr, 0x30);
- iobarrier_rw();
- l_sect = sect;
- }
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- /*
- * We wait for the last triggered sector
- */
- if (l_sect < 0)
- goto DONE;
-
- start = get_timer (0);
- last = start;
- addr = info->start[l_sect];
-
- DEBUGF ("Start erase timeout: %d\n", CONFIG_SYS_FLASH_ERASE_TOUT);
-
- while ((in8(addr) & 0x80) != 0x80) {
- if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- flash_reset (info->start[0]);
- flash_to_mem();
- return 1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
- iobarrier_rw();
- }
-
-DONE:
- /* reset to read mode */
- flash_reset (info->start[0]);
- flash_to_mem();
-
- printf (" done\n");
- return 0;
-}
-
-/*
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- ulong cp, wp, data;
- int i, l, rc;
- ulong out_cnt = 0;
-
- flash_to_xd();
-
- wp = (addr & ~3); /* get lower word aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i=0, cp=wp; i<l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
- for (; i<4 && cnt>0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt==0 && i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- if ((rc = write_word(info, wp, data)) != 0) {
- flash_to_mem();
- return (rc);
- }
- wp += 4;
- }
-
- putc(219);
-
- /*
- * handle word aligned part
- */
- while (cnt >= 4) {
- if (out_cnt>26214)
- {
- putc(219);
- out_cnt = 0;
- }
- data = 0;
- for (i=0; i<4; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_word(info, wp, data)) != 0) {
- flash_to_mem();
- return (rc);
- }
- wp += 4;
- cnt -= 4;
- out_cnt += 4;
- }
-
- if (cnt == 0) {
- flash_to_mem();
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- flash_to_mem();
- return (write_word(info, wp, data));
-}
-
-/*
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t *info, ulong dest, ulong data)
-{
- volatile ulong addr = info->start[0];
- ulong start;
- int i;
-
- flash_to_xd();
-
- /* Check if Flash is (sufficiently) erased */
- if ((in32(dest) & data) != data) {
- flash_to_mem();
- return (2);
- }
-
- /* write each byte out */
- for (i = 0; i < 4; i++) {
- char *data_ch = (char *)&data;
- int flag = disable_interrupts();
-
- out8(addr + 0x555, 0xAA);
- iobarrier_rw();
- out8(addr + 0x2AA, 0x55);
- iobarrier_rw();
- out8(addr + 0x555, 0xA0);
- iobarrier_rw();
- out8(dest+i, data_ch[i]);
- iobarrier_rw();
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* data polling for D7 */
- start = get_timer (0);
- while ((in8(dest+i) & 0x80) != (data_ch[i] & 0x80)) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- flash_reset (addr);
- flash_to_mem();
- return (1);
- }
- iobarrier_rw();
- }
- }
-
- flash_reset (addr);
- flash_to_mem();
- return (0);
-}
-
-/*
- * Reset bank to read mode
- */
-static void flash_reset (ulong addr)
-{
- flash_to_xd();
- out8(addr, 0xF0); /* reset bank */
- iobarrier_rw();
- flash_to_mem();
-}
-
-void flash_print_info (flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD: printf ("AMD "); break;
- case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
- case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break;
- case FLASH_MAN_STM: printf ("SGS THOMSON "); break;
- default: printf ("Unknown Vendor "); break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM040: printf ("29F040 or 29LV040 (4 Mbit, uniform sectors)\n");
- break;
- case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n");
- break;
- case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n");
- break;
- case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n");
- break;
- case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n");
- break;
- default: printf ("Unknown Chip Type\n");
- break;
- }
-
- if (info->size % 0x100000 == 0) {
- printf (" Size: %ld MB in %d Sectors\n",
- info->size / 0x100000, info->sector_count);
- } else if (info->size % 0x400 == 0) {
- printf (" Size: %ld KB in %d Sectors\n",
- info->size / 0x400, info->sector_count);
- } else {
- printf (" Size: %ld B in %d Sectors\n",
- info->size, info->sector_count);
- }
-
- printf (" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " "
- );
- }
- printf ("\n");
-}
diff --git a/tools/updater/junk b/tools/updater/junk
deleted file mode 100644
index f73285a..0000000
--- a/tools/updater/junk
+++ /dev/null
@@ -1 +0,0 @@
-................................................................................................................................................................................................................................................................
\ No newline at end of file
diff --git a/tools/updater/ppcstring.S b/tools/updater/ppcstring.S
deleted file mode 100644
index 8152ac9..0000000
--- a/tools/updater/ppcstring.S
+++ /dev/null
@@ -1,213 +0,0 @@
-/*
- * String handling functions for PowerPC.
- *
- * Copyright (C) 1996 Paul Mackerras.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <ppc_asm.tmpl>
-#include <asm/errno.h>
-
- .globl strcpy
-strcpy:
- addi r5,r3,-1
- addi r4,r4,-1
-1: lbzu r0,1(r4)
- cmpwi 0,r0,0
- stbu r0,1(r5)
- bne 1b
- blr
-
- .globl strncpy
-strncpy:
- cmpwi 0,r5,0
- beqlr
- mtctr r5
- addi r6,r3,-1
- addi r4,r4,-1
-1: lbzu r0,1(r4)
- cmpwi 0,r0,0
- stbu r0,1(r6)
- bdnzf 2,1b /* dec ctr, branch if ctr != 0 && !cr0.eq */
- blr
-
- .globl strcat
-strcat:
- addi r5,r3,-1
- addi r4,r4,-1
-1: lbzu r0,1(r5)
- cmpwi 0,r0,0
- bne 1b
- addi r5,r5,-1
-1: lbzu r0,1(r4)
- cmpwi 0,r0,0
- stbu r0,1(r5)
- bne 1b
- blr
-
- .globl strcmp
-strcmp:
- addi r5,r3,-1
- addi r4,r4,-1
-1: lbzu r3,1(r5)
- cmpwi 1,r3,0
- lbzu r0,1(r4)
- subf. r3,r0,r3
- beqlr 1
- beq 1b
- blr
-
- .globl strlen
-strlen:
- addi r4,r3,-1
-1: lbzu r0,1(r4)
- cmpwi 0,r0,0
- bne 1b
- subf r3,r3,r4
- blr
-
- .globl memset
-memset:
- rlwimi r4,r4,8,16,23
- rlwimi r4,r4,16,0,15
- addi r6,r3,-4
- cmplwi 0,r5,4
- blt 7f
- stwu r4,4(r6)
- beqlr
- andi. r0,r6,3
- add r5,r0,r5
- subf r6,r0,r6
- rlwinm r0,r5,32-2,2,31
- mtctr r0
- bdz 6f
-1: stwu r4,4(r6)
- bdnz 1b
-6: andi. r5,r5,3
-7: cmpwi 0,r5,0
- beqlr
- mtctr r5
- addi r6,r6,3
-8: stbu r4,1(r6)
- bdnz 8b
- blr
-
- .globl bcopy
-bcopy:
- mr r6,r3
- mr r3,r4
- mr r4,r6
- b memcpy
-
- .globl memmove
-memmove:
- cmplw 0,r3,r4
- bgt backwards_memcpy
- /* fall through */
-
- .globl memcpy
-memcpy:
- rlwinm. r7,r5,32-3,3,31 /* r0 = r5 >> 3 */
- addi r6,r3,-4
- addi r4,r4,-4
- beq 2f /* if less than 8 bytes to do */
- andi. r0,r6,3 /* get dest word aligned */
- mtctr r7
- bne 5f
-1: lwz r7,4(r4)
- lwzu r8,8(r4)
- stw r7,4(r6)
- stwu r8,8(r6)
- bdnz 1b
- andi. r5,r5,7
-2: cmplwi 0,r5,4
- blt 3f
- lwzu r0,4(r4)
- addi r5,r5,-4
- stwu r0,4(r6)
-3: cmpwi 0,r5,0
- beqlr
- mtctr r5
- addi r4,r4,3
- addi r6,r6,3
-4: lbzu r0,1(r4)
- stbu r0,1(r6)
- bdnz 4b
- blr
-5: subfic r0,r0,4
- mtctr r0
-6: lbz r7,4(r4)
- addi r4,r4,1
- stb r7,4(r6)
- addi r6,r6,1
- bdnz 6b
- subf r5,r0,r5
- rlwinm. r7,r5,32-3,3,31
- beq 2b
- mtctr r7
- b 1b
-
- .globl backwards_memcpy
-backwards_memcpy:
- rlwinm. r7,r5,32-3,3,31 /* r0 = r5 >> 3 */
- add r6,r3,r5
- add r4,r4,r5
- beq 2f
- andi. r0,r6,3
- mtctr r7
- bne 5f
-1: lwz r7,-4(r4)
- lwzu r8,-8(r4)
- stw r7,-4(r6)
- stwu r8,-8(r6)
- bdnz 1b
- andi. r5,r5,7
-2: cmplwi 0,r5,4
- blt 3f
- lwzu r0,-4(r4)
- subi r5,r5,4
- stwu r0,-4(r6)
-3: cmpwi 0,r5,0
- beqlr
- mtctr r5
-4: lbzu r0,-1(r4)
- stbu r0,-1(r6)
- bdnz 4b
- blr
-5: mtctr r0
-6: lbzu r7,-1(r4)
- stbu r7,-1(r6)
- bdnz 6b
- subf r5,r0,r5
- rlwinm. r7,r5,32-3,3,31
- beq 2b
- mtctr r7
- b 1b
-
- .globl memcmp
-memcmp:
- cmpwi 0,r5,0
- ble- 2f
- mtctr r5
- addi r6,r3,-1
- addi r4,r4,-1
-1: lbzu r3,1(r6)
- lbzu r0,1(r4)
- subf. r3,r0,r3
- bdnzt 2,1b
- blr
-2: li r3,0
- blr
-
- .global memchr
-memchr:
- cmpwi 0,r5,0
- ble- 2f
- mtctr r5
- addi r3,r3,-1
-1: lbzu r0,1(r3)
- cmpw 0,r0,r4
- bdnzf 2,1b
- beqlr
-2: li r3,0
- blr
diff --git a/tools/updater/string.c b/tools/updater/string.c
deleted file mode 100644
index 954fb01..0000000
--- a/tools/updater/string.c
+++ /dev/null
@@ -1,340 +0,0 @@
-/*
- * linux/lib/string.c
- *
- * Copyright (C) 1991, 1992 Linus Torvalds
- */
-
-/*
- * stupid library routines.. The optimized versions should generally be found
- * as inline code in <asm-xx/string.h>
- *
- * These are buggy as well..
- */
-
-#include <linux/types.h>
-#include <linux/string.h>
-#include <malloc.h>
-
-#define __HAVE_ARCH_BCOPY
-#define __HAVE_ARCH_MEMCMP
-#define __HAVE_ARCH_MEMCPY
-#define __HAVE_ARCH_MEMMOVE
-#define __HAVE_ARCH_MEMSET
-#define __HAVE_ARCH_STRCAT
-#define __HAVE_ARCH_STRCMP
-#define __HAVE_ARCH_STRCPY
-#define __HAVE_ARCH_STRLEN
-#define __HAVE_ARCH_STRNCPY
-
-char * ___strtok = NULL;
-
-#ifndef __HAVE_ARCH_STRCPY
-char * strcpy(char * dest,const char *src)
-{
- char *tmp = dest;
-
- while ((*dest++ = *src++) != '\0')
- /* nothing */;
- return tmp;
-}
-#endif
-
-#ifndef __HAVE_ARCH_STRNCPY
-char * strncpy(char * dest,const char *src,size_t count)
-{
- char *tmp = dest;
-
- while (count-- && (*dest++ = *src++) != '\0')
- /* nothing */;
-
- return tmp;
-}
-#endif
-
-#ifndef __HAVE_ARCH_STRCAT
-char * strcat(char * dest, const char * src)
-{
- char *tmp = dest;
-
- while (*dest)
- dest++;
- while ((*dest++ = *src++) != '\0')
- ;
-
- return tmp;
-}
-#endif
-
-#ifndef __HAVE_ARCH_STRNCAT
-char * strncat(char *dest, const char *src, size_t count)
-{
- char *tmp = dest;
-
- if (count) {
- while (*dest)
- dest++;
- while ((*dest++ = *src++)) {
- if (--count == 0) {
- *dest = '\0';
- break;
- }
- }
- }
-
- return tmp;
-}
-#endif
-
-#ifndef __HAVE_ARCH_STRCMP
-int strcmp(const char * cs,const char * ct)
-{
- register signed char __res;
-
- while (1) {
- if ((__res = *cs - *ct++) != 0 || !*cs++)
- break;
- }
-
- return __res;
-}
-#endif
-
-#ifndef __HAVE_ARCH_STRNCMP
-int strncmp(const char * cs,const char * ct,size_t count)
-{
- register signed char __res = 0;
-
- while (count) {
- if ((__res = *cs - *ct++) != 0 || !*cs++)
- break;
- count--;
- }
-
- return __res;
-}
-#endif
-
-#ifndef __HAVE_ARCH_STRCHR
-char * strchr(const char * s, int c)
-{
- for(; *s != (char) c; ++s)
- if (*s == '\0')
- return NULL;
- return (char *) s;
-}
-#endif
-
-#ifndef __HAVE_ARCH_STRRCHR
-char * strrchr(const char * s, int c)
-{
- const char *p = s + strlen(s);
- do {
- if (*p == (char)c)
- return (char *)p;
- } while (--p >= s);
- return NULL;
-}
-#endif
-
-#ifndef __HAVE_ARCH_STRLEN
-size_t strlen(const char * s)
-{
- const char *sc;
-
- for (sc = s; *sc != '\0'; ++sc)
- /* nothing */;
- return sc - s;
-}
-#endif
-
-#ifndef __HAVE_ARCH_STRNLEN
-size_t strnlen(const char * s, size_t count)
-{
- const char *sc;
-
- for (sc = s; count-- && *sc != '\0'; ++sc)
- /* nothing */;
- return sc - s;
-}
-#endif
-
-#ifndef __HAVE_ARCH_STRDUP
-char * strdup(const char *s)
-{
- char *new;
-
- if ((s == NULL) ||
- ((new = malloc (strlen(s) + 1)) == NULL) ) {
- return NULL;
- }
-
- strcpy (new, s);
- return new;
-}
-#endif
-
-#ifndef __HAVE_ARCH_STRSPN
-size_t strspn(const char *s, const char *accept)
-{
- const char *p;
- const char *a;
- size_t count = 0;
-
- for (p = s; *p != '\0'; ++p) {
- for (a = accept; *a != '\0'; ++a) {
- if (*p == *a)
- break;
- }
- if (*a == '\0')
- return count;
- ++count;
- }
-
- return count;
-}
-#endif
-
-#ifndef __HAVE_ARCH_STRPBRK
-char * strpbrk(const char * cs,const char * ct)
-{
- const char *sc1,*sc2;
-
- for( sc1 = cs; *sc1 != '\0'; ++sc1) {
- for( sc2 = ct; *sc2 != '\0'; ++sc2) {
- if (*sc1 == *sc2)
- return (char *) sc1;
- }
- }
- return NULL;
-}
-#endif
-
-#ifndef __HAVE_ARCH_STRTOK
-char * strtok(char * s,const char * ct)
-{
- char *sbegin, *send;
-
- sbegin = s ? s : ___strtok;
- if (!sbegin) {
- return NULL;
- }
- sbegin += strspn(sbegin,ct);
- if (*sbegin == '\0') {
- ___strtok = NULL;
- return( NULL );
- }
- send = strpbrk( sbegin, ct);
- if (send && *send != '\0')
- *send++ = '\0';
- ___strtok = send;
- return (sbegin);
-}
-#endif
-
-#ifndef __HAVE_ARCH_MEMSET
-void * memset(void * s,char c,size_t count)
-{
- char *xs = (char *) s;
-
- while (count--)
- *xs++ = c;
-
- return s;
-}
-#endif
-
-#ifndef __HAVE_ARCH_BCOPY
-char * bcopy(const char * src, char * dest, int count)
-{
- char *tmp = dest;
-
- while (count--)
- *tmp++ = *src++;
-
- return dest;
-}
-#endif
-
-#ifndef __HAVE_ARCH_MEMCPY
-void * memcpy(void * dest,const void *src,size_t count)
-{
- char *tmp = (char *) dest, *s = (char *) src;
-
- while (count--)
- *tmp++ = *s++;
-
- return dest;
-}
-#endif
-
-#ifndef __HAVE_ARCH_MEMMOVE
-void * memmove(void * dest,const void *src,size_t count)
-{
- char *tmp, *s;
-
- if (dest <= src) {
- tmp = (char *) dest;
- s = (char *) src;
- while (count--)
- *tmp++ = *s++;
- }
- else {
- tmp = (char *) dest + count;
- s = (char *) src + count;
- while (count--)
- *--tmp = *--s;
- }
-
- return dest;
-}
-#endif
-
-#ifndef __HAVE_ARCH_MEMCMP
-int memcmp(const void * cs,const void * ct,size_t count)
-{
- const unsigned char *su1, *su2;
- signed char res = 0;
-
- for( su1 = cs, su2 = ct; 0 < count; ++su1, ++su2, count--)
- if ((res = *su1 - *su2) != 0)
- break;
- return res;
-}
-#endif
-
-/*
- * find the first occurrence of byte 'c', or 1 past the area if none
- */
-#ifndef __HAVE_ARCH_MEMSCAN
-void * memscan(void * addr, int c, size_t size)
-{
- unsigned char * p = (unsigned char *) addr;
-
- while (size) {
- if (*p == c)
- return (void *) p;
- p++;
- size--;
- }
- return (void *) p;
-}
-#endif
-
-#ifndef __HAVE_ARCH_STRSTR
-char * strstr(const char * s1,const char * s2)
-{
- int l1, l2;
-
- l2 = strlen(s2);
- if (!l2)
- return (char *) s1;
- l1 = strlen(s1);
- while (l1 >= l2) {
- l1--;
- if (!memcmp(s1,s2,l2))
- return (char *) s1;
- s1++;
- }
- return NULL;
-}
-#endif
diff --git a/tools/updater/update.c b/tools/updater/update.c
deleted file mode 100644
index 18f122a..0000000
--- a/tools/updater/update.c
+++ /dev/null
@@ -1,63 +0,0 @@
-#include <common.h>
-#include <exports.h>
-
-extern unsigned long __dummy;
-void do_reset (void);
-void do_updater(void);
-
-void _main(void)
-{
- int i;
- printf("U-Boot Firmware Updater\n\n\n");
- printf("****************************************************\n"
- "* ATTENTION!! PLEASE READ THIS NOTICE CAREFULLY! *\n"
- "****************************************************\n\n"
- "This program will update your computer's firmware.\n"
- "Do NOT remove the disk, reset the machine, or do\n"
- "anything that might disrupt functionality. If this\n");
- printf("Program fails, your computer might be unusable, and\n"
- "you will need to return your board for reflashing.\n"
- "If you find this too risky, remove the diskette and\n"
- "switch off your machine now. Otherwise press the \n"
- "SPACE key now to start the process\n\n");
- do
- {
- char x;
- while (!tstc());
- x = getc();
- if (x == ' ') break;
- } while (1);
-
- do_updater();
-
- i = 5;
-
- printf("\nUpdate done. Please remove diskette.\n");
- printf("The machine will automatically reset in %d seconds\n", i);
- printf("You can switch off/reset now when the floppy is removed\n\n");
-
- while (i)
- {
- printf("Resetting in %d\r", i);
- udelay(1000000);
- i--;
- }
- do_reset();
- while (1);
-}
-
-void do_updater(void)
-{
- unsigned long *addr = &__dummy + 65;
- unsigned long flash_size = flash_init();
- int rc;
-
- flash_sect_protect(0, 0xFFF00000, 0xFFF7FFFF);
- printf("Erasing ");
- flash_sect_erase(0xFFF00000, 0xFFF7FFFF);
- printf("Writing ");
- rc = flash_write((uchar *)addr, 0xFFF00000, 0x7FFFF);
- if (rc != 0) printf("\nFlashing failed due to error %d\n", rc);
- else printf("\ndone\n");
- flash_sect_protect(1, 0xFFF00000, 0xFFF7FFFF);
-}
diff --git a/tools/updater/utils.c b/tools/updater/utils.c
deleted file mode 100644
index 61a6118..0000000
--- a/tools/updater/utils.c
+++ /dev/null
@@ -1,148 +0,0 @@
-#include <common.h>
-#include <asm/processor.h>
-#include <memio.h>
-#include <linux/ctype.h>
-
-static __inline__ unsigned long
-get_msr(void)
-{
- unsigned long msr;
-
- asm volatile("mfmsr %0" : "=r" (msr) :);
- return msr;
-}
-
-static __inline__ void
-set_msr(unsigned long msr)
-{
- asm volatile("mtmsr %0" : : "r" (msr));
-}
-
-static __inline__ unsigned long
-get_dec(void)
-{
- unsigned long val;
-
- asm volatile("mfdec %0" : "=r" (val) :);
- return val;
-}
-
-
-static __inline__ void
-set_dec(unsigned long val)
-{
- asm volatile("mtdec %0" : : "r" (val));
-}
-
-
-void
-enable_interrupts(void)
-{
- set_msr (get_msr() | MSR_EE);
-}
-
-/* returns flag if MSR_EE was set before */
-int
-disable_interrupts(void)
-{
- ulong msr;
-
- msr = get_msr();
- set_msr (msr & ~MSR_EE);
- return ((msr & MSR_EE) != 0);
-}
-
-u8 in8(u32 port)
-{
- return in_byte(port);
-}
-
-void out8(u32 port, u8 val)
-{
- out_byte(port, val);
-}
-
-unsigned long in32(u32 port)
-{
- return in_long(port);
-}
-
-unsigned long simple_strtoul(const char *cp,char **endp,unsigned int base)
-{
- unsigned long result = 0,value;
-
- if (*cp == '0') {
- cp++;
- if ((*cp == 'x') && isxdigit(cp[1])) {
- base = 16;
- cp++;
- }
- if (!base) {
- base = 8;
- }
- }
- if (!base) {
- base = 10;
- }
- while (isxdigit(*cp) && (value = isdigit(*cp) ? *cp-'0' : (islower(*cp)
- ? toupper(*cp) : *cp)-'A'+10) < base) {
- result = result*base + value;
- cp++;
- }
- if (endp)
- *endp = (char *)cp;
- return result;
-}
-
-long simple_strtol(const char *cp,char **endp,unsigned int base)
-{
- if(*cp=='-')
- return -simple_strtoul(cp+1,endp,base);
- return simple_strtoul(cp,endp,base);
-}
-
-static inline void
-soft_restart(unsigned long addr)
-{
- /* SRR0 has system reset vector, SRR1 has default MSR value */
- /* rfi restores MSR from SRR1 and sets the PC to the SRR0 value */
-
- __asm__ __volatile__ ("mtspr 26, %0" :: "r" (addr));
- __asm__ __volatile__ ("li 4, (1 << 6)" ::: "r4");
- __asm__ __volatile__ ("mtspr 27, 4");
- __asm__ __volatile__ ("rfi");
-
- while(1); /* not reached */
-}
-
-void
-do_reset (void)
-{
- ulong addr;
- /* flush and disable I/D cache */
- __asm__ __volatile__ ("mfspr 3, 1008" ::: "r3");
- __asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5");
- __asm__ __volatile__ ("ori 4, 3, 0xc00" ::: "r4");
- __asm__ __volatile__ ("andc 5, 3, 5" ::: "r5");
- __asm__ __volatile__ ("sync");
- __asm__ __volatile__ ("mtspr 1008, 4");
- __asm__ __volatile__ ("isync");
- __asm__ __volatile__ ("sync");
- __asm__ __volatile__ ("mtspr 1008, 5");
- __asm__ __volatile__ ("isync");
- __asm__ __volatile__ ("sync");
-
-#ifdef CONFIG_SYS_RESET_ADDRESS
- addr = CONFIG_SYS_RESET_ADDRESS;
-#else
- /*
- * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address,
- * CONFIG_SYS_MONITOR_BASE - sizeof (ulong) is usually a valid
- * address. Better pick an address known to be invalid on your
- * system and assign it to CONFIG_SYS_RESET_ADDRESS.
- */
- addr = CONFIG_SYS_MONITOR_BASE - sizeof (ulong);
-#endif
- soft_restart(addr);
- while(1); /* not reached */
-}