arc: introduce U-Boot port for ARCv2 ISA
ARC HS and ARC EM are new cores based on ARCv2 ISA which is binary
incompatible with ISAv1 (AKA ARCompact).
Significant difference between ISAv2 and v1 is implementation of
interrupt vector table.
In v1 it is implemented in the same way as on many other architectures -
as a special location where user may put whether code executed in place
(if machine word of space is enough) or jump to a full-scale interrupt
handler.
In v2 interrupt table is just an array of adresses of real interrupt
handlers. That requires a separate section for IVT that is not encoded
as code by assembler.
This change adds support for following cores:
* ARC EM6 (simple 32-bit microcontroller without MMU)
* ARC HS36 (advanced 32-bit microcontroller without MMU)
* ARC HS38 (advanced 32-bit microcontroller with MMU)
As a part of ARC HS38 new version of MMU (v4) was introduced.
Also this change adds AXS131 board which is the same DW ARC SDP base board but
with ARC HS38 CPU tile.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index a8dc4e2..24f5c02 100644
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -8,30 +8,79 @@
default y
config SYS_CPU
- default "arcv1"
+ default "arcv1" if ISA_ARCOMPACT
+ default "arcv2" if ISA_ARCV2
+
+choice
+ prompt "ARC Instruction Set"
+ default ISA_ARCOMPACT
+
+config ISA_ARCOMPACT
+ bool "ARCompact ISA"
+ help
+ The original ARC ISA of ARC600/700 cores
+
+config ISA_ARCV2
+ bool "ARC ISA v2"
+ help
+ ISA for the Next Generation ARC-HS cores
+
+endchoice
choice
prompt "CPU selection"
- default CPU_ARC770D
+ default CPU_ARC770D if ISA_ARCOMPACT
+ default CPU_ARCHS38 if ISA_ARCV2
config CPU_ARC750D
bool "ARC 750D"
select ARC_MMU_V2
+ depends on ISA_ARCOMPACT
help
Choose this option to build an U-Boot for ARC750D CPU.
config CPU_ARC770D
bool "ARC 770D"
select ARC_MMU_V3
+ depends on ISA_ARCOMPACT
help
Choose this option to build an U-Boot for ARC770D CPU.
+config CPU_ARCEM6
+ bool "ARC EM6"
+ select ARC_MMU_ABSENT
+ depends on ISA_ARCV2
+ help
+ Next Generation ARC Core based on ISA-v2 ISA without MMU.
+
+config CPU_ARCHS36
+ bool "ARC HS36"
+ select ARC_MMU_ABSENT
+ depends on ISA_ARCV2
+ help
+ Next Generation ARC Core based on ISA-v2 ISA without MMU.
+
+config CPU_ARCHS38
+ bool "ARC HS38"
+ select ARC_MMU_V4
+ depends on ISA_ARCV2
+ help
+ Next Generation ARC Core based on ISA-v2 ISA with MMU.
+
endchoice
choice
prompt "MMU Version"
default ARC_MMU_V3 if CPU_ARC770D
default ARC_MMU_V2 if CPU_ARC750D
+ default ARC_MMU_ABSENT if CPU_ARCEM6
+ default ARC_MMU_ABSENT if CPU_ARCHS36
+ default ARC_MMU_V4 if CPU_ARCHS38
+
+config ARC_MMU_ABSENT
+ bool "No MMU"
+ help
+ No MMU
config ARC_MMU_V2
bool "MMU v2"
@@ -48,6 +97,12 @@
Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
Shared Address Spaces (SASID)
+config ARC_MMU_V4
+ bool "MMU v4"
+ depends on CPU_ARCHS38
+ help
+ Introduced as a part of ARC HS38 release.
+
endchoice
config CPU_BIG_ENDIAN