| commit | ef4cf5ae393e4adf532f536d6da97c87f88db230 | [log] [tgz] |
|---|---|---|
| author | David Wu <david.wu@rock-chips.com> | Wed Sep 20 14:28:19 2017 +0800 |
| committer | Philipp Tomsich <philipp.tomsich@theobroma-systems.com> | Sun Oct 01 00:33:29 2017 +0200 |
| tree | 57fba8ac99e6c10b3ab505c6e8ded1637e850706 | |
| parent | 2e4ce50d1aca35d13944f48a7e15d0b63e86eb38 [diff] |
rockchip: clk: Add SARADC clock support for rk3288 The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1). SARADC integer divider control register is 8-bits width. Signed-off-by: David Wu <david.wu@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>