tree 406d2f16e72d4406d8516fcd1bfb4de330bb3bb9
parent 2519cb344ee7911ab2f6643449f5dcc32cec9653
author York Sun <yorksun@freescale.com> 1414434692 -0700
committer York Sun <yorksun@freescale.com> 1417795568 -0800

mpc85xx/t208xqds: Adjust DDR timing parameters

Adjust timing for dual-rank UDIMM, verified on M3CQ-8GHS3C0E for speed of
1066, 1333, 1600, 1866MT/s. The 1866 timing is copied to 2133 timing in
case such DIMM comes available.

Also update single-rank 1866 timing. Enable interactive debugging as well.

Signed-off-by: York Sun <yorksun@freescale.com>
CC: Shengzhou Liu <Shengzhou.Liu@freescale.com>