powerpc: Enable device tree support for P1020RDB
Add device tree for P1020RDB boards and enable CONFIG_OF_CONTROL
so that device tree can be compiled.
Update board README for device tree usage.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile
index f0d49aa..3a806bd 100644
--- a/arch/powerpc/dts/Makefile
+++ b/arch/powerpc/dts/Makefile
@@ -1,5 +1,7 @@
# SPDX-License-Identifier: GPL-2.0+
+dtb-$(CONFIG_TARGET_P1020RDB_PC) += p1020rdb-pc.dtb p1020rdb-pc_36b.dtb
+dtb-$(CONFIG_TARGET_P1020RDB_PD) += p1020rdb-pd.dtb
dtb-$(CONFIG_TARGET_T1024RDB) += t1024rdb.dtb
dtb-$(CONFIG_TARGET_T1042D4RDB) += t1042d4rdb.dtb
dtb-$(CONFIG_TARGET_T2080QDS) += t2080qds.dtb
diff --git a/arch/powerpc/dts/e500v2_power_isa.dtsi b/arch/powerpc/dts/e500v2_power_isa.dtsi
new file mode 100644
index 0000000..010e8e5
--- /dev/null
+++ b/arch/powerpc/dts/e500v2_power_isa.dtsi
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * e500v2 Power ISA Device Tree Source (include)
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/ {
+ cpus {
+ power-isa-version = "2.03";
+ power-isa-b; // Base
+ power-isa-e; // Embedded
+ power-isa-atb; // Alternate Time Base
+ power-isa-cs; // Cache Specification
+ power-isa-e.le; // Embedded.Little-Endian
+ power-isa-e.pm; // Embedded.Performance Monitor
+ power-isa-ecl; // Embedded Cache Locking
+ power-isa-mmc; // Memory Coherence
+ power-isa-sp; // Signal Processing Engine
+ power-isa-sp.fd; // SPE.Embedded Float Scalar Double
+ power-isa-sp.fs; // SPE.Embedded Float Scalar Single
+ power-isa-sp.fv; // SPE.Embedded Float Vector
+ mmu-type = "power-embedded";
+ };
+};
diff --git a/arch/powerpc/dts/p1020-post.dtsi b/arch/powerpc/dts/p1020-post.dtsi
new file mode 100644
index 0000000..e1a4f50
--- /dev/null
+++ b/arch/powerpc/dts/p1020-post.dtsi
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P1020 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+&soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ compatible = "fsl,p1020-immr", "simple-bus";
+ bus-frequency = <0x0>;
+
+ mpic: pic@40000 {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <4>;
+ reg = <0x40000 0x40000>;
+ compatible = "fsl,mpic";
+ device_type = "open-pic";
+ big-endian;
+ single-cpu-affinity;
+ last-interrupt-source = <255>;
+ };
+};
diff --git a/arch/powerpc/dts/p1020.dtsi b/arch/powerpc/dts/p1020.dtsi
new file mode 100644
index 0000000..ee2b6f4
--- /dev/null
+++ b/arch/powerpc/dts/p1020.dtsi
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P1020 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/dts-v1/;
+
+/include/ "e500v2_power_isa.dtsi"
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&mpic>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: PowerPC,P1020@0 {
+ device_type = "cpu";
+ reg = <0>;
+ };
+ cpu1: PowerPC,P1020@1 {
+ device_type = "cpu";
+ reg = <1>;
+ };
+ };
+};
diff --git a/arch/powerpc/dts/p1020rdb-pc.dts b/arch/powerpc/dts/p1020rdb-pc.dts
new file mode 100644
index 0000000..fd68b8b
--- /dev/null
+++ b/arch/powerpc/dts/p1020rdb-pc.dts
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P1020RDB-PC Device Tree Source
+ *
+ * Copyright 2013 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/include/ "p1020.dtsi"
+
+/ {
+ model = "fsl,P1020RDB-PC";
+ compatible = "fsl,P1020RDB-PC";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&mpic>;
+
+ soc: soc@ffe00000 {
+ ranges = <0x0 0x0 0xffe00000 0x100000>;
+ };
+};
+
+/include/ "p1020-post.dtsi"
diff --git a/arch/powerpc/dts/p1020rdb-pc_36b.dts b/arch/powerpc/dts/p1020rdb-pc_36b.dts
new file mode 100644
index 0000000..a23d031
--- /dev/null
+++ b/arch/powerpc/dts/p1020rdb-pc_36b.dts
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P1020RDB-PC (36-bit address map) Device Tree Source
+ *
+ * Copyright 2013 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/include/ "p1020.dtsi"
+
+/ {
+ model = "fsl,P1020RDB-PC";
+ compatible = "fsl,P1020RDB-PC";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&mpic>;
+
+ soc: soc@fffe00000 {
+ ranges = <0x0 0xf 0xffe00000 0x100000>;
+ };
+};
+
+/include/ "p1020-post.dtsi"
diff --git a/arch/powerpc/dts/p1020rdb-pd.dts b/arch/powerpc/dts/p1020rdb-pd.dts
new file mode 100644
index 0000000..81f25a3
--- /dev/null
+++ b/arch/powerpc/dts/p1020rdb-pd.dts
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P1020RDB-PD Device Tree Source
+ *
+ * Copyright 2013 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/include/ "p1020.dtsi"
+
+/ {
+ model = "fsl,P1020RDB-PD";
+ compatible = "fsl,P1020RDB-PD";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&mpic>;
+
+ soc: soc@ffe00000 {
+ ranges = <0x0 0x0 0xffe00000 0x100000>;
+ };
+};
+
+/include/ "p1020-post.dtsi"