ARM: dts: aspeed: Add AST2600 SoC support
AST2600 is the 7th generation of Aspeed SoC designated for
Interated Remote Management Processor.
AST2600 has significant performance improvement by integrating
1.2GHz dual-core ARM Cortex A7 (r0p5) CPU with FPU. Most of the
controllers are also improved with more features and better
performance than preceding AST24xx/AST25xx.
Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
diff --git a/arch/arm/dts/ast2600-u-boot.dtsi b/arch/arm/dts/ast2600-u-boot.dtsi
new file mode 100644
index 0000000..4648c07
--- /dev/null
+++ b/arch/arm/dts/ast2600-u-boot.dtsi
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0+
+#include <dt-bindings/clock/ast2600-clock.h>
+#include <dt-bindings/reset/ast2600-reset.h>
+
+#include "ast2600.dtsi"
+
+/ {
+ scu: clock-controller@1e6e2000 {
+ compatible = "aspeed,ast2600-scu";
+ reg = <0x1e6e2000 0x1000>;
+ u-boot,dm-pre-reloc;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ uart-clk-source = <0x0>; /* uart clock source selection: 0: uxclk 1: huxclk*/
+ };
+
+ rst: reset-controller {
+ u-boot,dm-pre-reloc;
+ compatible = "aspeed,ast2600-reset";
+ aspeed,wdt = <&wdt1>;
+ #reset-cells = <1>;
+ };
+
+ sdrammc: sdrammc@1e6e0000 {
+ u-boot,dm-pre-reloc;
+ compatible = "aspeed,ast2600-sdrammc";
+ reg = <0x1e6e0000 0x100
+ 0x1e6e0100 0x300
+ 0x1e6e0400 0x200 >;
+ #reset-cells = <1>;
+ clocks = <&scu ASPEED_CLK_MPLL>;
+ resets = <&rst ASPEED_RESET_SDRAM>;
+ };
+
+ ahb {
+ u-boot,dm-pre-reloc;
+
+ apb {
+ u-boot,dm-pre-reloc;
+ };
+
+ };
+};
+