tree 41e5ea01cfc6d023c4789bdf759f447c7cc43dad
parent ab467c512e79dbd14f02352655f054a4304c457e
author Dave Liu <daveliu@freescale.com> 1267762920 +0800
committer Kumar Gala <galak@kernel.crashing.org> 1270616843 -0500

fsl-ddr: Fix the turnaround timing for TIMING_CFG_4

Read-to-read/Write-to-write turnaround for same chip select
of DDR3 memory, BL/2+2 cycles is enough for them at BC4 and
OTF case, BL/2 cycles is enough for fixed BL8.
Cutting down the turnaround from BL/2+4 to BL/2+2 or BL/2
will improve the memory performance.

Signed-off-by: Dave Liu <daveliu@freescale.com>