commit ebe4c1e6469444753bd2ba93fe63e6183cf2905c
author Claudiu Manoil <claudiu.manoil@freescale.com> Wed Aug 12 13:29:14 2015 +0300
committer York Sun <yorksun@freescale.com> Tue Sep 01 21:39:03 2015 -0500
tree cec6f84bbbdf284f6abceb121663b07b2f4b2a61
parent da2919b4a904411c374a6e0d9dc771e180968266

ls102xa: etsec: Use proper settings for BE BDs

Replace the DMACTRL[LE] hack with recommended settings
for ETSECDMAMCR to get the same end effect - obtaining
big-endian buffer descriptors and frame data for eTSEC.
The reset / default value for ETSECDMAMCR is preserved,
excepting the BD and FR bits which are cleared to enable
the BE mode in accordance with the H/W specifications.

Fixes: 52d00a8 "ls102xa: etsec: Add etsec support for LS102xA"
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Acked-by: Alison Wang <alison.wang@freescale.com>
Tested-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h

diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index d34044a..60aa0d3 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -143,7 +143,7 @@
 	u32	sdhcpcr;
 };
 
-#define SCFG_ETSECDMAMCR_LE_BD_FR	0xf8001a0f
+#define SCFG_ETSECDMAMCR_LE_BD_FR	0x00000c00
 #define SCFG_ETSECCMCR_GE2_CLK125	0x04000000
 #define SCFG_ETSECCMCR_GE0_CLK125	0x00000000
 #define SCFG_ETSECCMCR_GE1_CLK125	0x08000000

board/freescale/ls1021aqds/ls1021aqds.c

diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c
index d6ef6ba..e585380 100644
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -280,7 +280,8 @@
 	unsigned int major;
 
 #ifdef CONFIG_TSEC_ENET
-	out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
+	/* clear BD & FR bits for BE BD's and frame data */
+	clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
 #endif
 
 #ifdef CONFIG_FSL_IFC

board/freescale/ls1021atwr/ls1021atwr.c

diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c
index b7458a9..006700f 100644
--- a/board/freescale/ls1021atwr/ls1021atwr.c
+++ b/board/freescale/ls1021atwr/ls1021atwr.c
@@ -481,7 +481,8 @@
 	unsigned int major;
 
 #ifdef CONFIG_TSEC_ENET
-	out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
+	/* clear BD & FR bits for BE BD's and frame data */
+	clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
 	out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
 #endif
 

drivers/net/tsec.c

diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index 42d0374..4bdc188 100644
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c
@@ -271,9 +271,6 @@
 	out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
 	out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
 	clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
-#ifdef CONFIG_LS102XA
-	setbits_be32(&regs->dmactrl, DMACTRL_LE);
-#endif
 
 	do {
 		uint16_t status;
@@ -370,9 +367,6 @@
 	out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
 	out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
 	clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
-#ifdef CONFIG_LS102XA
-	setbits_be32(&regs->dmactrl, DMACTRL_LE);
-#endif
 }
 
 /* This returns the status bits of the device.	The return value