powerpc/t1023rdb: Add T1023 RDB board support
T1023RDB is a Freescale Reference Design Board that hosts the T1023 SoC.
T1023RDB board Overview
-----------------------
- T1023 SoC integrating two 64-bit e5500 cores up to 1.4GHz
- CoreNet fabric supporting coherent and noncoherent transactions with
prioritization and bandwidth allocation
- Memory: 2GB Micron MT40A512M8HX unbuffered 32-bit fixed DDR4 without ECC
- Accelerator: DPAA components consist of FMan, BMan, QMan, DCE and SEC
- Ethernet interfaces:
- one 1G RGMII port on-board(RTL8211F PHY)
- one 1G SGMII port on-board(RTL8211F PHY)
- one 2.5G SGMII port on-board(AQR105 PHY)
- PCIe: Two Mini-PCIe connectors on-board.
- SerDes: 4 lanes up to 10.3125GHz
- NOR: 128MB S29GL01GS110TFIV10 Spansion NOR Flash
- NAND: 512MB S34MS04G200BFI000 Spansion NAND Flash
- eSPI: 64MB S25FL512SAGMFI010 Spansion SPI flash.
- USB: one Type-A USB 2.0 port with internal PHY
- eSDHC: support SD/MMC card and eMMC on-board
- 256Kbit M24256 I2C EEPROM
- RTC: Real-time clock DS1339 on I2C bus
- UART: one serial port on-board with RJ45 connector
- Debugging: JTAG/COP for T1023 debugging
As well updated T1024RDB to add T1023RDB.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
[York Sun: fix defconfig files]
Reviewed-by: York Sun <yorksun@freescale.com>
diff --git a/board/freescale/t102xrdb/ddr.c b/board/freescale/t102xrdb/ddr.c
index a2a8f4c..adf9fd5 100644
--- a/board/freescale/t102xrdb/ddr.c
+++ b/board/freescale/t102xrdb/ddr.c
@@ -135,8 +135,83 @@
/* for DDR bus 32bit test on T1024 */
popts->data_bus_width = DDR_DATA_BUS_WIDTH_32;
#endif
+
+#ifdef CONFIG_T1023RDB
+ popts->wrlvl_ctl_2 = 0x07070606;
+ popts->half_strength_driver_enable = 1;
+#endif
}
+#ifdef CONFIG_SYS_DDR_RAW_TIMING
+/* 2GB discrete DDR4 MT40A512M8HX on T1023RDB */
+dimm_params_t ddr_raw_timing = {
+ .n_ranks = 1,
+ .rank_density = 0x80000000,
+ .capacity = 0x80000000,
+ .primary_sdram_width = 32,
+ .ec_sdram_width = 8,
+ .registered_dimm = 0,
+ .mirrored_dimm = 0,
+ .n_row_addr = 15,
+ .n_col_addr = 10,
+ .bank_addr_bits = 2,
+ .bank_group_bits = 2,
+ .edc_config = 0,
+ .burst_lengths_bitmask = 0x0c,
+ .tckmin_x_ps = 938,
+ .tckmax_ps = 1500,
+ .caslat_x = 0x000DFA00,
+ .taa_ps = 13500,
+ .trcd_ps = 13500,
+ .trp_ps = 13500,
+ .tras_ps = 33000,
+ .trc_ps = 46500,
+ .trfc1_ps = 260000,
+ .trfc2_ps = 160000,
+ .trfc4_ps = 110000,
+ .tfaw_ps = 25000,
+ .trrds_ps = 3700,
+ .trrdl_ps = 5300,
+ .tccdl_ps = 5355,
+ .refresh_rate_ps = 7800000,
+ .dq_mapping[0] = 0x0,
+ .dq_mapping[1] = 0x0,
+ .dq_mapping[2] = 0x0,
+ .dq_mapping[3] = 0x0,
+ .dq_mapping[4] = 0x0,
+ .dq_mapping[5] = 0x0,
+ .dq_mapping[6] = 0x0,
+ .dq_mapping[7] = 0x0,
+ .dq_mapping[8] = 0x0,
+ .dq_mapping[9] = 0x0,
+ .dq_mapping[10] = 0x0,
+ .dq_mapping[11] = 0x0,
+ .dq_mapping[12] = 0x0,
+ .dq_mapping[13] = 0x0,
+ .dq_mapping[14] = 0x0,
+ .dq_mapping[15] = 0x0,
+ .dq_mapping[16] = 0x0,
+ .dq_mapping[17] = 0x0,
+ .dq_mapping_ors = 1,
+};
+
+int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
+ unsigned int controller_number,
+ unsigned int dimm_number)
+{
+ const char dimm_model[] = "Fixed DDR4 on board";
+
+ if (((controller_number == 0) && (dimm_number == 0)) ||
+ ((controller_number == 1) && (dimm_number == 0))) {
+ memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
+ memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
+ memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
+ }
+
+ return 0;
+}
+#endif
+
#if defined(CONFIG_DEEP_SLEEP)
void board_mem_sleep_setup(void)
{
@@ -155,8 +230,9 @@
phys_size_t dram_size;
#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
+#ifndef CONFIG_SYS_DDR_RAW_TIMING
puts("Initializing....using SPD\n");
-
+#endif
dram_size = fsl_ddr_sdram();
dram_size = setup_ddr_tlbs(dram_size / 0x100000);
dram_size *= 0x100000;