| commit | e7690e61952b0058214fc36cad91d1c77a8c0239 | [log] [tgz] |
|---|---|---|
| author | Marek Vasut <marek.vasut+renesas@gmail.com> | Tue Apr 27 19:36:39 2021 +0200 |
| committer | Marek Vasut <marek.vasut+renesas@gmail.com> | Fri May 21 15:00:17 2021 +0200 |
| tree | 518a679d6fd290cf789b696b278efa593bcccd41 | |
| parent | d413214fb74873721d92ffe27fa63158ee84e469 [diff] |
clk: renesas: Deduplicate gen3_clk_get_rate64() PLL handling Most of the PLLx, MAIN, FIXED clock handlers are calling very similar code, which determines parent rate and then applies multiplication and division. The only difference is whether multiplication is fixed factor or coming from CRx register. Deduplicate the code into a single function. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>