diff --git a/board/freescale/mpc8313erdb/config.mk b/board/freescale/mpc8313erdb/config.mk
index f768264..fd72a14 100644
--- a/board/freescale/mpc8313erdb/config.mk
+++ b/board/freescale/mpc8313erdb/config.mk
@@ -1 +1,7 @@
+ifndef NAND_SPL
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
+endif
+
+ifndef TEXT_BASE
 TEXT_BASE = 0xFE000000
+endif
diff --git a/board/freescale/mpc8313erdb/mpc8313erdb.c b/board/freescale/mpc8313erdb/mpc8313erdb.c
index 7cbdb7b..ebb703d 100644
--- a/board/freescale/mpc8313erdb/mpc8313erdb.c
+++ b/board/freescale/mpc8313erdb/mpc8313erdb.c
@@ -29,6 +29,8 @@
 #include <pci.h>
 #include <mpc83xx.h>
 #include <vsc7385.h>
+#include <ns16550.h>
+#include <nand.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -50,6 +52,7 @@
 	return 0;
 }
 
+#ifndef CONFIG_NAND_SPL
 static struct pci_region pci_regions[] = {
 	{
 		bus_start: CFG_PCI1_MEM_BASE,
@@ -128,3 +131,32 @@
 #endif
 }
 #endif
+#else /* CONFIG_NAND_SPL */
+void board_init_f(ulong bootflag)
+{
+	board_early_init_f();
+	NS16550_init((NS16550_t)(CFG_IMMR + 0x4500),
+	             CFG_NS16550_CLK / 16 / CONFIG_BAUDRATE);
+	puts("NAND boot... ");
+	init_timebase();
+	initdram(0);
+	relocate_code(CFG_NAND_U_BOOT_RELOC + 0x10000, (gd_t *)gd,
+	              CFG_NAND_U_BOOT_RELOC);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+	nand_boot();
+}
+
+void putc(char c)
+{
+	if (gd->flags & GD_FLG_SILENT)
+		return;
+
+	if (c == '\n')
+		NS16550_putc((NS16550_t)(CFG_IMMR + 0x4500), '\r');
+
+	NS16550_putc((NS16550_t)(CFG_IMMR + 0x4500), c);
+}
+#endif
diff --git a/board/freescale/mpc8313erdb/sdram.c b/board/freescale/mpc8313erdb/sdram.c
index afd8b9d..3a6347f 100644
--- a/board/freescale/mpc8313erdb/sdram.c
+++ b/board/freescale/mpc8313erdb/sdram.c
@@ -58,8 +58,10 @@
  */
 static long fixed_sdram(void)
 {
-	volatile immap_t *im = (volatile immap_t *)CFG_IMMR;
 	u32 msize = CFG_DDR_SIZE * 1024 * 1024;
+
+#ifndef CFG_RAMBOOT
+	volatile immap_t *im = (volatile immap_t *)CFG_IMMR;
 	u32 msize_log2 = __ilog2(msize);
 
 	im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE >> 12;
@@ -100,6 +102,7 @@
 
 	/* enable DDR controller */
 	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
+#endif
 
 	return msize;
 }