| commit | dbbbb3abeff325855cae76e33d69d5665631443f | [log] [tgz] |
|---|---|---|
| author | Haiying Wang <Haiying.Wang@freescale.com> | Fri Oct 03 12:36:39 2008 -0400 |
| committer | Wolfgang Denk <wd@denx.de> | Sat Oct 18 21:54:04 2008 +0200 |
| tree | 2df59a7ac7364e4c501e228c74db3cd5f14ad3b1 | |
| parent | 1c9aa76bf9013069e24258f46f4687c9f98a02d6 [diff] |
Make DDR interleaving mode work correctly
Fix some bugs:
1. Correctly set intlv_ctl in cs_config.
2. Correctly set sa, ea in cs_bnds when bank interleaving mode is enabled.
3. Set base_address and total memory for each ddr controller in memory
controller interleaving mode.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>