arm: socfpga: Restructure clock manager driver
Restructure clock manager driver in the preparation to support A10.
Move the Gen5 specific code to _gen5 files.
- Change all uint32_t to u32 and change to use macro BIT(n) for bit shift.
- Check return value from wait_for_bit(). So change return type to int for
cm_write_with_phase() and cm_basic_init().
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 809cd47..b76de4c 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -13,7 +13,8 @@
obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
# QTS-generated config file wrappers
-obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += scan_manager.o wrap_pll_config.o
+obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += scan_manager.o wrap_pll_config.o \
+ clock_manager_gen5.o
obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o wrap_pinmux_config.o \
wrap_sdram_config.o
CFLAGS_wrap_iocsr_config.o += -I$(srctree)/board/$(BOARDDIR)