* Patch by Rick Bronson, 16 Mar 2003:
Add support for Atmel AT91RM9200DK w/NAND
* Patches by Robert Schwebel, 19 Mar 2003:
- use arm-linux-gcc as default compiler for ARM
- fix i2c fixup code
- fix missing baudrate setting
- added $loadaddr / CFG_LOAD_ADDR support to loadb
- moved "ignoring trailing characters" _before_ u-boot wants to
print out diagnostics messages; removes bogus characters at the
end of transmission
* Patch by John Zhan, 18 Mar 2003:
Add support for SinoVee Microsystems SC8xx boards
* Patch by Rolf Offermanns, 21 Mar 2003:
ported the dnp1110 related changes from the current armboot cvs to
current u-boot cvs. smc91111 does not work. problem marked in
smc91111.c, grep for "FIXME".
* Patch by Brian Auld, 25 Mar 2003:
Add support for STM flash chips on ebony board
* Add PCI support for MPC8250 Boards (PM825 module)
* Patch by Stefan Roese, 25 Mar 2003:
diff --git a/include/AT91RM9200.h b/include/AT91RM9200.h
new file mode 100644
index 0000000..f65328f
--- /dev/null
+++ b/include/AT91RM9200.h
@@ -0,0 +1,349 @@
+/* ---------------------------------------------------------------------------- */
+/* ATMEL Microcontroller Software Support - ROUSSET - */
+/* ---------------------------------------------------------------------------- */
+/* The software is delivered "AS IS" without warranty or condition of any */
+/* kind, either express, implied or statutory. This includes without */
+/* limitation any warranty or condition with respect to merchantability or */
+/* fitness for any particular purpose, or against the infringements of */
+/* intellectual property rights of others. */
+/* ---------------------------------------------------------------------------- */
+/* File Name : AT91RM9200.h */
+/* Object : AT91RM9200 definitions */
+/* Generated : AT91 SW Application Group 10/29/2002 (16:10:51) */
+#ifndef AT91RM9200_H
+#define AT91RM9200_H
+
+typedef volatile unsigned int AT91_REG;/* Hardware register definition */
+
+/* ***************************************************************************** */
+/* SOFTWARE API DEFINITION FOR Timer Counter Channel Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_TC {
+ AT91_REG TC_CCR; /* Channel Control Register */
+ AT91_REG TC_CMR; /* Channel Mode Register */
+ AT91_REG Reserved0[2]; /* */
+ AT91_REG TC_CV; /* Counter Value */
+ AT91_REG TC_RA; /* Register A */
+ AT91_REG TC_RB; /* Register B */
+ AT91_REG TC_RC; /* Register C */
+ AT91_REG TC_SR; /* Status Register */
+ AT91_REG TC_IER; /* Interrupt Enable Register */
+ AT91_REG TC_IDR; /* Interrupt Disable Register */
+ AT91_REG TC_IMR; /* Interrupt Mask Register */
+} AT91S_TC, *AT91PS_TC;
+
+/* ***************************************************************************** */
+/* SOFTWARE API DEFINITION FOR Usart */
+/* ***************************************************************************** */
+typedef struct _AT91S_USART {
+ AT91_REG US_CR; /* Control Register */
+ AT91_REG US_MR; /* Mode Register */
+ AT91_REG US_IER; /* Interrupt Enable Register */
+ AT91_REG US_IDR; /* Interrupt Disable Register */
+ AT91_REG US_IMR; /* Interrupt Mask Register */
+ AT91_REG US_CSR; /* Channel Status Register */
+ AT91_REG US_RHR; /* Receiver Holding Register */
+ AT91_REG US_THR; /* Transmitter Holding Register */
+ AT91_REG US_BRGR; /* Baud Rate Generator Register */
+ AT91_REG US_RTOR; /* Receiver Time-out Register */
+ AT91_REG US_TTGR; /* Transmitter Time-guard Register */
+ AT91_REG Reserved0[5]; /* */
+ AT91_REG US_FIDI; /* FI_DI_Ratio Register */
+ AT91_REG US_NER; /* Nb Errors Register */
+ AT91_REG US_XXR; /* XON_XOFF Register */
+ AT91_REG US_IF; /* IRDA_FILTER Register */
+ AT91_REG Reserved1[44]; /* */
+ AT91_REG US_RPR; /* Receive Pointer Register */
+ AT91_REG US_RCR; /* Receive Counter Register */
+ AT91_REG US_TPR; /* Transmit Pointer Register */
+ AT91_REG US_TCR; /* Transmit Counter Register */
+ AT91_REG US_RNPR; /* Receive Next Pointer Register */
+ AT91_REG US_RNCR; /* Receive Next Counter Register */
+ AT91_REG US_TNPR; /* Transmit Next Pointer Register */
+ AT91_REG US_TNCR; /* Transmit Next Counter Register */
+ AT91_REG US_PTCR; /* PDC Transfer Control Register */
+ AT91_REG US_PTSR; /* PDC Transfer Status Register */
+} AT91S_USART, *AT91PS_USART;
+
+/* ***************************************************************************** */
+/* SOFTWARE API DEFINITION FOR Parallel Input Output Controler */
+/* ***************************************************************************** */
+typedef struct _AT91S_PIO {
+ AT91_REG PIO_PER; /* PIO Enable Register */
+ AT91_REG PIO_PDR; /* PIO Disable Register */
+ AT91_REG PIO_PSR; /* PIO Status Register */
+ AT91_REG Reserved0[1]; /* */
+ AT91_REG PIO_OER; /* Output Enable Register */
+ AT91_REG PIO_ODR; /* Output Disable Registerr */
+ AT91_REG PIO_OSR; /* Output Status Register */
+ AT91_REG Reserved1[1]; /* */
+ AT91_REG PIO_IFER; /* Input Filter Enable Register */
+ AT91_REG PIO_IFDR; /* Input Filter Disable Register */
+ AT91_REG PIO_IFSR; /* Input Filter Status Register */
+ AT91_REG Reserved2[1]; /* */
+ AT91_REG PIO_SODR; /* Set Output Data Register */
+ AT91_REG PIO_CODR; /* Clear Output Data Register */
+ AT91_REG PIO_ODSR; /* Output Data Status Register */
+ AT91_REG PIO_PDSR; /* Pin Data Status Register */
+ AT91_REG PIO_IER; /* Interrupt Enable Register */
+ AT91_REG PIO_IDR; /* Interrupt Disable Register */
+ AT91_REG PIO_IMR; /* Interrupt Mask Register */
+ AT91_REG PIO_ISR; /* Interrupt Status Register */
+ AT91_REG PIO_MDER; /* Multi-driver Enable Register */
+ AT91_REG PIO_MDDR; /* Multi-driver Disable Register */
+ AT91_REG PIO_MDSR; /* Multi-driver Status Register */
+ AT91_REG Reserved3[1]; /* */
+ AT91_REG PIO_PPUDR; /* Pull-up Disable Register */
+ AT91_REG PIO_PPUER; /* Pull-up Enable Register */
+ AT91_REG PIO_PPUSR; /* Pad Pull-up Status Register */
+ AT91_REG Reserved4[1]; /* */
+ AT91_REG PIO_ASR; /* Select A Register */
+ AT91_REG PIO_BSR; /* Select B Register */
+ AT91_REG PIO_ABSR; /* AB Select Status Register */
+ AT91_REG Reserved5[9]; /* */
+ AT91_REG PIO_OWER; /* Output Write Enable Register */
+ AT91_REG PIO_OWDR; /* Output Write Disable Register */
+ AT91_REG PIO_OWSR; /* Output Write Status Register */
+} AT91S_PIO, *AT91PS_PIO;
+
+
+/* ***************************************************************************** */
+/* SOFTWARE API DEFINITION FOR Debug Unit */
+/* ***************************************************************************** */
+typedef struct _AT91S_DBGU {
+ AT91_REG DBGU_CR; /* Control Register */
+ AT91_REG DBGU_MR; /* Mode Register */
+ AT91_REG DBGU_IER; /* Interrupt Enable Register */
+ AT91_REG DBGU_IDR; /* Interrupt Disable Register */
+ AT91_REG DBGU_IMR; /* Interrupt Mask Register */
+ AT91_REG DBGU_CSR; /* Channel Status Register */
+ AT91_REG DBGU_RHR; /* Receiver Holding Register */
+ AT91_REG DBGU_THR; /* Transmitter Holding Register */
+ AT91_REG DBGU_BRGR; /* Baud Rate Generator Register */
+ AT91_REG Reserved0[7]; /* */
+ AT91_REG DBGU_C1R; /* Chip ID1 Register */
+ AT91_REG DBGU_C2R; /* Chip ID2 Register */
+ AT91_REG DBGU_FNTR; /* Force NTRST Register */
+ AT91_REG Reserved1[45]; /* */
+ AT91_REG DBGU_RPR; /* Receive Pointer Register */
+ AT91_REG DBGU_RCR; /* Receive Counter Register */
+ AT91_REG DBGU_TPR; /* Transmit Pointer Register */
+ AT91_REG DBGU_TCR; /* Transmit Counter Register */
+ AT91_REG DBGU_RNPR; /* Receive Next Pointer Register */
+ AT91_REG DBGU_RNCR; /* Receive Next Counter Register */
+ AT91_REG DBGU_TNPR; /* Transmit Next Pointer Register */
+ AT91_REG DBGU_TNCR; /* Transmit Next Counter Register */
+ AT91_REG DBGU_PTCR; /* PDC Transfer Control Register */
+ AT91_REG DBGU_PTSR; /* PDC Transfer Status Register */
+} AT91S_DBGU, *AT91PS_DBGU;
+
+
+/* ***************************************************************************** */
+/* SOFTWARE API DEFINITION FOR Static Memory Controller 2 Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_SMC2 {
+ AT91_REG SMC2_CSR[8]; /* SMC2 Chip Select Register */
+} AT91S_SMC2, *AT91PS_SMC2;
+
+/* ***************************************************************************** */
+/* SOFTWARE API DEFINITION FOR Ethernet MAC */
+/* ***************************************************************************** */
+typedef struct _AT91S_EMAC {
+ AT91_REG EMAC_CTL; /* Network Control Register */
+ AT91_REG EMAC_CFG; /* Network Configuration Register */
+ AT91_REG EMAC_SR; /* Network Status Register */
+ AT91_REG EMAC_TAR; /* Transmit Address Register */
+ AT91_REG EMAC_TCR; /* Transmit Control Register */
+ AT91_REG EMAC_TSR; /* Transmit Status Register */
+ AT91_REG EMAC_RBQP; /* Receive Buffer Queue Pointer */
+ AT91_REG Reserved0[1]; /* */
+ AT91_REG EMAC_RSR; /* Receive Status Register */
+ AT91_REG EMAC_ISR; /* Interrupt Status Register */
+ AT91_REG EMAC_IER; /* Interrupt Enable Register */
+ AT91_REG EMAC_IDR; /* Interrupt Disable Register */
+ AT91_REG EMAC_IMR; /* Interrupt Mask Register */
+ AT91_REG EMAC_MAN; /* PHY Maintenance Register */
+ AT91_REG Reserved1[2]; /* */
+ AT91_REG EMAC_FRA; /* Frames Transmitted OK Register */
+ AT91_REG EMAC_SCOL; /* Single Collision Frame Register */
+ AT91_REG EMAC_MCOL; /* Multiple Collision Frame Register */
+ AT91_REG EMAC_OK; /* Frames Received OK Register */
+ AT91_REG EMAC_SEQE; /* Frame Check Sequence Error Register */
+ AT91_REG EMAC_ALE; /* Alignment Error Register */
+ AT91_REG EMAC_DTE; /* Deferred Transmission Frame Register */
+ AT91_REG EMAC_LCOL; /* Late Collision Register */
+ AT91_REG EMAC_ECOL; /* Excessive Collision Register */
+ AT91_REG EMAC_CSE; /* Carrier Sense Error Register */
+ AT91_REG EMAC_TUE; /* Transmit Underrun Error Register */
+ AT91_REG EMAC_CDE; /* Code Error Register */
+ AT91_REG EMAC_ELR; /* Excessive Length Error Register */
+ AT91_REG EMAC_RJB; /* Receive Jabber Register */
+ AT91_REG EMAC_USF; /* Undersize Frame Register */
+ AT91_REG EMAC_SQEE; /* SQE Test Error Register */
+ AT91_REG EMAC_DRFC; /* Discarded RX Frame Register */
+ AT91_REG Reserved2[3]; /* */
+ AT91_REG EMAC_HSH; /* Hash Address High[63:32] */
+ AT91_REG EMAC_HSL; /* Hash Address Low[31:0] */
+ AT91_REG EMAC_SA1L; /* Specific Address 1 Low, First 4 bytes */
+ AT91_REG EMAC_SA1H; /* Specific Address 1 High, Last 2 bytes */
+ AT91_REG EMAC_SA2L; /* Specific Address 2 Low, First 4 bytes */
+ AT91_REG EMAC_SA2H; /* Specific Address 2 High, Last 2 bytes */
+ AT91_REG EMAC_SA3L; /* Specific Address 3 Low, First 4 bytes */
+ AT91_REG EMAC_SA3H; /* Specific Address 3 High, Last 2 bytes */
+ AT91_REG EMAC_SA4L; /* Specific Address 4 Low, First 4 bytes */
+ AT91_REG EMAC_SA4H; /* Specific Address 4 High, Last 2 bytesr */
+} AT91S_EMAC, *AT91PS_EMAC;
+
+/* -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- */
+#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) /* (DBGU) RXRDY Interrupt */
+#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) /* (DBGU) TXRDY Interrupt */
+#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) /* (DBGU) End of Receive Transfer Interrupt */
+#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) /* (DBGU) End of Transmit Interrupt */
+#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) /* (DBGU) Overrun Interrupt */
+#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) /* (DBGU) Framing Error Interrupt */
+#define AT91C_US_PARE ((unsigned int) 0x1 << 7) /* (DBGU) Parity Error Interrupt */
+#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) /* (DBGU) TXEMPTY Interrupt */
+#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) /* (DBGU) TXBUFE Interrupt */
+#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) /* (DBGU) RXBUFF Interrupt */
+#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) /* (DBGU) COMM_TX Interrupt */
+#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) /* (DBGU) COMM_RX Interrupt */
+
+/* -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- */
+#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) /* (DBGU) Reset Receiver */
+#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) /* (DBGU) Reset Transmitter */
+#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) /* (DBGU) Receiver Enable */
+#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) /* (DBGU) Receiver Disable */
+#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) /* (DBGU) Transmitter Enable */
+#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) /* (DBGU) Transmitter Disable */
+
+#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) /* (USART) Clock */
+#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) /* (USART) Character Length: 8 bits */
+#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) /* (DBGU) No Parity */
+#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) /* (USART) 1 stop bit */
+
+#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) /* (PMC) Peripheral Clock Enable Register */
+#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) /* (PIOA) PIO Disable Register */
+#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) /* Pin Controlled by PA30 */
+#define AT91C_PIO_PC0 ((unsigned int) 1 << 0) /* Pin Controlled by PC0 */
+#define AT91C_PC0_BFCK ((unsigned int) AT91C_PIO_PC0) /* Burst Flash Clock */
+#define AT91C_PA30_DRXD ((unsigned int) AT91C_PIO_PA30) /* DBGU Debug Receive Data */
+#define AT91C_PIO_PA31 ((unsigned int) 1 << 31) /* Pin Controlled by PA31 */
+#define AT91C_PA31_DTXD ((unsigned int) AT91C_PIO_PA31) /* DBGU Debug Transmit Data */
+
+#define AT91C_ID_SYS ((unsigned int) 1) /* System Peripheral */
+#define AT91C_ID_TC0 ((unsigned int) 17) /* Timer Counter 0 */
+#define AT91C_ID_EMAC ((unsigned int) 24) /* Ethernet MAC */
+
+#define AT91C_PIO_PC1 ((unsigned int) 1 << 1) /* Pin Controlled by PC1 */
+#define AT91C_PC1_BFRDY_SMOE ((unsigned int) AT91C_PIO_PC1) /* Burst Flash Ready */
+#define AT91C_PIO_PC3 ((unsigned int) 1 << 3) /* Pin Controlled by PC3 */
+#define AT91C_PC3_BFBAA_SMWE ((unsigned int) AT91C_PIO_PC3) /* Burst Flash Address Advance / SmartMedia Write Enable */
+#define AT91C_PIO_PC2 ((unsigned int) 1 << 2) /* Pin Controlled by PC2 */
+#define AT91C_PC2_BFAVD ((unsigned int) AT91C_PIO_PC2) /* Burst Flash Address Valid */
+#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) /* Pin Controlled by PB1 */
+
+#define AT91C_TC_TIMER_DIV1_CLOCK ((unsigned int) 0x0 << 0) /* (TC) MCK/2 */
+#define AT91C_TC_TIMER_DIV2_CLOCK ((unsigned int) 0x1 << 0) /* (TC) MCK/8 */
+#define AT91C_TC_TIMER_DIV3_CLOCK ((unsigned int) 0x2 << 0) /* (TC) MCK/32 */
+#define AT91C_TC_TIMER_DIV4_CLOCK ((unsigned int) 0x3 << 0) /* (TC) MCK/128 */
+#define AT91C_TC_SLOW_CLOCK ((unsigned int) 0x4 << 0) /* (TC) SLOW CLK */
+#define AT91C_TC_XC0_CLOCK ((unsigned int) 0x5 << 0) /* (TC) XC0 */
+#define AT91C_TC_XC1_CLOCK ((unsigned int) 0x6 << 0) /* (TC) XC1 */
+#define AT91C_TC_XC2_CLOCK ((unsigned int) 0x7 << 0) /* (TC) XC2 */
+#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) /* (TCB) None signal connected to XC0 */
+#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) /* (TCB) None signal connected to XC1 */
+#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) /* (TCB) None signal connected to XC2 */
+#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) /* (TC) Counter Clock Disable Command */
+#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) /* (TC) Software Trigger Command */
+#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) /* (TC) Counter Clock Enable Command */
+
+#define AT91C_EMAC_BNQ ((unsigned int) 0x1 << 4) /* (EMAC) */
+#define AT91C_EMAC_COMP ((unsigned int) 0x1 << 5) /* (EMAC) */
+#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) /* (EMAC) */
+#define AT91C_EMAC_RE ((unsigned int) 0x1 << 2) /* (EMAC) Receive enable. */
+#define AT91C_EMAC_TE ((unsigned int) 0x1 << 3) /* (EMAC) Transmit enable. */
+#define AT91C_EMAC_CLK ((unsigned int) 0x3 << 10) /* (EMAC) */
+#define AT91C_EMAC_RMII ((unsigned int) 0x1 << 13) /* (EMAC) */
+#define AT91C_EMAC_NBC ((unsigned int) 0x1 << 5) /* (EMAC) No broadcast. */
+#define AT91C_EMAC_CAF ((unsigned int) 0x1 << 4) /* (EMAC) Copy all frames. */
+#define AT91C_EMAC_BNA ((unsigned int) 0x1 << 0) /* (EMAC) */
+#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) /* (EMAC) */
+#define AT91C_EMAC_RSR_OVR ((unsigned int) 0x1 << 2) /* (EMAC) */
+#define AT91C_EMAC_CSR ((unsigned int) 0x1 << 5) /* (EMAC) Clear statistics registers. */
+#define AT91C_EMAC_SPD ((unsigned int) 0x1 << 0) /* (EMAC) Speed. */
+#define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) /* (EMAC) Full duplex. */
+#define AT91C_EMAC_LINK ((unsigned int) 0x1 << 0) /* (EMAC) */
+#define AT91C_EMAC_MPE ((unsigned int) 0x1 << 4) /* (EMAC) Management port enable. */
+#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) /* Pin Controlled by PA16 */
+#define AT91C_PA16_EMDIO ((unsigned int) AT91C_PIO_PA16) /* Ethernet MAC Management Data Input/Output */
+#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) /* Pin Controlled by PA15 */
+#define AT91C_PA15_EMDC ((unsigned int) AT91C_PIO_PA15) /* Ethernet MAC Management Data Clock */
+#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) /* Pin Controlled by PA14 */
+#define AT91C_PA14_ERXER ((unsigned int) AT91C_PIO_PA14) /* Ethernet MAC Receive Error */
+#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) /* Pin Controlled by PA13 */
+#define AT91C_PA13_ERX1 ((unsigned int) AT91C_PIO_PA13) /* Ethernet MAC Receive Data 1 */
+#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) /* Pin Controlled by PA12 */
+#define AT91C_PA12_ERX0 ((unsigned int) AT91C_PIO_PA12) /* Ethernet MAC Receive Data 0 */
+#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) /* Pin Controlled by PA11 */
+#define AT91C_PA11_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PA11) /* Ethernet MAC Carrier Sense/Carrier Sense and Data Valid */
+#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) /* Pin Controlled by PA10 */
+#define AT91C_PA10_ETX1 ((unsigned int) AT91C_PIO_PA10) /* Ethernet MAC Transmit Data 1 */
+#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) /* Pin Controlled by PA9 */
+#define AT91C_PA9_ETX0 ((unsigned int) AT91C_PIO_PA9) /* Ethernet MAC Transmit Data 0 */
+#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) /* Pin Controlled by PA8 */
+#define AT91C_PA8_ETXEN ((unsigned int) AT91C_PIO_PA8) /* Ethernet MAC Transmit Enable */
+#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) /* Pin Controlled by PA7 */
+#define AT91C_PA7_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PA7) /* Ethernet MAC Transmit Clock/Reference Clock */
+#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) /* Pin Controlled by PB25 */
+#define AT91C_PB25_DSR1 ((unsigned int) AT91C_PIO_PB25) /* USART 1 Data Set ready */
+#define AT91C_PB25_EF100 ((unsigned int) AT91C_PIO_PB25) /* Ethernet MAC Force 100 Mbits */
+#define AT91C_PIO_PB19 ((unsigned int) 1 << 19) /* Pin Controlled by PB19 */
+#define AT91C_PB19_DTR1 ((unsigned int) AT91C_PIO_PB19) /* USART 1 Data Terminal ready */
+#define AT91C_PB19_ERXCK ((unsigned int) AT91C_PIO_PB19) /* Ethernet MAC Receive Clock */
+#define AT91C_PIO_PB18 ((unsigned int) 1 << 18) /* Pin Controlled by PB18 */
+#define AT91C_PB18_RI1 ((unsigned int) AT91C_PIO_PB18) /* USART 1 Ring Indicator */
+#define AT91C_PB18_ECOL ((unsigned int) AT91C_PIO_PB18) /* Ethernet MAC Collision Detected */
+#define AT91C_PIO_PB17 ((unsigned int) 1 << 17) /* Pin Controlled by PB17 */
+#define AT91C_PB17_RF2 ((unsigned int) AT91C_PIO_PB17) /* SSC Receive Frame Sync 2 */
+#define AT91C_PB17_ERXDV ((unsigned int) AT91C_PIO_PB17) /* Ethernet MAC Receive Data Valid */
+#define AT91C_PIO_PB16 ((unsigned int) 1 << 16) /* Pin Controlled by PB16 */
+#define AT91C_PB16_RK2 ((unsigned int) AT91C_PIO_PB16) /* SSC Receive Clock 2 */
+#define AT91C_PB16_ERX3 ((unsigned int) AT91C_PIO_PB16) /* Ethernet MAC Receive Data 3 */
+#define AT91C_PIO_PB15 ((unsigned int) 1 << 15) /* Pin Controlled by PB15 */
+#define AT91C_PB15_RD2 ((unsigned int) AT91C_PIO_PB15) /* SSC Receive Data 2 */
+#define AT91C_PB15_ERX2 ((unsigned int) AT91C_PIO_PB15) /* Ethernet MAC Receive Data 2 */
+#define AT91C_PIO_PB14 ((unsigned int) 1 << 14) /* Pin Controlled by PB14 */
+#define AT91C_PB14_TD2 ((unsigned int) AT91C_PIO_PB14) /* SSC Transmit Data 2 */
+#define AT91C_PB14_ETXER ((unsigned int) AT91C_PIO_PB14) /* Ethernet MAC Transmikt Coding Error */
+#define AT91C_PIO_PB13 ((unsigned int) 1 << 13) /* Pin Controlled by PB13 */
+#define AT91C_PB13_TK2 ((unsigned int) AT91C_PIO_PB13) /* SSC Transmit Clock 2 */
+#define AT91C_PB13_ETX3 ((unsigned int) AT91C_PIO_PB13) /* Ethernet MAC Transmit Data 3 */
+#define AT91C_PIO_PB12 ((unsigned int) 1 << 12) /* Pin Controlled by PB12 */
+#define AT91C_PB12_TF2 ((unsigned int) AT91C_PIO_PB12) /* SSC Transmit Frame Sync 2 */
+#define AT91C_PB12_ETX2 ((unsigned int) AT91C_PIO_PB12) /* Ethernet MAC Transmit Data 2 */
+
+#define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) /* (PIOB) Select B Register */
+#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFBC000) /* (EMAC) Base Address */
+#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) /* (PIOB) PIO Disable Register */
+
+#define AT91C_EBI_CS3A_SMC_SmartMedia ((unsigned int) 0x1 << 3) /* (EBI) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated. */
+#define AT91C_SMC2_ACSS_STANDARD ((unsigned int) 0x0 << 16) /* (SMC2) Standard, asserted at the beginning of the access and deasserted at the end. */
+#define AT91C_SMC2_DBW_8 ((unsigned int) 0x2 << 13) /* (SMC2) 8-bit. */
+#define AT91C_SMC2_WSEN ((unsigned int) 0x1 << 7) /* (SMC2) Wait State Enable */
+#define AT91C_PIOC_ASR ((AT91_REG *) 0xFFFFF870) /* (PIOC) Select A Register */
+
+#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) /* (TC0) Base Address */
+#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) /* (DBGU) Base Address */
+#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) /* (PIOA) Base Address */
+#define AT91C_EBI_CSA ((AT91_REG *) 0xFFFFFF60) /* (EBI) Chip Select Assignment Register */
+#define AT91C_BASE_SMC2 ((AT91PS_SMC2) 0xFFFFFF70) /* (SMC2) Base Address */
+#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) /* (US1) Base Address */
+#define AT91C_TCB0_BMR ((AT91_REG *) 0xFFFA00C4) /* (TCB0) TC Block Mode Register */
+#define AT91C_TCB0_BCR ((AT91_REG *) 0xFFFA00C0) /* (TCB0) TC Block Control Register */
+#define AT91C_PIOC_PDR ((AT91_REG *) 0xFFFFF804) /* (PIOC) PIO Disable Register */
+#define AT91C_PIOC_PER ((AT91_REG *) 0xFFFFF800) /* (PIOC) PIO Enable Register */
+#define AT91C_PIOC_ODR ((AT91_REG *) 0xFFFFF814) /* (PIOC) Output Disable Registerr */
+#define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) /* (PIOB) PIO Enable Register */
+#define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) /* (PIOB) Output Disable Registerr */
+#define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) /* (PIOB) Pin Data Status Register */
+#endif
diff --git a/include/asm-ppc/u-boot.h b/include/asm-ppc/u-boot.h
index eea9c7c..e417e0d 100644
--- a/include/asm-ppc/u-boot.h
+++ b/include/asm-ppc/u-boot.h
@@ -68,11 +68,11 @@
#if defined(CONFIG_HYMOD)
hymod_conf_t bi_hymod_conf; /* hymod configuration information */
#endif
-#if defined(CONFIG_EVB64260) || defined(CONFIG_PN62)
+#if defined(CONFIG_EVB64260) || defined(CONFIG_PN62) || defined(CONFIG_SVM_SC8xx)
/* second onboard ethernet port */
unsigned char bi_enet1addr[6];
#endif
-#if defined(CONFIG_EVB64260)
+#if defined(CONFIG_EVB64260) || defined(CONFIG_SVM_SC8xx)
/* third onboard ethernet port */
unsigned char bi_enet2addr[6];
#endif
diff --git a/include/cmd_confdefs.h b/include/cmd_confdefs.h
index c462c3f..4e7ab9b 100644
--- a/include/cmd_confdefs.h
+++ b/include/cmd_confdefs.h
@@ -78,6 +78,7 @@
#define CFG_CMD_SPI 0x0000100000000000 /* SPI utility */
#define CFG_CMD_FDOS 0x0000200000000000 /* Floppy DOS support */
#define CFG_CMD_VFD 0x0000400000000000 /* VFD support (TRAB) */
+#define CFG_CMD_NAND 0x0000800000000000 /* NAND support */
#define CFG_CMD_ALL 0xFFFFFFFFFFFFFFFF /* ALL commands */
@@ -106,6 +107,7 @@
CFG_CMD_JFFS2 | \
CFG_CMD_KGDB | \
CFG_CMD_MII | \
+ CFG_CMD_NAND | \
CFG_CMD_PCI | \
CFG_CMD_PCMCIA | \
CFG_CMD_REGINFO | \
diff --git a/include/cmd_nand.h b/include/cmd_nand.h
new file mode 100644
index 0000000..febb27d
--- /dev/null
+++ b/include/cmd_nand.h
@@ -0,0 +1,55 @@
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * NAND support
+ */
+#ifndef _CMD_NAND_H
+#define _CMD_NAND_H
+
+#include <common.h>
+#include <command.h>
+
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#define CMD_TBL_NAND MK_CMD_TBL_ENTRY( \
+ "nand", 3, 5, 1, do_nand, \
+ "nand - NAND sub-system\n", \
+ "info - show available NAND devices\n" \
+ "nand device [dev] - show or set current device\n" \
+ "nand read addr off size\n" \
+ "nand write addr off size - read/write `size'" \
+ " bytes starting at offset `off'\n" \
+ " to/from memory address `addr'\n" \
+ "nand erase off size - erase `size' bytes of NAND from offset `off'\n" \
+),
+
+#define CMD_TBL_NANDBOOT MK_CMD_TBL_ENTRY( \
+ "nboot", 4, 4, 1, do_nandboot, \
+ "nboot - boot from NAND device\n", \
+ "loadAddr dev\n" \
+),
+
+int do_nand (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+int do_nandboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+
+#else
+#define CMD_TBL_NAND
+#define CMD_TBL_NANDBOOT
+#endif
+
+#endif /* _CMD_NAND_H */
diff --git a/include/commproc.h b/include/commproc.h
index 5ff82b7..a7d8dbd 100644
--- a/include/commproc.h
+++ b/include/commproc.h
@@ -1128,6 +1128,57 @@
/*** NETVIA *******************************************************/
+/* SinoVee Microsystems SC8xx series FEL8xx-AT,SC823,SC850,SC855T,SC860T */
+#if ( defined CONFIG_SVM_SC8xx )
+# ifndef CONFIG_FEC_ENET
+
+#define PROFF_ENET PROFF_SCC2
+#define CPM_CR_ENET CPM_CR_CH_SCC2
+#define SCC_ENET 1
+
+ /* Bits in parallel I/O port registers that have to be set/cleared
+ * * * * to configure the pins for SCC2 use.
+ * * * */
+#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
+#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
+#define PA_ENET_RCLK ((ushort)0x0400) /* PA 5 */
+#define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */
+
+#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
+
+#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
+#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
+/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
+ * * * * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
+ * * * */
+#define SICR_ENET_MASK ((uint)0x0000ff00)
+#define SICR_ENET_CLKRT ((uint)0x00003700)
+
+# else /* Use FEC for Fast Ethernet */
+
+#undef SCC_ENET
+#define FEC_ENET
+
+#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
+#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
+#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
+#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
+#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
+#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
+#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
+#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
+#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
+#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
+#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
+#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
+#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
+
+#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
+
+# endif /* CONFIG_FEC_ENET */
+#endif /* CONFIG_SVM_SC8xx */
+
+
#if defined(CONFIG_NETVIA)
/* Bits in parallel I/O port registers that have to be set/cleared
* to configure the pins for SCC2 use.
diff --git a/include/configs/at91rm9200dk.h b/include/configs/at91rm9200dk.h
new file mode 100644
index 0000000..6315f0a
--- /dev/null
+++ b/include/configs/at91rm9200dk.h
@@ -0,0 +1,153 @@
+/*
+ * Rick Bronson <rick@efn.org>
+ *
+ * Configuation settings for the AT91RM9200DK board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* ARM asynchronous clock */
+#define AT91C_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal (18432000 / 4 * 39) */
+#define AT91C_MASTER_CLOCK 59904000 /* peripheral clock (AT91C_MASTER_CLOCK / 3) */
+
+#define CONFIG_AT91RM9200DK 1 /* on an AT91RM9200DK Board */
+#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
+#define CONFIG_BAUDRATE 115200
+/*
+ * Hardware drivers
+ */
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_SERIAL3 1 /* we use SERIAL 3 */
+
+#undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */
+
+#undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */
+
+#define CONFIG_COMMANDS \
+ (CONFIG_CMD_DFL | \
+ CFG_CMD_DHCP | \
+ CFG_CMD_NAND )
+/* CFG_CMD_EEPROM | \ might consider these
+ CFG_CMD_I2C | \
+ CFG_CMD_USB | \
+ CFG_CMD_MII | \
+ CFG_CMD_SDRAM | \ */
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
+#define SECTORSIZE 512
+
+#define ADDR_COLUMN 1
+#define ADDR_PAGE 2
+#define ADDR_COLUMN_PAGE 3
+
+#define NAND_ChipID_UNKNOWN 0x00
+#define NAND_MAX_FLOORS 1
+#define NAND_MAX_CHIPS 1
+
+#define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */
+#define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */
+
+#define NAND_DISABLE_CE(nand) do { *AT91C_PIOC_SODR = AT91C_PIO_PC0;} while(0)
+#define NAND_ENABLE_CE(nand) do { *AT91C_PIOC_CODR = AT91C_PIO_PC0;} while(0)
+
+#define NAND_WAIT_READY(nand) while (!(*AT91C_PIOC_PDSR & AT91C_PIO_PC2))
+
+#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_CLE) = (__u8)(d); } while(0)
+#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_ALE) = (__u8)(d); } while(0)
+#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
+#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
+/* the following are NOP's in our implementation */
+#define NAND_CTL_CLRALE(nandptr)
+#define NAND_CTL_SETALE(nandptr)
+#define NAND_CTL_CLRCLE(nandptr)
+#define NAND_CTL_SETCLE(nandptr)
+
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM 0x20000000
+#define PHYS_SDRAM_SIZE 0x2000000 /* 32 megs */
+
+#define CFG_MEMTEST_START PHYS_SDRAM
+#define CFG_MEMTEST_END CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 262144
+
+#define CONFIG_DRIVER_ETHER
+
+#define PHYS_FLASH_1 0x10000000
+#define PHYS_FLASH_SIZE 0x200000 /* 2 megs main flash */
+#define CFG_FLASH_BASE PHYS_FLASH_1
+#define CFG_MAX_FLASH_BANKS 1
+#define CFG_MAX_FLASH_SECT 40
+#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0xe000)
+#define CFG_ENV_SIZE 0x2000
+#define CFG_LOAD_ADDR 0x21000000 /* default load address */
+
+#define CFG_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
+
+#define CFG_PROMPT "Uboot> " /* Monitor Command Prompt */
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+
+#ifndef __ASSEMBLY__
+/*-----------------------------------------------------------------------
+ * Board specific extension for bd_info
+ *
+ * This structure is embedded in the global bd_info (bd_t) structure
+ * and can be used by the board specific code (eg board/...)
+ */
+
+struct bd_info_ext
+{
+ /* helper variable for board environment handling
+ *
+ * env_crc_valid == 0 => uninitialised
+ * env_crc_valid > 0 => environment crc in flash is valid
+ * env_crc_valid < 0 => environment crc in flash is invalid
+ */
+ int env_crc_valid;
+};
+#endif
+
+#define CFG_HZ AT91C_MASTER_CLOCK/2 /* AT91C_TC0_CMR is implicitly set to
+ AT91C_TC_TIMER_DIV1_CLOCK */
+
+#define CONFIG_STACKSIZE (32*1024) /* regular stack */
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+#endif
diff --git a/include/configs/dnp1110.h b/include/configs/dnp1110.h
index 5a7642b..8594e65 100644
--- a/include/configs/dnp1110.h
+++ b/include/configs/dnp1110.h
@@ -76,7 +76,7 @@
#define CONFIG_NETMASK 255.255.0.0
#define CONFIG_IPADDR 172.22.2.23
#define CONFIG_SERVERIP 172.22.2.22
-#define CONFIG_BOOTFILE "elinos-dnp1110"
+#define CONFIG_BOOTFILE "dnp1110"
#define CONFIG_BOOTCOMMAND "tftp; bootm"
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
@@ -128,21 +128,23 @@
#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
#define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */
+#define PHYS_FLASH_BANK_SIZE 0x01000000 /* 32 MB Banks */
+#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 256 KB sectors (x2) */
#define CFG_FLASH_BASE PHYS_FLASH_1
/*-----------------------------------------------------------------------
* FLASH and environment organization
*/
-#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CFG_MAX_FLASH_SECT (31+8) /* max number of sectors on one chip */
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
/* timeout values are in ticks */
#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */
#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */
#define CFG_ENV_IS_IN_FLASH 1
-#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x1C000) /* Addr of Environment Sector */
-#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
+#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0xF80000) /* Addr of Environment Sector */
+#define CFG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */
#endif /* __CONFIG_H */
diff --git a/include/configs/svm_sc8xx.h b/include/configs/svm_sc8xx.h
new file mode 100644
index 0000000..b46b0be
--- /dev/null
+++ b/include/configs/svm_sc8xx.h
@@ -0,0 +1,470 @@
+/*
+ * (C) Copyright 2000, 2001, 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific,
+ * for SinoVee Microsystems SC8xx series SBC
+ * http://www.fel.com.cn (Chinese)
+ * http://www.sinovee.com (English)
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* Custom configuration */
+/* SC823,SC850,SC860SAR, FEL8xx-AT(823/850/860) */
+/* SC85T,SC860T, FEL8xx-AT(855T/860T) */
+/*#define CONFIG_FEL8xx_AT */
+/*#define CONFIG_LCD */
+/* if core > 50MHz , un-comment CONFIG_BUS_DIV2 */
+/* #define CONFIG_50MHz */
+/* #define CONFIG_66MHz */
+/* #define CONFIG_75MHz */
+#define CONFIG_80MHz
+/*#define CONFIG_100MHz */
+/* #define CONFIG_BUS_DIV2 1 */
+/* for BOOT device port size */
+/* #define CONFIG_BOOT_8B */
+#define CONFIG_BOOT_16B
+/* #define CONFIG_BOOT_32B */
+/* #define CONFIG_CAN_DRIVER */
+/* #define DEBUG */
+#define CONFIG_FEC_ENET
+
+/* #define CONFIG_SDRAM_16M */
+#define CONFIG_SDRAM_32M
+/* #define CONFIG_SDRAM_64M */
+#define CFG_RESET_ADDRESS 0xffffffff
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+/* #define CONFIG_MPC823 1 */
+/* #define CONFIG_MPC850 1 */
+#define CONFIG_MPC855 1
+/* #define CONFIG_MPC860 1 */
+/* #define CONFIG_MPC860T 1 */
+
+#undef CONFIG_WATCHDOG /* watchdog */
+
+#define CONFIG_SVM_SC8xx 1 /* ...on SVM SC8xx series */
+
+#ifdef CONFIG_LCD /* with LCD controller ? */
+/* #define CONFIG_NEC_NL6648BC20 1 / * use NEC NL6648BC20 display */
+#endif
+
+#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
+#undef CONFIG_8xx_CONS_SMC2
+#undef CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE 19200 /* console baudrate = 115kbps */
+#if 0
+#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
+#else
+#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
+#endif
+
+#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
+
+#define CONFIG_BOARD_TYPES 1 /* support board types */
+
+#define CONFIG_PREBOOT "echo;echo Welcome to U-Boot SVM port;echo;echo Type \"? or help\" to get on-line help;echo"
+
+#undef CONFIG_BOOTARGS
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$(serverip):$(rootpath)\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs $(bootargs) " \
+ "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
+ ":$(hostname):$(netdev):off panic=1\0" \
+ "flash_nfs=run nfsargs addip;" \
+ "bootm $(kernel_addr)\0" \
+ "flash_self=run ramargs addip;" \
+ "bootm $(kernel_addr) $(ramdisk_addr)\0" \
+ "net_nfs=tftp 0x210000 $(bootfile);run nfsargs addip;bootm\0" \
+ "rootpath=/opt/sinovee/ppc8xx-linux-2.0/target\0" \
+ "bootfile=pImage-sc855t\0" \
+ "kernel_addr=48000000\0" \
+ "ramdisk_addr=48100000\0" \
+ ""
+#define CONFIG_BOOTCOMMAND \
+ "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
+ "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
+ "tftpboot 0x210000 pImage-sc855t;bootm 0x210000"
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
+
+
+#ifdef CONFIG_LCD
+# undef CONFIG_STATUS_LED /* disturbs display */
+#else
+# define CONFIG_STATUS_LED 1 /* Status LED enabled */
+#endif /* CONFIG_LCD */
+
+#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
+
+#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
+
+#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
+ CFG_CMD_ASKENV | \
+ CFG_CMD_DHCP | \
+ CFG_CMD_DOC | \
+/* CFG_CMD_IDE |*/ \
+ CFG_CMD_DATE )
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR 0xFF000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR CFG_IMMR
+#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
+#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_FLASH_BASE 0x40000000
+#define CFG_MONITOR_LEN (384 << 10) /* Reserve 192 kB for Monitor */
+#define CFG_MONITOR_BASE CFG_FLASH_BASE
+#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
+
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+#define CFG_ENV_IS_IN_FLASH 1
+
+#ifdef CONFIG_BOOT_8B
+#define CFG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */
+#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
+#elif defined (CONFIG_BOOT_16B)
+#define CFG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */
+#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
+#elif defined (CONFIG_BOOT_32B)
+#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
+#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
+#endif
+
+/* Address and size of Redundant Environment Sector */
+#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+
+
+/*-----------------------------------------------------------------------
+ * Hardware Information Block
+ */
+#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
+#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
+#define CFG_HWINFO_MAGIC 0x46454C38 /* 'SVM8' */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control 11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+/*#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+ SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
+*/
+#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_SWF | \
+ SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR 0xffffff88
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration 11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#ifndef CONFIG_CAN_DRIVER
+/*#define CFG_SIUMCR 0x00610c00 */
+#define CFG_SIUMCR 0x00000000
+#else /* we must activate GPL5 in the SIUMCR for CAN */
+#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#endif /* CONFIG_CAN_DRIVER */
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control 11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR 0x0001
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register 11-27
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RTCSC 0x00c3
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control 11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR 0x0000
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ */
+#if defined (CONFIG_100MHz)
+#define CFG_PLPRCR 0x06301000
+#define CONFIG_8xx_GCLK_FREQ 100000000
+#elif defined (CONFIG_80MHz)
+#define CFG_PLPRCR 0x04f01000
+#define CONFIG_8xx_GCLK_FREQ 80000000
+#elif defined(CONFIG_75MHz)
+#define CFG_PLPRCR 0x04a00100
+#define CONFIG_8xx_GCLK_FREQ 75000000
+#elif defined(CONFIG_66MHz)
+#define CFG_PLPRCR 0x04101000
+#define CONFIG_8xx_GCLK_FREQ 66000000
+#elif defined(CONFIG_50MHz)
+#define CFG_PLPRCR 0x03101000
+#define CONFIG_8xx_GCLK_FREQ 50000000
+#endif
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register 15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK SCCR_EBDF11
+#ifdef CONFIG_BUS_DIV2
+#define CFG_SCCR 0x02020000 | SCCR_RTSEL
+#else /* up to 50 MHz we use a 1:1 clock */
+#define CFG_SCCR 0x02000000 | SCCR_RTSEL
+#endif
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
+#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
+#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
+#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
+#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
+#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
+#define CFG_PCMCIA_IO_ADDR (0xEC000000)
+#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
+
+#define CONFIG_IDE_8xx_DIRECT 1 /* Direct IDE not supported */
+#undef CONFIG_IDE_LED /* LED for ide not supported */
+#undef CONFIG_IDE_RESET /* reset for ide not supported */
+
+#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
+#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
+
+#define CFG_ATA_BASE_ADDR 0xFE100010
+#define CFG_ATA_IDE0_OFFSET 0x0000
+/*#define CFG_ATA_IDE1_OFFSET 0x0C00 */
+#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O
+ */
+#define CFG_ATA_REG_OFFSET 0x0200 /* Offset for normal register accesses
+ */
+#define CFG_ATA_ALT_OFFSET 0x0210 /* Offset for alternate registers
+ */
+#define CONFIG_ATAPI
+#define CFG_PIO_MODE 0
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+/*#define CFG_DER 0x2002000F*/
+#define CFG_DER 0x0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
+#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
+#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
+
+/*
+ * FLASH timing:
+ */
+#if defined(CONFIG_100MHz)
+#define CFG_OR_TIMING_FLASH 0x000002f4
+#define CFG_OR_TIMING_DOC 0x000002f4
+#define CFG_MxMR_PTx 0x61000000
+#define CFG_MPTPR 0x400
+
+#elif defined(CONFIG_80MHz)
+#define CFG_OR_TIMING_FLASH 0x00000ff4
+#define CFG_OR_TIMING_DOC 0x000001f4
+#define CFG_MxMR_PTx 0x4e000000
+#define CFG_MPTPR 0x400
+
+#elif defined(CONFIG_75MHz)
+#define CFG_OR_TIMING_FLASH 0x000008f4
+#define CFG_OR_TIMING_DOC 0x000002f4
+#define CFG_MxMR_PTx 0x49000000
+#define CFG_MPTPR 0x400
+
+#elif defined(CONFIG_66MHz)
+#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
+ OR_SCY_3_CLK | OR_EHTR | OR_BI)
+/*#define CFG_OR_TIMING_FLASH 0x000001f4 */
+#define CFG_OR_TIMING_DOC 0x000003f4
+#define CFG_MxMR_PTx 0x40000000
+#define CFG_MPTPR 0x400
+
+#else /* 50 MHz */
+#define CFG_OR_TIMING_FLASH 0x00000ff4
+#define CFG_OR_TIMING_DOC 0x000001f4
+#define CFG_MxMR_PTx 0x30000000
+#define CFG_MPTPR 0x400
+#endif /*CONFIG_??MHz */
+
+
+#if defined (CONFIG_BOOT_8B) /* 512K X 8 ,29F040 , 2MB space */
+#define CFG_OR0_PRELIM (0xffe00000 | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_8)
+#elif defined (CONFIG_BOOT_16B) /* 29lv160 X 16 , 4MB space */
+#define CFG_OR0_PRELIM (0xffc00000 | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_16)
+#elif defined( CONFIG_BOOT_32B ) /* 29lv160 X 2 X 32, 4/8/16MB , 64MB space */
+#define CFG_OR0_PRELIM (0xfc000000 | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+#else
+#error Boot device port size missing.
+#endif
+
+/*
+ * Disk-On-Chip configuration
+ */
+
+#define CFG_DOC_SHORT_TIMEOUT
+#define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
+
+#define CFG_DOC_SUPPORT_2000
+#define CFG_DOC_SUPPORT_MILLENNIUM
+#define CFG_DOC_BASE 0x80000000
+
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#endif /* __CONFIG_H */
diff --git a/include/flash.h b/include/flash.h
index b4c8bad..b7f13d3 100644
--- a/include/flash.h
+++ b/include/flash.h
@@ -105,6 +105,7 @@
#define AMD_MANUFACT 0x00010001 /* AMD manuf. ID in D23..D16, D7..D0 */
#define FUJ_MANUFACT 0x00040004 /* FUJITSU manuf. ID in D23..D16, D7..D0 */
+#define ATM_MANUFACT 0x001F001F /* ATMEL */
#define STM_MANUFACT 0x00200020 /* STM (Thomson) manuf. ID in D23.. -"- */
#define SST_MANUFACT 0x00BF00BF /* SST manuf. ID in D23..D16, D7..D0 */
#define MT_MANUFACT 0x00890089 /* MT manuf. ID in D23..D16, D7..D0 */
@@ -156,6 +157,8 @@
#define AMD_ID_DL640 0x227E227E /* 29DL640D ID (64 M, dual boot sectors)*/
#define AMD_ID_LV640U 0x22D722D7 /* 29LV640U ID (64 M, uniform sectors) */
+#define ATM_ID_BV1614 0x000000C0 /* 49BV1614 ID */
+
#define FUJI_ID_29F800BA 0x22582258 /* MBM29F800BA ID (8M) */
#define FUJI_ID_29F800TA 0x22D622D6 /* MBM29F800TA ID (8M) */
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index a3a7ec3..4425187 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -1,10 +1,11 @@
/*
- * u-boot/include/linux/mtd/nand.h
+ * linux/include/linux/mtd/nand.h
*
* Copyright (c) 2000 David Woodhouse <dwmw2@mvhi.com>
* Steven J. Hill <sjhill@cotw.com>
+ * Thomas Gleixner <gleixner@autronix.de>
*
- * $Id: nand.h,v 1.8 2000/10/30 17:16:17 sjhill Exp $
+ * $Id: nand.h,v 1.13 2002/04/28 13:40:41 gleixner Exp $
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@@ -23,6 +24,14 @@
* bat later if I did something naughty.
* 10-11-2000 SJH Added private NAND flash structure for driver
* 10-24-2000 SJH Added prototype for 'nand_scan' function
+ * 10-29-2001 TG changed nand_chip structure to support
+ * hardwarespecific function for accessing control lines
+ * 02-21-2002 TG added support for different read/write adress and
+ * ready/busy line access function
+ * 02-26-2002 TG added chip_delay to nand_chip structure to optimize
+ * command delay times for different chips
+ * 04-28-2002 TG OOB config defines moved from nand.c to avoid duplicate
+ * defines in jffs2/wbuf.c
*/
#ifndef __LINUX_MTD_NAND_H
#define __LINUX_MTD_NAND_H
@@ -42,6 +51,82 @@
#define NAND_CMD_RESET 0xff
/*
+ * Enumeration for NAND flash chip state
+ */
+typedef enum {
+ FL_READY,
+ FL_READING,
+ FL_WRITING,
+ FL_ERASING,
+ FL_SYNCING
+} nand_state_t;
+
+
+/*
+ * NAND Private Flash Chip Data
+ *
+ * Structure overview:
+ *
+ * IO_ADDR - address to access the 8 I/O lines of the flash device
+ *
+ * hwcontrol - hardwarespecific function for accesing control-lines
+ *
+ * dev_ready - hardwarespecific function for accesing device ready/busy line
+ *
+ * chip_lock - spinlock used to protect access to this structure
+ *
+ * wq - wait queue to sleep on if a NAND operation is in progress
+ *
+ * state - give the current state of the NAND device
+ *
+ * page_shift - number of address bits in a page (column address bits)
+ *
+ * data_buf - data buffer passed to/from MTD user modules
+ *
+ * data_cache - data cache for redundant page access and shadow for
+ * ECC failure
+ *
+ * ecc_code_buf - used only for holding calculated or read ECCs for
+ * a page read or written when ECC is in use
+ *
+ * reserved - padding to make structure fall on word boundary if
+ * when ECC is in use
+ */
+struct Nand {
+ char floor, chip;
+ unsigned long curadr;
+ unsigned char curmode;
+ /* Also some erase/write/pipeline info when we get that far */
+};
+
+struct nand_chip {
+ int page_shift;
+ u_char *data_buf;
+ u_char *data_cache;
+ int cache_page;
+ u_char ecc_code_buf[6];
+ u_char reserved[2];
+ char ChipID; /* Type of DiskOnChip */
+ struct Nand *chips;
+ int chipshift;
+ char* chips_name;
+ unsigned long erasesize;
+ unsigned long mfr; /* Flash IDs - only one type of flash per device */
+ unsigned long id;
+ char* name;
+ struct NFTLrecord nftl;
+ int nftl_found;
+ int numchips;
+ char page256;
+ char pageadrlen;
+ unsigned long IO_ADDR; /* address to access the 8 I/O lines to the flash device */
+ unsigned long totlen;
+ uint oobblock; // Size of OOB blocks (e.g. 512)
+ uint oobsize; // Amount of OOB data per block (e.g. 16)
+ uint eccsize;
+};
+
+/*
* NAND Flash Manufacturer ID Codes
*/
#define NAND_MFR_TOSHIBA 0x98
@@ -84,4 +169,30 @@
unsigned long erasesize;
};
+/*
+* Constants for oob configuration
+*/
+#define NAND_NOOB_ECCPOS0 0
+#define NAND_NOOB_ECCPOS1 1
+#define NAND_NOOB_ECCPOS2 2
+#define NAND_NOOB_ECCPOS3 3
+#define NAND_NOOB_ECCPOS4 4
+#define NAND_NOOB_ECCPOS5 5
+#define NAND_NOOB_BADBPOS -1
+#define NAND_NOOB_ECCVPOS -1
+
+#define NAND_JFFS2_OOB_ECCPOS0 0
+#define NAND_JFFS2_OOB_ECCPOS1 1
+#define NAND_JFFS2_OOB_ECCPOS2 2
+#define NAND_JFFS2_OOB_ECCPOS3 3
+#define NAND_JFFS2_OOB_ECCPOS4 6
+#define NAND_JFFS2_OOB_ECCPOS5 7
+#define NAND_JFFS2_OOB_BADBPOS 5
+#define NAND_JFFS2_OOB_ECCVPOS 4
+
+#define NAND_JFFS2_OOB8_FSDAPOS 6
+#define NAND_JFFS2_OOB16_FSDAPOS 8
+#define NAND_JFFS2_OOB8_FSDALEN 2
+#define NAND_JFFS2_OOB16_FSDALEN 8
+
#endif /* __LINUX_MTD_NAND_H */
diff --git a/include/pcmcia.h b/include/pcmcia.h
index beb1c16..16653f3 100644
--- a/include/pcmcia.h
+++ b/include/pcmcia.h
@@ -48,7 +48,7 @@
# else
# define CONFIG_PCMCIA_SLOT_B
# endif
-#elif defined(CONFIG_TQM8xxL)
+#elif defined(CONFIG_TQM8xxL) || defined(CONFIG_SVM_SC8xx)
# define CONFIG_PCMCIA_SLOT_B /* The TQM8xxL use SLOT_B */
#elif defined(CONFIG_SPD823TS) /* The SPD8xx use SLOT_B */
# define CONFIG_PCMCIA_SLOT_B
diff --git a/include/status_led.h b/include/status_led.h
index 369cce2..79d9fb4 100644
--- a/include/status_led.h
+++ b/include/status_led.h
@@ -269,6 +269,20 @@
# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
+#elif defined(CONFIG_SVM_SC8xx)
+# define STATUS_LED_PAR im_cpm.cp_pbpar
+# define STATUS_LED_DIR im_cpm.cp_pbdir
+# define STATUS_LED_ODR im_cpm.cp_pbodr
+# define STATUS_LED_DAT im_cpm.cp_pbdat
+
+# define STATUS_LED_BIT 0x00000001
+# define STATUS_LED_PERIOD (CFG_HZ / 2)
+# define STATUS_LED_STATE STATUS_LED_BLINKING
+
+# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
+
+# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
+
/************************************************************************/
#else
# error Status LED configuration missing