| commit | da91cfed54ec44d88f93af2adfbdeada8ab4403e | [log] [tgz] |
|---|---|---|
| author | Stefan Agner <stefan.agner@toradex.com> | Wed Aug 03 13:08:55 2016 -0700 |
| committer | Tom Rini <trini@konsulko.com> | Fri Aug 12 09:22:15 2016 -0400 |
| tree | 0f33c7db11beb3a000cf119a7b8905b2597fbec0 | |
| parent | 2651a052d8ab13a8609c51053ba0f693f1be3295 [diff] |
ARM: non-sec: flush code cacheline aligned Flush operations need to be cacheline aligned to take effect, make sure to flush always complete cachelines. This avoids messages such as: CACHE: Misaligned operation at range [00900000, 009004d9] Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Tested-by: Fabio Estevam <fabio.estevam@nxp.com>