Tegra: Fix MSELECT clock divisors for T30/T114.
A comparison of registers between our internal NV U-Boot and
u-boot-tegra/next showed some discrepancies in the MSELECT
clock divisor programming. T20 doesn't have a MSELECT clk src reg.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
diff --git a/arch/arm/cpu/arm720t/tegra30/cpu.c b/arch/arm/cpu/arm720t/tegra30/cpu.c
index dedcdd9..e162357 100644
--- a/arch/arm/cpu/arm720t/tegra30/cpu.c
+++ b/arch/arm/cpu/arm720t/tegra30/cpu.c
@@ -110,8 +110,8 @@
reset_set_enable(PERIPH_ID_MSELECT, 1);
clock_set_enable(PERIPH_ID_MSELECT, 1);
- /* Switch MSELECT clock to PLLP (00) */
- clock_ll_set_source(PERIPH_ID_MSELECT, 0);
+ /* Switch MSELECT clock to PLLP (00) and use a divisor of 2 */
+ clock_ll_set_source_divisor(PERIPH_ID_MSELECT, 0, 2);
/*
* Our high-level clock routines are not available prior to