ARM: DRA72x: Add support for detection of SR2.0
Add support for detection of SR2.0 version of DRA72x family of
processors.
Signed-off-by: Ravi Babu <ravibabu@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
index 7f8c0a4..93d1efb 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -775,6 +775,7 @@
break;
case DRA722_ES1_0:
+ case DRA722_ES2_0:
*prcm = &dra7xx_prcm;
*dplls_data = &dra72x_dplls;
*omap_vcores = &dra722_volts;
@@ -807,6 +808,7 @@
*regs = &ioregs_dra7xx_es1;
break;
case DRA722_ES1_0:
+ case DRA722_ES2_0:
*regs = &ioregs_dra72x_es1;
break;
diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c
index 8f184df..e3ac8bb 100644
--- a/arch/arm/cpu/armv7/omap5/hwinit.c
+++ b/arch/arm/cpu/armv7/omap5/hwinit.c
@@ -373,6 +373,9 @@
case DRA722_CONTROL_ID_CODE_ES1_0:
*omap_si_rev = DRA722_ES1_0;
break;
+ case DRA722_CONTROL_ID_CODE_ES2_0:
+ *omap_si_rev = DRA722_ES2_0;
+ break;
default:
*omap_si_rev = OMAP5430_SILICON_ID_INVALID;
}
diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c
index 7dc5bb7..5cf360c 100644
--- a/arch/arm/cpu/armv7/omap5/sdram.c
+++ b/arch/arm/cpu/armv7/omap5/sdram.c
@@ -438,6 +438,7 @@
}
break;
case DRA722_ES1_0:
+ case DRA722_ES2_0:
*regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz;
*size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz);
break;
@@ -670,6 +671,7 @@
case DRA752_ES1_1:
case DRA752_ES2_0:
case DRA722_ES1_0:
+ case DRA722_ES2_0:
bug_00339_regs_ptr = dra_bug_00339_regs;
*iterations = sizeof(dra_bug_00339_regs)/
sizeof(dra_bug_00339_regs[0]);